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GET /api/patches/65518/?format=api
{ "id": 65518, "url": "http://patches.dpdk.org/api/patches/65518/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1580815045-32132-8-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1580815045-32132-8-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1580815045-32132-8-git-send-email-anoobj@marvell.com", "date": "2020-02-04T11:17:17", "name": "[v4,07/15] crypto/octeontx2: enable CPT to share QP with ethdev", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "31fd7caee0e5dc19716b34f34f57e0f00c59f42c", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1580815045-32132-8-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 8411, "url": "http://patches.dpdk.org/api/series/8411/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8411", "date": "2020-02-04T11:17:10", "name": "add OCTEON TX2 inline IPsec support", "version": 4, "mbox": "http://patches.dpdk.org/series/8411/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65518/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65518/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DD7CEA0532;\n\tTue, 4 Feb 2020 12:19:23 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B51931C0B9;\n\tTue, 4 Feb 2020 12:18:49 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3495C1C12C\n for <dev@dpdk.org>; Tue, 4 Feb 2020 12:18:48 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 014BFlgL011400; Tue, 4 Feb 2020 03:18:47 -0800", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 2xw9qukg20-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 04 Feb 2020 03:18:47 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Feb\n 2020 03:18:45 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 4 Feb 2020 03:18:45 -0800", "from ajoseph83.caveonetworks.com (unknown [10.29.45.60])\n by maili.marvell.com (Postfix) with ESMTP id E18923F7079;\n Tue, 4 Feb 2020 03:18:40 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=jvdvZOZB9YURz1OccB2WBp0vrAzf+/AND4gDnYuzdYA=;\n b=hz+NQbUx2GsL1AwHOGvxun4c6c5a3D8Fw4GvZcWEj7mywetWlDVRrCfIzT/qMP1yBo1s\n 1j/kpbyRjJ+EpTFs04U/L+1nxDTK+G2cOSZ3MCVIslARhuWkHwAjLor99Z28ssGC5zOP\n Hst0TORCbHZE6EGinwenJWLNS9qgYu0ZbhWb3Eb67EJOmcqsBdbHLR0IGVcm6JUumjM0\n BJRgZguRUAyarsRzaGoJ9rzngZojqhpnIdk/6HtNmoXoML304L7dZa7NZ02u0tVmMpEv\n X0O6GiCsQ39rVm+1nhWo6RWsOkFfichC6LItpjJwqeOe1+IRhTtC/tY/4yuern4qncDn MQ==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Declan Doherty\n <declan.doherty@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Narayana Prasad <pathreya@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Ankur Dwivedi\n <adwivedi@marvell.com>, Archana Muniganti <marchana@marvell.com>, Tejasree\n Kondoj <ktejasree@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>,\n \"Lukasz Bartosik\" <lbartosik@marvell.com>, <dev@dpdk.org>", "Date": "Tue, 4 Feb 2020 16:47:17 +0530", "Message-ID": "<1580815045-32132-8-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1580815045-32132-1-git-send-email-anoobj@marvell.com>", "References": "<1580465035-30455-1-git-send-email-anoobj@marvell.com>\n <1580815045-32132-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-02-04_02:2020-02-04,\n 2020-02-04 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 07/15] crypto/octeontx2: enable CPT to share\n\tQP with ethdev", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding the infrastructure to save one opaque pointer in idev and\nimplement the consumer-producer in the PMDs which uses it accordingly.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/common/octeontx2/otx2_sec_idev.c | 92 ++++++++++++++++++++++\n drivers/common/octeontx2/otx2_sec_idev.h | 21 +++++\n .../octeontx2/rte_common_octeontx2_version.map | 3 +\n .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 22 +-----\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 17 ++++\n drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 35 ++++++++\n drivers/net/octeontx2/otx2_ethdev_sec.c | 9 +++\n 7 files changed, 178 insertions(+), 21 deletions(-)\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_qp.h", "diff": "diff --git a/drivers/common/octeontx2/otx2_sec_idev.c b/drivers/common/octeontx2/otx2_sec_idev.c\nindex 532abde..e924078 100644\n--- a/drivers/common/octeontx2/otx2_sec_idev.c\n+++ b/drivers/common/octeontx2/otx2_sec_idev.c\n@@ -2,12 +2,16 @@\n * Copyright(C) 2020 Marvell International Ltd.\n */\n \n+#include <rte_atomic.h>\n #include <rte_bus_pci.h>\n #include <rte_ethdev.h>\n+#include <rte_spinlock.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_sec_idev.h\"\n \n+static struct otx2_sec_idev_cfg sec_cfg[OTX2_MAX_INLINE_PORTS];\n+\n /**\n * @internal\n * Check if rte_eth_dev is security offload capable otx2_eth_dev\n@@ -26,3 +30,91 @@ otx2_eth_dev_is_sec_capable(struct rte_eth_dev *eth_dev)\n \n \treturn 0;\n }\n+\n+int\n+otx2_sec_idev_cfg_init(int port_id)\n+{\n+\tstruct otx2_sec_idev_cfg *cfg;\n+\tint i;\n+\n+\tcfg = &sec_cfg[port_id];\n+\tcfg->tx_cpt_idx = 0;\n+\trte_spinlock_init(&cfg->tx_cpt_lock);\n+\n+\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n+\t\tcfg->tx_cpt[i].qp = NULL;\n+\t\trte_atomic16_set(&cfg->tx_cpt[i].ref_cnt, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_sec_idev_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp)\n+{\n+\tstruct otx2_sec_idev_cfg *cfg;\n+\tint i, ret;\n+\n+\tif (qp == NULL || port_id > OTX2_MAX_INLINE_PORTS)\n+\t\treturn -EINVAL;\n+\n+\tcfg = &sec_cfg[port_id];\n+\n+\t/* Find a free slot to save CPT LF */\n+\n+\trte_spinlock_lock(&cfg->tx_cpt_lock);\n+\n+\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n+\t\tif (cfg->tx_cpt[i].qp == NULL) {\n+\t\t\tcfg->tx_cpt[i].qp = qp;\n+\t\t\tret = 0;\n+\t\t\tgoto unlock;\n+\t\t}\n+\t}\n+\n+\tret = -EINVAL;\n+\n+unlock:\n+\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n+\treturn ret;\n+}\n+\n+int\n+otx2_sec_idev_tx_cpt_qp_remove(struct otx2_cpt_qp *qp)\n+{\n+\tstruct otx2_sec_idev_cfg *cfg;\n+\tuint16_t port_id;\n+\tint i, ret;\n+\n+\tif (qp == NULL)\n+\t\treturn -EINVAL;\n+\n+\tfor (port_id = 0; port_id < OTX2_MAX_INLINE_PORTS; port_id++) {\n+\t\tcfg = &sec_cfg[port_id];\n+\n+\t\trte_spinlock_lock(&cfg->tx_cpt_lock);\n+\n+\t\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n+\t\t\tif (cfg->tx_cpt[i].qp != qp)\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Don't free if the QP is in use by any sec session */\n+\t\t\tif (rte_atomic16_read(&cfg->tx_cpt[i].ref_cnt)) {\n+\t\t\t\tret = -EBUSY;\n+\t\t\t} else {\n+\t\t\t\tcfg->tx_cpt[i].qp = NULL;\n+\t\t\t\tret = 0;\n+\t\t\t}\n+\n+\t\t\tgoto unlock;\n+\t\t}\n+\n+\t\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n+\t}\n+\n+\treturn -ENOENT;\n+\n+unlock:\n+\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n+\treturn ret;\n+}\ndiff --git a/drivers/common/octeontx2/otx2_sec_idev.h b/drivers/common/octeontx2/otx2_sec_idev.h\nindex a5d929e..20d71d0 100644\n--- a/drivers/common/octeontx2/otx2_sec_idev.h\n+++ b/drivers/common/octeontx2/otx2_sec_idev.h\n@@ -7,6 +7,27 @@\n \n #include <rte_ethdev.h>\n \n+#define OTX2_MAX_CPT_QP_PER_PORT 64\n+#define OTX2_MAX_INLINE_PORTS 64\n+\n+struct otx2_cpt_qp;\n+\n+struct otx2_sec_idev_cfg {\n+\tstruct {\n+\t\tstruct otx2_cpt_qp *qp;\n+\t\trte_atomic16_t ref_cnt;\n+\t} tx_cpt[OTX2_MAX_CPT_QP_PER_PORT];\n+\n+\tuint16_t tx_cpt_idx;\n+\trte_spinlock_t tx_cpt_lock;\n+};\n+\n uint8_t otx2_eth_dev_is_sec_capable(struct rte_eth_dev *eth_dev);\n \n+int otx2_sec_idev_cfg_init(int port_id);\n+\n+int otx2_sec_idev_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp);\n+\n+int otx2_sec_idev_tx_cpt_qp_remove(struct otx2_cpt_qp *qp);\n+\n #endif /* _OTX2_SEC_IDEV_H_ */\ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex 724fa35..775aca8 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -28,6 +28,9 @@ DPDK_20.0 {\n \totx2_npa_pf_func_get;\n \totx2_npa_set_defaults;\n \totx2_register_irq;\n+\totx2_sec_idev_cfg_init;\n+\totx2_sec_idev_tx_cpt_qp_add;\n+\totx2_sec_idev_tx_cpt_qp_remove;\n \totx2_sso_pf_func_get;\n \totx2_sso_pf_func_set;\n \totx2_unregister_irq;\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex 6f78aa4..43db6a6 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -15,6 +15,7 @@\n #include \"cpt_mcode_defines.h\"\n \n #include \"otx2_dev.h\"\n+#include \"otx2_cryptodev_qp.h\"\n \n /* CPT instruction queue length */\n #define OTX2_CPT_IQ_LEN\t\t\t8200\n@@ -135,27 +136,6 @@ enum cpt_9x_comp_e {\n \tCPT_9X_COMP_E_LAST_ENTRY = 0x06\n };\n \n-struct otx2_cpt_qp {\n-\tuint32_t id;\n-\t/**< Queue pair id */\n-\tuintptr_t base;\n-\t/**< Base address where BAR is mapped */\n-\tvoid *lmtline;\n-\t/**< Address of LMTLINE */\n-\trte_iova_t lf_nq_reg;\n-\t/**< LF enqueue register address */\n-\tstruct pending_queue pend_q;\n-\t/**< Pending queue */\n-\tstruct rte_mempool *sess_mp;\n-\t/**< Session mempool */\n-\tstruct rte_mempool *sess_mp_priv;\n-\t/**< Session private data mempool */\n-\tstruct cpt_qp_meta_info meta_info;\n-\t/**< Metabuf info required to support operations on the queue pair */\n-\trte_iova_t iq_dma_addr;\n-\t/**< Instruction queue address */\n-};\n-\n void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);\n \n int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 005b0a9..7eebb49 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -149,6 +149,11 @@ otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n \tif (ret)\n \t\treturn ret;\n \n+\t/* Publish inline Tx QP to eth dev security */\n+\tret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn 0;\n }\n \n@@ -243,6 +248,12 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \n \tqp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);\n \n+\tret = otx2_sec_idev_tx_cpt_qp_remove(qp);\n+\tif (ret && (ret != -ENOENT)) {\n+\t\tCPT_LOG_ERR(\"Could not delete inline configuration\");\n+\t\tgoto mempool_destroy;\n+\t}\n+\n \totx2_cpt_iq_disable(qp);\n \n \tret = otx2_cpt_qp_inline_cfg(dev, qp);\n@@ -276,6 +287,12 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n \tchar name[RTE_MEMZONE_NAMESIZE];\n \tint ret;\n \n+\tret = otx2_sec_idev_tx_cpt_qp_remove(qp);\n+\tif (ret && (ret != -ENOENT)) {\n+\t\tCPT_LOG_ERR(\"Could not delete inline configuration\");\n+\t\treturn ret;\n+\t}\n+\n \totx2_cpt_iq_disable(qp);\n \n \totx2_cpt_metabuf_mempool_destroy(qp);\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\nnew file mode 100644\nindex 0000000..9d48da4\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n@@ -0,0 +1,35 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_QP_H_\n+#define _OTX2_CRYPTODEV_QP_H_\n+\n+#include <rte_common.h>\n+#include <rte_mempool.h>\n+#include <rte_spinlock.h>\n+\n+#include \"cpt_common.h\"\n+\n+struct otx2_cpt_qp {\n+\tuint32_t id;\n+\t/**< Queue pair id */\n+\tuintptr_t base;\n+\t/**< Base address where BAR is mapped */\n+\tvoid *lmtline;\n+\t/**< Address of LMTLINE */\n+\trte_iova_t lf_nq_reg;\n+\t/**< LF enqueue register address */\n+\tstruct pending_queue pend_q;\n+\t/**< Pending queue */\n+\tstruct rte_mempool *sess_mp;\n+\t/**< Session mempool */\n+\tstruct rte_mempool *sess_mp_priv;\n+\t/**< Session private data mempool */\n+\tstruct cpt_qp_meta_info meta_info;\n+\t/**< Metabuf info required to support operations on the queue pair */\n+\trte_iova_t iq_dma_addr;\n+\t/**< Instruction queue address */\n+};\n+\n+#endif /* _OTX2_CRYPTODEV_QP_H_ */\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_sec.c b/drivers/net/octeontx2/otx2_ethdev_sec.c\nindex d0b2dba..8859042 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_sec.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_sec.c\n@@ -10,9 +10,11 @@\n #include <rte_security.h>\n #include <rte_security_driver.h>\n \n+#include \"otx2_cryptodev_qp.h\"\n #include \"otx2_ethdev.h\"\n #include \"otx2_ethdev_sec.h\"\n #include \"otx2_ipsec_fp.h\"\n+#include \"otx2_sec_idev.h\"\n \n #define ETH_SEC_MAX_PKT_LEN\t1450\n \n@@ -160,12 +162,19 @@ int\n otx2_eth_sec_ctx_create(struct rte_eth_dev *eth_dev)\n {\n \tstruct rte_security_ctx *ctx;\n+\tint ret;\n \n \tctx = rte_malloc(\"otx2_eth_sec_ctx\",\n \t\t\t sizeof(struct rte_security_ctx), 0);\n \tif (ctx == NULL)\n \t\treturn -ENOMEM;\n \n+\tret = otx2_sec_idev_cfg_init(eth_dev->data->port_id);\n+\tif (ret) {\n+\t\trte_free(ctx);\n+\t\treturn ret;\n+\t}\n+\n \t/* Populate ctx */\n \n \tctx->device = eth_dev;\n", "prefixes": [ "v4", "07/15" ] }