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GET /api/patches/65514/?format=api
{ "id": 65514, "url": "http://patches.dpdk.org/api/patches/65514/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1580815045-32132-4-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1580815045-32132-4-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1580815045-32132-4-git-send-email-anoobj@marvell.com", "date": "2020-02-04T11:17:13", "name": "[v4,03/15] crypto/octeontx2: configure for inline IPsec", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "10ebe20f11170cd9fd09db7b4d1fe721145e3d68", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1580815045-32132-4-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 8411, "url": "http://patches.dpdk.org/api/series/8411/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8411", "date": "2020-02-04T11:17:10", "name": "add OCTEON TX2 inline IPsec support", "version": 4, "mbox": "http://patches.dpdk.org/series/8411/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65514/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65514/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 843AAA0532;\n\tTue, 4 Feb 2020 12:18:39 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 24C521C0CF;\n\tTue, 4 Feb 2020 12:18:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 285271C0C2\n for <dev@dpdk.org>; Tue, 4 Feb 2020 12:18:25 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 014BFlgG011400; Tue, 4 Feb 2020 03:18:24 -0800", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 2xw9qukg0p-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 04 Feb 2020 03:18:24 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 4 Feb\n 2020 03:18:22 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 4 Feb 2020 03:18:22 -0800", "from ajoseph83.caveonetworks.com (unknown [10.29.45.60])\n by maili.marvell.com (Postfix) with ESMTP id 2F3D23F7068;\n Tue, 4 Feb 2020 03:18:17 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0818;\n bh=t35V2emztThA7vpUbEACDTHurcQnoI8kssdndVTVrq4=;\n b=rjOFbNvzAZ4XzrjOefTioVXS9exT3Z3IelH8Sj+HutN4yQQHmY21pmZmt83mfBpo+9XX\n hixAa8QRNFmObMSAgyCLSSKNhN2GjyJ1aVW5/FkAcrTJclyt7WrqNq45dq6397OQ8j4e\n riD5hxCQAOdjSn6q+DkmvbuBZ1wWyPN/9BUtKsOpd1A6fZU6FpZf3wTISfJ/pk4Q8rwp\n fa1KFcnRo2AaIJdr9fhkTxSn5MN6yRgBhtkJI9ibL4yttLZPrNaHQWEs7/TKGa31nOab\n W/hSaB/EXUbxnhbMGUS5NIZaFsk3Vnc1EgxCV/+KRyib1pRwce0KxOuEzuj89veI2aeq ng==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Declan Doherty\n <declan.doherty@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Tejasree Kondoj <ktejasree@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Narayana Prasad <pathreya@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Ankur Dwivedi\n <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n Archana Muniganti <marchana@marvell.com>,\n Vamsi Attunuru <vattunuru@marvell.com>, Lukasz\n Bartosik <lbartosik@marvell.com>, <dev@dpdk.org>", "Date": "Tue, 4 Feb 2020 16:47:13 +0530", "Message-ID": "<1580815045-32132-4-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1580815045-32132-1-git-send-email-anoobj@marvell.com>", "References": "<1580465035-30455-1-git-send-email-anoobj@marvell.com>\n <1580815045-32132-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-02-04_02:2020-02-04,\n 2020-02-04 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 03/15] crypto/octeontx2: configure for inline\n\tIPsec", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <ktejasree@marvell.com>\n\nFor enabling outbound inline IPsec, a CPT queue needs to be tied\nto a NIX PF_FUNC. Distribute CPT queues fairly among all available\notx2 eth ports.\n\nFor inbound, one CPT LF will be assigned and initialized by kernel.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Archana Muniganti <marchana@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/crypto/octeontx2/Makefile | 3 +-\n drivers/crypto/octeontx2/meson.build | 2 +\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 54 ++++++++++++++++++++++++++\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 7 ++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 39 +++++++++++++++++++\n 5 files changed, 104 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile\nindex f7d6c37..3ba67ed 100644\n--- a/drivers/crypto/octeontx2/Makefile\n+++ b/drivers/crypto/octeontx2/Makefile\n@@ -10,7 +10,7 @@ LIB = librte_pmd_octeontx2_crypto.a\n # build flags\n CFLAGS += $(WERROR_FLAGS)\n \n-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_eal -lrte_ethdev -lrte_mbuf -lrte_mempool -lrte_ring\n LDLIBS += -lrte_cryptodev\n LDLIBS += -lrte_pci -lrte_bus_pci\n LDLIBS += -lrte_common_cpt -lrte_common_octeontx2\n@@ -21,6 +21,7 @@ CFLAGS += -O3\n CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2\n CFLAGS += -DALLOW_EXPERIMENTAL_API\n \n ifneq ($(CONFIG_RTE_ARCH_64),y)\ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nindex b6e5b73..67deca3 100644\n--- a/drivers/crypto/octeontx2/meson.build\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -8,6 +8,7 @@ endif\n deps += ['bus_pci']\n deps += ['common_cpt']\n deps += ['common_octeontx2']\n+deps += ['ethdev']\n name = 'octeontx2_crypto'\n \n allow_experimental_apis = true\n@@ -32,3 +33,4 @@ endforeach\n includes += include_directories('../../common/cpt')\n includes += include_directories('../../common/octeontx2')\n includes += include_directories('../../mempool/octeontx2')\n+includes += include_directories('../../net/octeontx2')\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex b54e407..6bb8316 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -2,10 +2,14 @@\n * Copyright (C) 2019 Marvell International Ltd.\n */\n #include <rte_cryptodev.h>\n+#include <rte_ethdev.h>\n \n #include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_hw_access.h\"\n #include \"otx2_cryptodev_mbox.h\"\n #include \"otx2_dev.h\"\n+#include \"otx2_ethdev.h\"\n+#include \"otx2_sec_idev.h\"\n #include \"otx2_mbox.h\"\n \n #include \"cpt_pmd_logs.h\"\n@@ -173,3 +177,53 @@ otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n \n \treturn otx2_cpt_send_mbox_msg(vf);\n }\n+\n+int\n+otx2_cpt_inline_init(const struct rte_cryptodev *dev)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct cpt_rx_inline_lf_cfg_msg *msg;\n+\tint ret;\n+\n+\tmsg = otx2_mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);\n+\tmsg->sso_pf_func = otx2_sso_pf_func_get();\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\tret = otx2_mbox_process(mbox);\n+\tif (ret < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp,\n+\t\t\tuint16_t port_id)\n+{\n+\tstruct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct cpt_inline_ipsec_cfg_msg *msg;\n+\tstruct otx2_eth_dev *otx2_eth_dev;\n+\tint ret;\n+\n+\tif (!otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))\n+\t\treturn -EINVAL;\n+\n+\totx2_eth_dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tmsg = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);\n+\tmsg->dir = CPT_INLINE_OUTBOUND;\n+\tmsg->enable = 1;\n+\tmsg->slot = qp->id;\n+\n+\tmsg->nix_pf_func = otx2_eth_dev->pf_func;\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\tret = otx2_mbox_process(mbox);\n+\tif (ret < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\nindex a298718..ae66b08 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n@@ -7,6 +7,8 @@\n \n #include <rte_cryptodev.h>\n \n+#include \"otx2_cryptodev_hw_access.h\"\n+\n int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n \t\t\t\t uint16_t *nb_queues);\n \n@@ -22,4 +24,9 @@ int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n \t\t\t uint64_t val);\n \n+int otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev,\n+\t\t\t struct otx2_cpt_qp *qp, uint16_t port_id);\n+\n+int otx2_cpt_inline_init(const struct rte_cryptodev *dev);\n+\n #endif /* _OTX2_CRYPTODEV_MBOX_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex ec0e58d..005b0a9 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -6,6 +6,7 @@\n \n #include <rte_cryptodev_pmd.h>\n #include <rte_errno.h>\n+#include <rte_ethdev.h>\n \n #include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_capabilities.h\"\n@@ -13,6 +14,7 @@\n #include \"otx2_cryptodev_mbox.h\"\n #include \"otx2_cryptodev_ops.h\"\n #include \"otx2_mbox.h\"\n+#include \"otx2_sec_idev.h\"\n \n #include \"cpt_hw_types.h\"\n #include \"cpt_pmd_logs.h\"\n@@ -127,6 +129,29 @@ otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)\n \tmeta_info->sg_mlen = 0;\n }\n \n+static int\n+otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n+{\n+\tstatic rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);\n+\tuint16_t port_id, nb_ethport = rte_eth_dev_count_avail();\n+\tint i, ret;\n+\n+\tfor (i = 0; i < nb_ethport; i++) {\n+\t\tport_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;\n+\t\tif (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i >= nb_ethport)\n+\t\treturn 0;\n+\n+\tret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n static struct otx2_cpt_qp *\n otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \t\t uint8_t group)\n@@ -220,6 +245,12 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n \n \totx2_cpt_iq_disable(qp);\n \n+\tret = otx2_cpt_qp_inline_cfg(dev, qp);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not configure queue for inline IPsec\");\n+\t\tgoto mempool_destroy;\n+\t}\n+\n \tret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,\n \t\t\t\t size_div40);\n \tif (ret) {\n@@ -913,12 +944,20 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,\n \t\tgoto queues_detach;\n \t}\n \n+\tret = otx2_cpt_inline_init(dev);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not enable inline IPsec\");\n+\t\tgoto intr_unregister;\n+\t}\n+\n \tdev->enqueue_burst = otx2_cpt_enqueue_burst;\n \tdev->dequeue_burst = otx2_cpt_dequeue_burst;\n \n \trte_mb();\n \treturn 0;\n \n+intr_unregister:\n+\totx2_cpt_err_intr_unregister(dev);\n queues_detach:\n \totx2_cpt_queues_detach(dev);\n \treturn ret;\n", "prefixes": [ "v4", "03/15" ] }