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GET /api/patches/65296/?format=api
{ "id": 65296, "url": "http://patches.dpdk.org/api/patches/65296/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1580292549-27439-9-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1580292549-27439-9-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1580292549-27439-9-git-send-email-matan@mellanox.com", "date": "2020-01-29T10:09:04", "name": "[v2,08/13] vdpa/mlx5: add basic steering configurations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "22374ea37487f318130f42b62f4caabdabf5bea6", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1580292549-27439-9-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8335, "url": "http://patches.dpdk.org/api/series/8335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8335", "date": "2020-01-29T10:08:56", "name": "Introduce mlx5 vDPA driver", "version": 2, "mbox": "http://patches.dpdk.org/series/8335/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65296/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65296/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 529B1A0531;\n\tWed, 29 Jan 2020 11:10:53 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CE0031BFF6;\n\tWed, 29 Jan 2020 11:10:13 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 8827D1BFF2\n for <dev@dpdk.org>; Wed, 29 Jan 2020 11:10:09 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 29 Jan 2020 12:10:07 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00TA9BHO032108;\n Wed, 29 Jan 2020 12:10:07 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org, Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>", "Date": "Wed, 29 Jan 2020 10:09:04 +0000", "Message-Id": "<1580292549-27439-9-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1580292549-27439-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>\n <1580292549-27439-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 08/13] vdpa/mlx5: add basic steering\n\tconfigurations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add a steering object to be managed by a new file mlx5_vdpa_steer.c.\n\nAllow promiscuous flow to scatter the device Rx packets to the virtio\nqueues using RSS action.\n\nIn order to allow correct RSS in L3 and L4, split the flow to 7 flows\nas required by the device.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/vdpa/mlx5/Makefile | 2 +\n drivers/vdpa/mlx5/meson.build | 1 +\n drivers/vdpa/mlx5/mlx5_vdpa.c | 1 +\n drivers/vdpa/mlx5/mlx5_vdpa.h | 34 +++++\n drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 265 ++++++++++++++++++++++++++++++++++++\n 5 files changed, 303 insertions(+)\n create mode 100644 drivers/vdpa/mlx5/mlx5_vdpa_steer.c", "diff": "diff --git a/drivers/vdpa/mlx5/Makefile b/drivers/vdpa/mlx5/Makefile\nindex 353e262..2f70a98 100644\n--- a/drivers/vdpa/mlx5/Makefile\n+++ b/drivers/vdpa/mlx5/Makefile\n@@ -11,6 +11,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_mem.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_event.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_virtq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_steer.c\n+\n \n # Basic CFLAGS.\n CFLAGS += -O3\ndiff --git a/drivers/vdpa/mlx5/meson.build b/drivers/vdpa/mlx5/meson.build\nindex e017f95..2849178 100644\n--- a/drivers/vdpa/mlx5/meson.build\n+++ b/drivers/vdpa/mlx5/meson.build\n@@ -15,6 +15,7 @@ sources = files(\n \t'mlx5_vdpa_mem.c',\n \t'mlx5_vdpa_event.c',\n \t'mlx5_vdpa_virtq.c',\n+\t'mlx5_vdpa_steer.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex dfbd0af..12cfee2 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -208,6 +208,7 @@\n \t\t\tgoto error;\n \t\t}\n \t\tpriv->caps = attr.vdpa;\n+\t\tpriv->log_max_rqt_size = attr.log_max_rqt_size;\n \t}\n \tpriv->ctx = ctx;\n \tpriv->dev_addr.pci_addr = pci_dev->addr;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex e530058..2b0b285 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -75,6 +75,18 @@ struct mlx5_vdpa_virtq {\n \t} umems[3];\n };\n \n+struct mlx5_vdpa_steer {\n+\tstruct mlx5_devx_obj *rqt;\n+\tvoid *domain;\n+\tvoid *tbl;\n+\tstruct {\n+\t\tstruct mlx5dv_flow_matcher *matcher;\n+\t\tstruct mlx5_devx_obj *tir;\n+\t\tvoid *tir_action;\n+\t\tvoid *flow;\n+\t} rss[7];\n+};\n+\n struct mlx5_vdpa_priv {\n \tTAILQ_ENTRY(mlx5_vdpa_priv) next;\n \tint id; /* vDPA device id. */\n@@ -95,7 +107,9 @@ struct mlx5_vdpa_priv {\n \tstruct mlx5_devx_obj *tis;\n \tuint16_t nr_virtqs;\n \tuint64_t features; /* Negotiated features. */\n+\tuint16_t log_max_rqt_size;\n \tSLIST_HEAD(virtq_list, mlx5_vdpa_virtq) virtq_list;\n+\tstruct mlx5_vdpa_steer steer;\n \tSLIST_HEAD(mr_list, mlx5_vdpa_query_mr) mr_list;\n };\n \n@@ -192,4 +206,24 @@ int mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n */\n int mlx5_vdpa_virtqs_prepare(struct mlx5_vdpa_priv *priv);\n \n+/**\n+ * Unset steering and release all its related resources- stop traffic.\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ */\n+int mlx5_vdpa_steer_unset(struct mlx5_vdpa_priv *priv);\n+\n+/**\n+ * Setup steering and all its related resources to enable RSS trafic from the\n+ * device to all the Rx host queues.\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+int mlx5_vdpa_steer_setup(struct mlx5_vdpa_priv *priv);\n+\n #endif /* RTE_PMD_MLX5_VDPA_H_ */\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_steer.c b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c\nnew file mode 100644\nindex 0000000..f365c10\n--- /dev/null\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_steer.c\n@@ -0,0 +1,265 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 Mellanox Technologies, Ltd\n+ */\n+#include <netinet/in.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+#include <rte_common.h>\n+\n+#include <mlx5_common.h>\n+\n+#include \"mlx5_vdpa_utils.h\"\n+#include \"mlx5_vdpa.h\"\n+\n+int\n+mlx5_vdpa_steer_unset(struct mlx5_vdpa_priv *priv)\n+{\n+\tint ret __rte_unused;\n+\tunsigned i;\n+\n+\tfor (i = 0; i < RTE_DIM(priv->steer.rss); ++i) {\n+\t\tif (priv->steer.rss[i].flow) {\n+\t\t\tclaim_zero(mlx5_glue->dv_destroy_flow\n+\t\t\t\t\t\t (priv->steer.rss[i].flow));\n+\t\t\tpriv->steer.rss[i].flow = NULL;\n+\t\t}\n+\t\tif (priv->steer.rss[i].tir_action) {\n+\t\t\tclaim_zero(mlx5_glue->destroy_flow_action\n+\t\t\t\t\t (priv->steer.rss[i].tir_action));\n+\t\t\tpriv->steer.rss[i].tir_action = NULL;\n+\t\t}\n+\t\tif (priv->steer.rss[i].tir) {\n+\t\t\tclaim_zero(mlx5_devx_cmd_destroy\n+\t\t\t\t\t\t (priv->steer.rss[i].tir));\n+\t\t\tpriv->steer.rss[i].tir = NULL;\n+\t\t}\n+\t\tif (priv->steer.rss[i].matcher) {\n+\t\t\tclaim_zero(mlx5_glue->dv_destroy_flow_matcher\n+\t\t\t\t\t\t (priv->steer.rss[i].matcher));\n+\t\t\tpriv->steer.rss[i].matcher = NULL;\n+\t\t}\n+\t}\n+\tif (priv->steer.tbl) {\n+\t\tclaim_zero(mlx5_glue->dr_destroy_flow_tbl(priv->steer.tbl));\n+\t\tpriv->steer.tbl = NULL;\n+\t}\n+\tif (priv->steer.domain) {\n+\t\tclaim_zero(mlx5_glue->dr_destroy_domain(priv->steer.domain));\n+\t\tpriv->steer.domain = NULL;\n+\t}\n+\tif (priv->steer.rqt) {\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(priv->steer.rqt));\n+\t\tpriv->steer.rqt = NULL;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * According to VIRTIO_NET Spec the virtqueues index identity its type by:\n+ * 0 receiveq1\n+ * 1 transmitq1\n+ * ...\n+ * 2(N-1) receiveqN\n+ * 2(N-1)+1 transmitqN\n+ * 2N controlq\n+ */\n+static uint8_t\n+is_virtq_recvq(int virtq_index, int nr_vring)\n+{\n+\tif (virtq_index % 2 == 0 && virtq_index != nr_vring - 1)\n+\t\treturn 1;\n+\treturn 0;\n+}\n+\n+#define MLX5_VDPA_DEFAULT_RQT_SIZE 512\n+static int __rte_unused\n+mlx5_vdpa_rqt_prepare(struct mlx5_vdpa_priv *priv)\n+{\n+\tstruct mlx5_vdpa_virtq *virtq;\n+\tuint32_t rqt_n = RTE_MIN(MLX5_VDPA_DEFAULT_RQT_SIZE,\n+\t\t\t\t 1 << priv->log_max_rqt_size);\n+\tstruct mlx5_devx_rqt_attr *attr = rte_zmalloc(__func__, sizeof(*attr)\n+\t\t\t\t\t\t + rqt_n *\n+\t\t\t\t\t\t sizeof(uint32_t), 0);\n+\tuint32_t i = 0, j;\n+\tint ret = 0;\n+\n+\tif (!attr) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate RQT attributes memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -ENOMEM;\n+\t}\n+\tSLIST_FOREACH(virtq, &priv->virtq_list, next) {\n+\t\tif (is_virtq_recvq(virtq->index, priv->nr_virtqs)) {\n+\t\t\tattr->rq_list[i] = virtq->virtq->id;\n+\t\t\ti++;\n+\t\t}\n+\t}\n+\tfor (j = 0; i != rqt_n; ++i, ++j)\n+\t\tattr->rq_list[i] = attr->rq_list[j];\n+\tattr->rq_type = MLX5_INLINE_Q_TYPE_VIRTQ;\n+\tattr->rqt_max_size = rqt_n;\n+\tattr->rqt_actual_size = rqt_n;\n+\tif (!priv->steer.rqt) {\n+\t\tpriv->steer.rqt = mlx5_devx_cmd_create_rqt(priv->ctx, attr);\n+\t\tif (!priv->steer.rqt) {\n+\t\t\tDRV_LOG(ERR, \"Failed to create RQT.\");\n+\t\t\tret = -rte_errno;\n+\t\t}\n+\t} else {\n+\t\tret = mlx5_devx_cmd_modify_rqt(priv->steer.rqt, attr);\n+\t\tif (ret)\n+\t\t\tDRV_LOG(ERR, \"Failed to modify RQT.\");\n+\t}\n+\trte_free(attr);\n+\treturn ret;\n+}\n+\n+static int __rte_unused\n+mlx5_vdpa_rss_flows_create(struct mlx5_vdpa_priv *priv)\n+{\n+#ifdef HAVE_MLX5DV_DR\n+\tstruct mlx5_devx_tir_attr tir_att = {\n+\t\t.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT,\n+\t\t.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ,\n+\t\t.transport_domain = priv->td->id,\n+\t\t.indirect_table = priv->steer.rqt->id,\n+\t\t.rx_hash_symmetric = 1,\n+\t\t.rx_hash_toeplitz_key = { 0x2cc681d1, 0x5bdbf4f7, 0xfca28319,\n+\t\t\t\t\t 0xdb1a3e94, 0x6b9e38d9, 0x2c9c03d1,\n+\t\t\t\t\t 0xad9944a7, 0xd9563d59, 0x063c25f3,\n+\t\t\t\t\t 0xfc1fdc2a },\n+\t};\n+\tstruct {\n+\t\tsize_t size;\n+\t\t/**< Size of match value. Do NOT split size and key! */\n+\t\tuint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];\n+\t\t/**< Matcher value. This value is used as the mask or a key. */\n+\t} matcher_mask = {\n+\t\t\t\t.size = sizeof(matcher_mask.buf),\n+\t\t\t},\n+\t matcher_value = {\n+\t\t\t\t.size = sizeof(matcher_value.buf),\n+\t\t\t};\n+\tstruct mlx5dv_flow_matcher_attr dv_attr = {\n+\t\t.type = IBV_FLOW_ATTR_NORMAL,\n+\t\t.match_mask = (void *)&matcher_mask,\n+\t};\n+\tvoid *match_m = matcher_mask.buf;\n+\tvoid *match_v = matcher_value.buf;\n+\tvoid *headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);\n+\tvoid *headers_v = MLX5_ADDR_OF(fte_match_param, match_v, outer_headers);\n+\tvoid *actions[1];\n+\tconst uint8_t l3_hash =\n+\t\t(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |\n+\t\t(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP);\n+\tconst uint8_t l4_hash =\n+\t\t(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT) |\n+\t\t(1 << MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT);\n+\tenum { PRIO, CRITERIA, IP_VER_M, IP_VER_V, IP_PROT_M, IP_PROT_V, L3_BIT,\n+\t L4_BIT, HASH, END};\n+\tconst uint8_t vars[RTE_DIM(priv->steer.rss)][END] = {\n+\t\t{ 7, 0, 0, 0, 0, 0, 0, 0, 0 },\n+\t\t{ 6, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0, 0,\n+\t\t MLX5_L3_PROT_TYPE_IPV4, 0, l3_hash },\n+\t\t{ 6, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0, 0,\n+\t\t MLX5_L3_PROT_TYPE_IPV6, 0, l3_hash },\n+\t\t{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0xff,\n+\t\t IPPROTO_UDP, MLX5_L3_PROT_TYPE_IPV4, MLX5_L4_PROT_TYPE_UDP,\n+\t\t l3_hash | l4_hash },\n+\t\t{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 4, 0xff,\n+\t\t IPPROTO_TCP, MLX5_L3_PROT_TYPE_IPV4, MLX5_L4_PROT_TYPE_TCP,\n+\t\t l3_hash | l4_hash },\n+\t\t{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0xff,\n+\t\t IPPROTO_UDP, MLX5_L3_PROT_TYPE_IPV6, MLX5_L4_PROT_TYPE_UDP,\n+\t\t l3_hash | l4_hash },\n+\t\t{ 5, 1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 0xf, 6, 0xff,\n+\t\t IPPROTO_TCP, MLX5_L3_PROT_TYPE_IPV6, MLX5_L4_PROT_TYPE_TCP,\n+\t\t l3_hash | l4_hash },\n+\t};\n+\tunsigned i;\n+\n+\tfor (i = 0; i < RTE_DIM(priv->steer.rss); ++i) {\n+\t\tdv_attr.priority = vars[i][PRIO];\n+\t\tdv_attr.match_criteria_enable = vars[i][CRITERIA];\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,\n+\t\t\t vars[i][IP_VER_M]);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,\n+\t\t\t vars[i][IP_VER_V]);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,\n+\t\t\t vars[i][IP_PROT_M]);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,\n+\t\t\t vars[i][IP_PROT_V]);\n+\t\ttir_att.rx_hash_field_selector_outer.l3_prot_type =\n+\t\t\t\t\t\t\t\tvars[i][L3_BIT];\n+\t\ttir_att.rx_hash_field_selector_outer.l4_prot_type =\n+\t\t\t\t\t\t\t\tvars[i][L4_BIT];\n+\t\ttir_att.rx_hash_field_selector_outer.selected_fields =\n+\t\t\t\t\t\t\t\t vars[i][HASH];\n+\t\tpriv->steer.rss[i].matcher = mlx5_glue->dv_create_flow_matcher\n+\t\t\t\t\t (priv->ctx, &dv_attr, priv->steer.tbl);\n+\t\tif (!priv->steer.rss[i].matcher) {\n+\t\t\tDRV_LOG(ERR, \"Failed to create matcher %d.\", i);\n+\t\t\tgoto error;\n+\t\t}\n+\t\tpriv->steer.rss[i].tir = mlx5_devx_cmd_create_tir(priv->ctx,\n+\t\t\t\t\t\t\t\t &tir_att);\n+\t\tif (!priv->steer.rss[i].tir) {\n+\t\t\tDRV_LOG(ERR, \"Failed to create TIR %d.\", i);\n+\t\t\tgoto error;\n+\t\t}\n+\t\tpriv->steer.rss[i].tir_action =\n+\t\t\t\tmlx5_glue->dv_create_flow_action_dest_devx_tir\n+\t\t\t\t\t\t (priv->steer.rss[i].tir->obj);\n+\t\tif (!priv->steer.rss[i].tir_action) {\n+\t\t\tDRV_LOG(ERR, \"Failed to create TIR action %d.\", i);\n+\t\t\tgoto error;\n+\t\t}\n+\t\tactions[0] = priv->steer.rss[i].tir_action;\n+\t\tpriv->steer.rss[i].flow = mlx5_glue->dv_create_flow\n+\t\t\t\t\t(priv->steer.rss[i].matcher,\n+\t\t\t\t\t (void *)&matcher_value, 1, actions);\n+\t\tif (!priv->steer.rss[i].flow) {\n+\t\t\tDRV_LOG(ERR, \"Failed to create flow %d.\", i);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\treturn 0;\n+error:\n+\t/* Resources will be freed by the caller. */\n+\treturn -1;\n+#else\n+\t(void)priv;\n+\treturn -ENOTSUP;\n+#endif /* HAVE_MLX5DV_DR */\n+}\n+\n+int\n+mlx5_vdpa_steer_setup(struct mlx5_vdpa_priv *priv)\n+{\n+#ifdef HAVE_MLX5DV_DR\n+\tif (mlx5_vdpa_rqt_prepare(priv))\n+\t\treturn -1;\n+\tpriv->steer.domain = mlx5_glue->dr_create_domain(priv->ctx,\n+\t\t\t\t\t\t MLX5DV_DR_DOMAIN_TYPE_NIC_RX);\n+\tif (!priv->steer.domain) {\n+\t\tDRV_LOG(ERR, \"Failed to create Rx domain.\");\n+\t\tgoto error;\n+\t}\n+\tpriv->steer.tbl = mlx5_glue->dr_create_flow_tbl(priv->steer.domain, 0);\n+\tif (!priv->steer.tbl) {\n+\t\tDRV_LOG(ERR, \"Failed to create table 0 with Rx domain.\");\n+\t\tgoto error;\n+\t}\n+\tif (mlx5_vdpa_rss_flows_create(priv))\n+\t\tgoto error;\n+\treturn 0;\n+error:\n+\tmlx5_vdpa_steer_unset(priv);\n+\treturn -1;\n+#else\n+\t(void)priv;\n+\treturn -ENOTSUP;\n+#endif /* HAVE_MLX5DV_DR */\n+}\n", "prefixes": [ "v2", "08/13" ] }