Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/65293/?format=api
{ "id": 65293, "url": "http://patches.dpdk.org/api/patches/65293/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1580292549-27439-6-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1580292549-27439-6-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1580292549-27439-6-git-send-email-matan@mellanox.com", "date": "2020-01-29T10:09:01", "name": "[v2,05/13] vdpa/mlx5: prepare HW queues", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "097481bed16d5e5615775672a6714e16578dd749", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1580292549-27439-6-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8335, "url": "http://patches.dpdk.org/api/series/8335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8335", "date": "2020-01-29T10:08:56", "name": "Introduce mlx5 vDPA driver", "version": 2, "mbox": "http://patches.dpdk.org/series/8335/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65293/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65293/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0372AA0531;\n\tWed, 29 Jan 2020 11:10:10 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CA69E1BFE1;\n\tWed, 29 Jan 2020 11:09:50 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 88E9A1BFE1\n for <dev@dpdk.org>; Wed, 29 Jan 2020 11:09:49 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 29 Jan 2020 12:09:46 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00TA9BHL032108;\n Wed, 29 Jan 2020 12:09:46 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org, Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>", "Date": "Wed, 29 Jan 2020 10:09:01 +0000", "Message-Id": "<1580292549-27439-6-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1580292549-27439-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>\n <1580292549-27439-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 05/13] vdpa/mlx5: prepare HW queues", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "As an arrangement to the vitrio queues creation, a 2 QPs and CQ may be\ncreated for the virtio queue.\n\nThe design is to trigger an event for the guest and for the vdpa driver\nwhen a new CQE is posted by the HW after the packet transition.\n\nThis patch add the basic operations to create and destroy the above HW\nobjects and to trigger the CQE events when a new CQE is posted.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 4 +\n drivers/vdpa/mlx5/Makefile | 1 +\n drivers/vdpa/mlx5/meson.build | 1 +\n drivers/vdpa/mlx5/mlx5_vdpa.h | 89 ++++++++\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 399 ++++++++++++++++++++++++++++++++++++\n 5 files changed, 494 insertions(+)\n create mode 100644 drivers/vdpa/mlx5/mlx5_vdpa_event.c", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex b48cd0a..b533798 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -392,6 +392,10 @@ struct mlx5_cqe {\n /* CQE format value. */\n #define MLX5_COMPRESSED 0x3\n \n+/* CQ doorbell cmd types. */\n+#define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)\n+#define MLX5_CQ_DBR_CMD_ALL (0 << 24)\n+\n /* Action type of header modification. */\n enum {\n \tMLX5_MODIFICATION_TYPE_SET = 0x1,\ndiff --git a/drivers/vdpa/mlx5/Makefile b/drivers/vdpa/mlx5/Makefile\nindex 5472797..7f13756 100644\n--- a/drivers/vdpa/mlx5/Makefile\n+++ b/drivers/vdpa/mlx5/Makefile\n@@ -9,6 +9,7 @@ LIB = librte_pmd_mlx5_vdpa.a\n # Sources.\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa.c\n SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_mem.c\n+SRCS-$(CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD) += mlx5_vdpa_event.c\n \n # Basic CFLAGS.\n CFLAGS += -O3\ndiff --git a/drivers/vdpa/mlx5/meson.build b/drivers/vdpa/mlx5/meson.build\nindex 7e5dd95..c609f7c 100644\n--- a/drivers/vdpa/mlx5/meson.build\n+++ b/drivers/vdpa/mlx5/meson.build\n@@ -13,6 +13,7 @@ deps += ['hash', 'common_mlx5', 'vhost', 'bus_pci', 'eal', 'sched']\n sources = files(\n \t'mlx5_vdpa.c',\n \t'mlx5_vdpa_mem.c',\n+\t'mlx5_vdpa_event.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex e27baea..30030b7 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -9,9 +9,40 @@\n \n #include <rte_vdpa.h>\n #include <rte_vhost.h>\n+#include <rte_spinlock.h>\n+#include <rte_interrupts.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n+#include <mlx5_prm.h>\n+\n+\n+#define MLX5_VDPA_INTR_RETRIES 256\n+#define MLX5_VDPA_INTR_RETRIES_USEC 1000\n+\n+struct mlx5_vdpa_cq {\n+\tuint16_t log_desc_n;\n+\tuint32_t cq_ci:24;\n+\tuint32_t arm_sn:2;\n+\trte_spinlock_t sl;\n+\tstruct mlx5_devx_obj *cq;\n+\tstruct mlx5dv_devx_umem *umem_obj;\n+\tunion {\n+\t\tvolatile void *umem_buf;\n+\t\tvolatile struct mlx5_cqe *cqes;\n+\t};\n+\tvolatile uint32_t *db_rec;\n+\tuint64_t errors;\n+};\n+\n+struct mlx5_vdpa_event_qp {\n+\tstruct mlx5_vdpa_cq cq;\n+\tstruct mlx5_devx_obj *fw_qp;\n+\tstruct mlx5_devx_obj *sw_qp;\n+\tstruct mlx5dv_devx_umem *umem_obj;\n+\tvoid *umem_buf;\n+\tvolatile uint32_t *db_rec;\n+};\n \n struct mlx5_vdpa_query_mr {\n \tSLIST_ENTRY(mlx5_vdpa_query_mr) next;\n@@ -34,6 +65,10 @@ struct mlx5_vdpa_priv {\n \tuint32_t gpa_mkey_index;\n \tstruct ibv_mr *null_mr;\n \tstruct rte_vhost_memory *vmem;\n+\tuint32_t eqn;\n+\tstruct mlx5dv_devx_event_channel *eventc;\n+\tstruct mlx5dv_devx_uar *uar;\n+\tstruct rte_intr_handle intr_handle;\n \tSLIST_HEAD(mr_list, mlx5_vdpa_query_mr) mr_list;\n };\n \n@@ -57,4 +92,58 @@ struct mlx5_vdpa_priv {\n */\n int mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv);\n \n+\n+/**\n+ * Create an event QP and all its related resources.\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ * @param[in] desc_n\n+ * Number of descriptors.\n+ * @param[in] callfd\n+ * The guest notification file descriptor.\n+ * @param[in/out] eqp\n+ * Pointer to the event QP structure.\n+ *\n+ * @return\n+ * 0 on success, -1 otherwise and rte_errno is set.\n+ */\n+int mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n+\t\t\t int callfd, struct mlx5_vdpa_event_qp *eqp);\n+\n+/**\n+ * Destroy an event QP and all its related resources.\n+ *\n+ * @param[in/out] eqp\n+ * Pointer to the event QP structure.\n+ */\n+void mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp);\n+\n+/**\n+ * Release all the event global resources.\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ */\n+void mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv);\n+\n+/**\n+ * Setup CQE event.\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv);\n+\n+/**\n+ * Unset CQE event .\n+ *\n+ * @param[in] priv\n+ * The vdpa driver private structure.\n+ */\n+void mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv);\n+\n #endif /* RTE_PMD_MLX5_VDPA_H_ */\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nnew file mode 100644\nindex 0000000..35518ad\n--- /dev/null\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -0,0 +1,399 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 Mellanox Technologies, Ltd\n+ */\n+#include <unistd.h>\n+#include <stdint.h>\n+#include <fcntl.h>\n+\n+#include <rte_malloc.h>\n+#include <rte_errno.h>\n+#include <rte_lcore.h>\n+#include <rte_atomic.h>\n+#include <rte_common.h>\n+#include <rte_io.h>\n+\n+#include <mlx5_common.h>\n+\n+#include \"mlx5_vdpa_utils.h\"\n+#include \"mlx5_vdpa.h\"\n+\n+\n+void\n+mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)\n+{\n+\tif (priv->uar) {\n+\t\tmlx5_glue->devx_free_uar(priv->uar);\n+\t\tpriv->uar = NULL;\n+\t}\n+\tif (priv->eventc) {\n+\t\tmlx5_glue->devx_destroy_event_channel(priv->eventc);\n+\t\tpriv->eventc = NULL;\n+\t}\n+\tpriv->eqn = 0;\n+}\n+\n+/* Prepare all the global resources for all the event objects.*/\n+static int\n+mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)\n+{\n+\tuint32_t lcore;\n+\n+\tif (priv->eventc)\n+\t\treturn 0;\n+\tlcore = (uint32_t)rte_lcore_to_cpu_id(-1);\n+\tif (mlx5_glue->devx_query_eqn(priv->ctx, lcore, &priv->eqn)) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to query EQ number %d.\", rte_errno);\n+\t\treturn -1;\n+\t}\n+\tpriv->eventc = mlx5_glue->devx_create_event_channel(priv->ctx,\n+\t\t\t MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);\n+\tif (!priv->eventc) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create event channel %d.\",\n+\t\t\trte_errno);\n+\t\tgoto error;\n+\t}\n+\tpriv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);\n+\tif (!priv->uar) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n+\t\tgoto error;\n+\t}\n+\treturn 0;\n+error:\n+\tmlx5_vdpa_event_qp_global_release(priv);\n+\treturn -1;\n+}\n+\n+static void\n+mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)\n+{\n+\tif (cq->cq)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(cq->cq));\n+\tif (cq->umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));\n+\tif (cq->umem_buf)\n+\t\trte_free((void *)(uintptr_t)cq->umem_buf);\n+\tmemset(cq, 0, sizeof(*cq));\n+}\n+\n+static inline void\n+mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)\n+{\n+\tconst unsigned int cqe_mask = (1 << cq->log_desc_n) - 1;\n+\tuint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;\n+\tuint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK & cqe_mask;\n+\tuint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;\n+\tuint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;\n+\tuint64_t db_be = rte_cpu_to_be_64(doorbell);\n+\tuint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);\n+\n+\trte_io_wmb();\n+\tcq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);\n+\trte_wmb();\n+#ifdef RTE_ARCH_64\n+\t*(uint64_t *)addr = db_be;\n+#else\n+\t*(uint32_t *)addr = db_be;\n+\trte_io_wmb();\n+\t*((uint32_t *)addr + 1) = db_be >> 32;\n+#endif\n+\tcq->arm_sn++;\n+}\n+\n+static int\n+mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,\n+\t\t int callfd, struct mlx5_vdpa_cq *cq)\n+{\n+\tstruct mlx5_devx_cq_attr attr;\n+\tsize_t pgsize = sysconf(_SC_PAGESIZE);\n+\tuint32_t umem_size;\n+\tint ret;\n+\tuint16_t event_nums[1] = {0};\n+\n+\tcq->log_desc_n = log_desc_n;\n+\tumem_size = sizeof(struct mlx5_cqe) * (1 << log_desc_n) +\n+\t\t\t\t\t\t\tsizeof(*cq->db_rec) * 2;\n+\tcq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);\n+\tif (!cq->umem_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -ENOMEM;\n+\t}\n+\tcq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\t\t\t\t\t\t(void *)(uintptr_t)cq->umem_buf,\n+\t\t\t\t\t\tumem_size,\n+\t\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n+\tif (!cq->umem_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to register umem for CQ.\");\n+\t\tgoto error;\n+\t}\n+\tattr.q_umem_valid = 1;\n+\tattr.db_umem_valid = 1;\n+\tattr.use_first_only = 0;\n+\tattr.overrun_ignore = 0;\n+\tattr.uar_page_id = priv->uar->page_id;\n+\tattr.q_umem_id = cq->umem_obj->umem_id;\n+\tattr.q_umem_offset = 0;\n+\tattr.db_umem_id = cq->umem_obj->umem_id;\n+\tattr.db_umem_offset = sizeof(struct mlx5_cqe) * (1 << log_desc_n);\n+\tattr.eqn = priv->eqn;\n+\tattr.log_cq_size = log_desc_n;\n+\tattr.log_page_size = rte_log2_u32(pgsize);\n+\tcq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);\n+\tif (!cq->cq)\n+\t\tgoto error;\n+\tcq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);\n+\tcq->cq_ci = 0;\n+\trte_spinlock_init(&cq->sl);\n+\t/* Subscribe CQ event to the event channel controlled by the driver. */\n+\tret = mlx5_glue->devx_subscribe_devx_event(priv->eventc, cq->cq->obj,\n+\t\t\t\t\t\t sizeof(event_nums),\n+\t\t\t\t\t\t event_nums,\n+\t\t\t\t\t\t (uint64_t)(uintptr_t)cq);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to subscribe CQE event.\");\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\t/* Subscribe CQ event to the guest FD only if it is not in poll mode. */\n+\tif (callfd != -1) {\n+\t\tret = mlx5_glue->devx_subscribe_devx_event_fd(priv->eventc,\n+\t\t\t\t\t\t\t callfd,\n+\t\t\t\t\t\t\t cq->cq->obj, 0);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Failed to subscribe CQE event fd.\");\n+\t\t\trte_errno = errno;\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\t/* First arming. */\n+\tmlx5_vdpa_cq_arm(priv, cq);\n+\treturn 0;\n+error:\n+\tmlx5_vdpa_cq_destroy(cq);\n+\treturn -1;\n+}\n+\n+static inline void __rte_unused\n+mlx5_vdpa_cq_poll(struct mlx5_vdpa_priv *priv __rte_unused,\n+\t\t struct mlx5_vdpa_cq *cq)\n+{\n+\tstruct mlx5_vdpa_event_qp *eqp =\n+\t\t\t\tcontainer_of(cq, struct mlx5_vdpa_event_qp, cq);\n+\tconst unsigned int cqe_size = 1 << cq->log_desc_n;\n+\tconst unsigned int cqe_mask = cqe_size - 1;\n+\tint ret;\n+\n+\tdo {\n+\t\tvolatile struct mlx5_cqe *cqe = cq->cqes + (cq->cq_ci &\n+\t\t\t\t\t\t\t cqe_mask);\n+\n+\t\tret = check_cqe(cqe, cqe_size, cq->cq_ci);\n+\t\tswitch (ret) {\n+\t\tcase MLX5_CQE_STATUS_ERR:\n+\t\t\tcq->errors++;\n+\t\t\t/*fall-through*/\n+\t\tcase MLX5_CQE_STATUS_SW_OWN:\n+\t\t\tcq->cq_ci++;\n+\t\t\tbreak;\n+\t\tcase MLX5_CQE_STATUS_HW_OWN:\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t} while (ret != MLX5_CQE_STATUS_HW_OWN);\n+\trte_io_wmb();\n+\t/* Ring CQ doorbell record. */\n+\tcq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n+\trte_io_wmb();\n+\t/* Ring SW QP doorbell record. */\n+\teqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cqe_size);\n+}\n+\n+static void\n+mlx5_vdpa_interrupt_handler(void *cb_arg)\n+{\n+#ifndef HAVE_IBV_DEVX_EVENT\n+\t(void)cb_arg;\n+\treturn;\n+#else\n+\tstruct mlx5_vdpa_priv *priv = cb_arg;\n+\tunion {\n+\t\tstruct mlx5dv_devx_async_event_hdr event_resp;\n+\t\tuint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];\n+\t} out;\n+\n+\twhile (mlx5_glue->devx_get_event(priv->eventc, &out.event_resp,\n+\t\t\t\t\t sizeof(out.buf)) >=\n+\t\t\t\t (ssize_t)sizeof(out.event_resp.cookie)) {\n+\t\tstruct mlx5_vdpa_cq *cq = (struct mlx5_vdpa_cq *)\n+\t\t\t\t\t (uintptr_t)out.event_resp.cookie;\n+\t\trte_spinlock_lock(&cq->sl);\n+\t\tmlx5_vdpa_cq_poll(priv, cq);\n+\t\tmlx5_vdpa_cq_arm(priv, cq);\n+\t\trte_spinlock_unlock(&cq->sl);\n+\t\tDRV_LOG(DEBUG, \"CQ %p event: new cq_ci = %u.\", cq, cq->cq_ci);\n+\t}\n+#endif /* HAVE_IBV_DEVX_ASYNC */\n+}\n+\n+int\n+mlx5_vdpa_cqe_event_setup(struct mlx5_vdpa_priv *priv)\n+{\n+\tint flags = fcntl(priv->eventc->fd, F_GETFL);\n+\tint ret = fcntl(priv->eventc->fd, F_SETFL, flags | O_NONBLOCK);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to change event channel FD.\");\n+\t\trte_errno = errno;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->intr_handle.fd = priv->eventc->fd;\n+\tpriv->intr_handle.type = RTE_INTR_HANDLE_EXT;\n+\tif (rte_intr_callback_register(&priv->intr_handle,\n+\t\t\t\t mlx5_vdpa_interrupt_handler, priv)) {\n+\t\tpriv->intr_handle.fd = 0;\n+\t\tDRV_LOG(ERR, \"Failed to register CQE interrupt %d.\", rte_errno);\n+\t\treturn -rte_errno;\n+\t}\n+\treturn 0;\n+}\n+\n+void\n+mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)\n+{\n+\tint retries = MLX5_VDPA_INTR_RETRIES;\n+\tint ret = -EAGAIN;\n+\n+\tif (priv->intr_handle.fd) {\n+\t\twhile (retries-- && ret == -EAGAIN) {\n+\t\t\tret = rte_intr_callback_unregister(&priv->intr_handle,\n+\t\t\t\t\t\t mlx5_vdpa_interrupt_handler,\n+\t\t\t\t\t\t priv);\n+\t\t\tif (ret == -EAGAIN) {\n+\t\t\t\tDRV_LOG(DEBUG, \"Try again to unregister fd %d \"\n+\t\t\t\t\t\"of CQ interrupt, retries = %d.\",\n+\t\t\t\t\tpriv->intr_handle.fd, retries);\n+\t\t\t\tusleep(MLX5_VDPA_INTR_RETRIES_USEC);\n+\t\t\t}\n+\t\t}\n+\t\tmemset(&priv->intr_handle, 0, sizeof(priv->intr_handle));\n+\t}\n+}\n+\n+void\n+mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)\n+{\n+\tif (eqp->sw_qp)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));\n+\tif (eqp->umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));\n+\tif (eqp->umem_buf)\n+\t\trte_free(eqp->umem_buf);\n+\tif (eqp->fw_qp)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));\n+\tmlx5_vdpa_cq_destroy(&eqp->cq);\n+\tmemset(eqp, 0, sizeof(*eqp));\n+}\n+\n+static int\n+mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)\n+{\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify FW QP to INIT state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t eqp->fw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify SW QP to INIT state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify FW QP to RTR state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t eqp->fw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify SW QP to RTR state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify FW QP to RTS state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t eqp->fw_qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify SW QP to RTS state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n+\t\t\t int callfd, struct mlx5_vdpa_event_qp *eqp)\n+{\n+\tstruct mlx5_devx_qp_attr attr = {0};\n+\tuint16_t log_desc_n = rte_log2_u32(desc_n);\n+\tuint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +\n+\t\t\t\t\t\t sizeof(*eqp->db_rec) * 2;\n+\n+\tif (mlx5_vdpa_event_qp_global_prepare(priv))\n+\t\treturn -1;\n+\tif (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))\n+\t\treturn -1;\n+\tattr.pd = priv->pdn;\n+\teqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tif (!eqp->fw_qp) {\n+\t\tDRV_LOG(ERR, \"Failed to create FW QP(%u).\", rte_errno);\n+\t\tgoto error;\n+\t}\n+\teqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);\n+\tif (!eqp->umem_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for SW QP.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\teqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)eqp->umem_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (!eqp->umem_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to register umem for SW QP.\");\n+\t\tgoto error;\n+\t}\n+\tattr.uar_index = priv->uar->page_id;\n+\tattr.cqn = eqp->cq.cq->id;\n+\tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n+\tattr.rq_size = 1 << log_desc_n;\n+\tattr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);\n+\tattr.sq_size = 0; /* No need SQ. */\n+\tattr.dbr_umem_valid = 1;\n+\tattr.wq_umem_id = eqp->umem_obj->umem_id;\n+\tattr.wq_umem_offset = 0;\n+\tattr.dbr_umem_id = eqp->umem_obj->umem_id;\n+\tattr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;\n+\teqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tif (!eqp->sw_qp) {\n+\t\tDRV_LOG(ERR, \"Failed to create SW QP(%u).\", rte_errno);\n+\t\tgoto error;\n+\t}\n+\teqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);\n+\tif (mlx5_vdpa_qps2rts(eqp))\n+\t\tgoto error;\n+\t/* First ringing. */\n+\trte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);\n+\treturn 0;\n+error:\n+\tmlx5_vdpa_event_qp_destroy(eqp);\n+\treturn -1;\n+}\n", "prefixes": [ "v2", "05/13" ] }