Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/65218/?format=api
{ "id": 65218, "url": "http://patches.dpdk.org/api/patches/65218/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1580205965-21492-17-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1580205965-21492-17-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1580205965-21492-17-git-send-email-matan@mellanox.com", "date": "2020-01-28T10:05:56", "name": "[v2,16/25] common/mlx5: add support for DevX QP operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "657456e7dac93263f38455309e2bb595753a88a1", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1580205965-21492-17-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8319, "url": "http://patches.dpdk.org/api/series/8319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8319", "date": "2020-01-28T10:05:40", "name": "Introduce mlx5 common library", "version": 2, "mbox": "http://patches.dpdk.org/series/8319/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/65218/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/65218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 918E2A04B3;\n\tTue, 28 Jan 2020 11:09:38 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1D3E41C1FE;\n\tTue, 28 Jan 2020 11:09:17 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 7EFB51C1FE\n for <dev@dpdk.org>; Tue, 28 Jan 2020 11:09:16 +0100 (CET)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 28 Jan 2020 12:09:15 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00SA6FpJ016102;\n Tue, 28 Jan 2020 12:09:15 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org, Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "Raslan Darawsheh <rasland@mellanox.com>", "Date": "Tue, 28 Jan 2020 10:05:56 +0000", "Message-Id": "<1580205965-21492-17-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1580205965-21492-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>\n <1580205965-21492-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 16/25] common/mlx5: add support for DevX QP\n\toperations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "QP creation is needed for vDPA virtq support.\n\nAdd 2 DevX commands to create QP and to modify QP state.\n\nThe support is for RC QP only in force loopback address mode.\n\nBy this way, the packets can be sent to other inernal destinations in\nthe nic. For example: other QPs or virtqs.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 167 ++++++++++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 20 ++\n drivers/common/mlx5/mlx5_prm.h | 376 ++++++++++++++++++++++++\n drivers/common/mlx5/rte_common_mlx5_version.map | 2 +\n 4 files changed, 564 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 2425513..e7288c8 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1124,7 +1124,8 @@ struct mlx5_devx_obj *\n \tMLX5_SET(cqc, cqctx, cc, attr->use_first_only);\n \tMLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);\n \tMLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);\n-\tMLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size);\n+\tMLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -\n+\t\t MLX5_ADAPTER_PAGE_SHIFT);\n \tMLX5_SET(cqc, cqctx, c_eqn, attr->eqn);\n \tMLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);\n \tif (attr->q_umem_valid) {\n@@ -1313,3 +1314,167 @@ struct mlx5_devx_obj *\n \tattr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);\n \treturn ret;\n }\n+\n+/**\n+ * Create QP using DevX API.\n+ *\n+ * @param[in] ctx\n+ * ibv_context returned from mlx5dv_open_device.\n+ * @param [in] attr\n+ * Pointer to QP attributes structure.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_qp(struct ibv_context *ctx,\n+\t\t\tstruct mlx5_devx_qp_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};\n+\tstruct mlx5_devx_obj *qp_obj = rte_zmalloc(__func__, sizeof(*qp_obj),\n+\t\t\t\t\t\t 0);\n+\tvoid *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);\n+\n+\tif (!qp_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate QP data.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);\n+\tMLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);\n+\tMLX5_SET(qpc, qpc, pd, attr->pd);\n+\tif (attr->uar_index) {\n+\t\tMLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);\n+\t\tMLX5_SET(qpc, qpc, uar_page, attr->uar_index);\n+\t\tMLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -\n+\t\t\t MLX5_ADAPTER_PAGE_SHIFT);\n+\t\tif (attr->sq_size) {\n+\t\t\tRTE_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));\n+\t\t\tMLX5_SET(qpc, qpc, cqn_snd, attr->cqn);\n+\t\t\tMLX5_SET(qpc, qpc, log_sq_size,\n+\t\t\t\t rte_log2_u32(attr->sq_size));\n+\t\t} else {\n+\t\t\tMLX5_SET(qpc, qpc, no_sq, 1);\n+\t\t}\n+\t\tif (attr->rq_size) {\n+\t\t\tRTE_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));\n+\t\t\tMLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);\n+\t\t\tMLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -\n+\t\t\t\t MLX5_LOG_RQ_STRIDE_SHIFT);\n+\t\t\tMLX5_SET(qpc, qpc, log_rq_size,\n+\t\t\t\t rte_log2_u32(attr->rq_size));\n+\t\t\tMLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);\n+\t\t} else {\n+\t\t\tMLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);\n+\t\t}\n+\t\tif (attr->dbr_umem_valid) {\n+\t\t\tMLX5_SET(qpc, qpc, dbr_umem_valid,\n+\t\t\t\t attr->dbr_umem_valid);\n+\t\t\tMLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);\n+\t\t}\n+\t\tMLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);\n+\t\tMLX5_SET64(create_qp_in, in, wq_umem_offset,\n+\t\t\t attr->wq_umem_offset);\n+\t\tMLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);\n+\t\tMLX5_SET(create_qp_in, in, wq_umem_valid, 1);\n+\t} else {\n+\t\t/* Special QP to be managed by FW - no SQ\\RQ\\CQ\\UAR\\DB rec. */\n+\t\tMLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);\n+\t\tMLX5_SET(qpc, qpc, no_sq, 1);\n+\t}\n+\tqp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n+\t\t\t\t\t\t sizeof(out));\n+\tif (!qp_obj->obj) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create QP Obj using DevX.\");\n+\t\trte_free(qp_obj);\n+\t\treturn NULL;\n+\t}\n+\tqp_obj->id = MLX5_GET(create_qp_out, out, qpn);\n+\treturn qp_obj;\n+}\n+\n+/**\n+ * Modify QP using DevX API.\n+ * Currently supports only force loop-back QP.\n+ *\n+ * @param[in] qp\n+ * Pointer to QP object structure.\n+ * @param [in] qp_st_mod_op\n+ * The QP state modification operation.\n+ * @param [in] remote_qp_id\n+ * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,\n+\t\t\t uint32_t remote_qp_id)\n+{\n+\tunion {\n+\t\tuint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];\n+\t\tuint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];\n+\t\tuint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];\n+\t} in;\n+\tunion {\n+\t\tuint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];\n+\t\tuint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];\n+\t\tuint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];\n+\t} out;\n+\tvoid *qpc;\n+\tint ret;\n+\tunsigned int inlen;\n+\tunsigned int outlen;\n+\n+\tmemset(&in, 0, sizeof(in));\n+\tmemset(&out, 0, sizeof(out));\n+\tMLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);\n+\tswitch (qp_st_mod_op) {\n+\tcase MLX5_CMD_OP_RST2INIT_QP:\n+\t\tMLX5_SET(rst2init_qp_in, &in, qpn, qp->id);\n+\t\tqpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);\n+\t\tMLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);\n+\t\tMLX5_SET(qpc, qpc, rre, 1);\n+\t\tMLX5_SET(qpc, qpc, rwe, 1);\n+\t\tMLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);\n+\t\tinlen = sizeof(in.rst2init);\n+\t\toutlen = sizeof(out.rst2init);\n+\t\tbreak;\n+\tcase MLX5_CMD_OP_INIT2RTR_QP:\n+\t\tMLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);\n+\t\tqpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);\n+\t\tMLX5_SET(qpc, qpc, primary_address_path.fl, 1);\n+\t\tMLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);\n+\t\tMLX5_SET(qpc, qpc, mtu, 1);\n+\t\tMLX5_SET(qpc, qpc, log_msg_max, 30);\n+\t\tMLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);\n+\t\tMLX5_SET(qpc, qpc, min_rnr_nak, 0);\n+\t\tinlen = sizeof(in.init2rtr);\n+\t\toutlen = sizeof(out.init2rtr);\n+\t\tbreak;\n+\tcase MLX5_CMD_OP_RTR2RTS_QP:\n+\t\tqpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);\n+\t\tMLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);\n+\t\tMLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);\n+\t\tMLX5_SET(qpc, qpc, log_ack_req_freq, 0);\n+\t\tMLX5_SET(qpc, qpc, retry_count, 7);\n+\t\tMLX5_SET(qpc, qpc, rnr_retry, 7);\n+\t\tinlen = sizeof(in.rtr2rts);\n+\t\toutlen = sizeof(out.rtr2rts);\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Invalid or unsupported QP modify op %u.\",\n+\t\t\tqp_st_mod_op);\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP using DevX.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\treturn ret;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 1631c08..d1a21b8 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -279,6 +279,22 @@ struct mlx5_devx_virtq_attr {\n \t} umems[3];\n };\n \n+\n+struct mlx5_devx_qp_attr {\n+\tuint32_t pd:24;\n+\tuint32_t uar_index:24;\n+\tuint32_t cqn:24;\n+\tuint32_t log_page_size:5;\n+\tuint32_t rq_size:17; /* Must be power of 2. */\n+\tuint32_t log_rq_stride:3;\n+\tuint32_t sq_size:17; /* Must be power of 2. */\n+\tuint32_t dbr_umem_valid:1;\n+\tuint32_t dbr_umem_id;\n+\tuint64_t dbr_address;\n+\tuint32_t wq_umem_id;\n+\tuint64_t wq_umem_offset;\n+};\n+\n /* mlx5_devx_cmds.c */\n \n struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n@@ -323,5 +339,9 @@ int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,\n \t\t\t struct mlx5_devx_virtq_attr *attr);\n int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,\n \t\t\t struct mlx5_devx_virtq_attr *attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_qp_attr *attr);\n+int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,\n+\t\t\t\t uint32_t qp_st_mod_op, uint32_t remote_qp_id);\n \n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4b8a34c..e53dd61 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -724,6 +724,19 @@ enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_CREATE_MKEY = 0x200,\n \tMLX5_CMD_OP_CREATE_CQ = 0x400,\n+\tMLX5_CMD_OP_CREATE_QP = 0x500,\n+\tMLX5_CMD_OP_RST2INIT_QP = 0x502,\n+\tMLX5_CMD_OP_INIT2RTR_QP = 0x503,\n+\tMLX5_CMD_OP_RTR2RTS_QP = 0x504,\n+\tMLX5_CMD_OP_RTS2RTS_QP = 0x505,\n+\tMLX5_CMD_OP_SQERR2RTS_QP = 0x506,\n+\tMLX5_CMD_OP_QP_2ERR = 0x507,\n+\tMLX5_CMD_OP_QP_2RST = 0x50A,\n+\tMLX5_CMD_OP_QUERY_QP = 0x50B,\n+\tMLX5_CMD_OP_SQD2RTS_QP = 0x50C,\n+\tMLX5_CMD_OP_INIT2INIT_QP = 0x50E,\n+\tMLX5_CMD_OP_SUSPEND_QP = 0x50F,\n+\tMLX5_CMD_OP_RESUME_QP = 0x510,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n \tMLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,\n \tMLX5_CMD_OP_CREATE_TIR = 0x900,\n@@ -747,6 +760,9 @@ enum {\n \tMLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,\n };\n \n+#define MLX5_ADAPTER_PAGE_SHIFT 12\n+#define MLX5_LOG_RQ_STRIDE_SHIFT 4\n+\n /* Flow counters. */\n struct mlx5_ifc_alloc_flow_counter_out_bits {\n \tu8 status[0x8];\n@@ -2034,6 +2050,366 @@ struct mlx5_ifc_query_virtq_out_bits {\n \tstruct mlx5_ifc_virtio_net_q_bits virtq;\n };\n \n+enum {\n+\tMLX5_QP_ST_RC = 0x0,\n+};\n+\n+enum {\n+\tMLX5_QP_PM_MIGRATED = 0x3,\n+};\n+\n+enum {\n+\tMLX5_NON_ZERO_RQ = 0x0,\n+\tMLX5_SRQ_RQ = 0x1,\n+\tMLX5_CRQ_RQ = 0x2,\n+\tMLX5_ZERO_LEN_RQ = 0x3,\n+};\n+\n+struct mlx5_ifc_ads_bits {\n+\tu8 fl[0x1];\n+\tu8 free_ar[0x1];\n+\tu8 reserved_at_2[0xe];\n+\tu8 pkey_index[0x10];\n+\tu8 reserved_at_20[0x8];\n+\tu8 grh[0x1];\n+\tu8 mlid[0x7];\n+\tu8 rlid[0x10];\n+\tu8 ack_timeout[0x5];\n+\tu8 reserved_at_45[0x3];\n+\tu8 src_addr_index[0x8];\n+\tu8 reserved_at_50[0x4];\n+\tu8 stat_rate[0x4];\n+\tu8 hop_limit[0x8];\n+\tu8 reserved_at_60[0x4];\n+\tu8 tclass[0x8];\n+\tu8 flow_label[0x14];\n+\tu8 rgid_rip[16][0x8];\n+\tu8 reserved_at_100[0x4];\n+\tu8 f_dscp[0x1];\n+\tu8 f_ecn[0x1];\n+\tu8 reserved_at_106[0x1];\n+\tu8 f_eth_prio[0x1];\n+\tu8 ecn[0x2];\n+\tu8 dscp[0x6];\n+\tu8 udp_sport[0x10];\n+\tu8 dei_cfi[0x1];\n+\tu8 eth_prio[0x3];\n+\tu8 sl[0x4];\n+\tu8 vhca_port_num[0x8];\n+\tu8 rmac_47_32[0x10];\n+\tu8 rmac_31_0[0x20];\n+};\n+\n+struct mlx5_ifc_qpc_bits {\n+\tu8 state[0x4];\n+\tu8 lag_tx_port_affinity[0x4];\n+\tu8 st[0x8];\n+\tu8 reserved_at_10[0x3];\n+\tu8 pm_state[0x2];\n+\tu8 reserved_at_15[0x1];\n+\tu8 req_e2e_credit_mode[0x2];\n+\tu8 offload_type[0x4];\n+\tu8 end_padding_mode[0x2];\n+\tu8 reserved_at_1e[0x2];\n+\tu8 wq_signature[0x1];\n+\tu8 block_lb_mc[0x1];\n+\tu8 atomic_like_write_en[0x1];\n+\tu8 latency_sensitive[0x1];\n+\tu8 reserved_at_24[0x1];\n+\tu8 drain_sigerr[0x1];\n+\tu8 reserved_at_26[0x2];\n+\tu8 pd[0x18];\n+\tu8 mtu[0x3];\n+\tu8 log_msg_max[0x5];\n+\tu8 reserved_at_48[0x1];\n+\tu8 log_rq_size[0x4];\n+\tu8 log_rq_stride[0x3];\n+\tu8 no_sq[0x1];\n+\tu8 log_sq_size[0x4];\n+\tu8 reserved_at_55[0x6];\n+\tu8 rlky[0x1];\n+\tu8 ulp_stateless_offload_mode[0x4];\n+\tu8 counter_set_id[0x8];\n+\tu8 uar_page[0x18];\n+\tu8 reserved_at_80[0x8];\n+\tu8 user_index[0x18];\n+\tu8 reserved_at_a0[0x3];\n+\tu8 log_page_size[0x5];\n+\tu8 remote_qpn[0x18];\n+\tstruct mlx5_ifc_ads_bits primary_address_path;\n+\tstruct mlx5_ifc_ads_bits secondary_address_path;\n+\tu8 log_ack_req_freq[0x4];\n+\tu8 reserved_at_384[0x4];\n+\tu8 log_sra_max[0x3];\n+\tu8 reserved_at_38b[0x2];\n+\tu8 retry_count[0x3];\n+\tu8 rnr_retry[0x3];\n+\tu8 reserved_at_393[0x1];\n+\tu8 fre[0x1];\n+\tu8 cur_rnr_retry[0x3];\n+\tu8 cur_retry_count[0x3];\n+\tu8 reserved_at_39b[0x5];\n+\tu8 reserved_at_3a0[0x20];\n+\tu8 reserved_at_3c0[0x8];\n+\tu8 next_send_psn[0x18];\n+\tu8 reserved_at_3e0[0x8];\n+\tu8 cqn_snd[0x18];\n+\tu8 reserved_at_400[0x8];\n+\tu8 deth_sqpn[0x18];\n+\tu8 reserved_at_420[0x20];\n+\tu8 reserved_at_440[0x8];\n+\tu8 last_acked_psn[0x18];\n+\tu8 reserved_at_460[0x8];\n+\tu8 ssn[0x18];\n+\tu8 reserved_at_480[0x8];\n+\tu8 log_rra_max[0x3];\n+\tu8 reserved_at_48b[0x1];\n+\tu8 atomic_mode[0x4];\n+\tu8 rre[0x1];\n+\tu8 rwe[0x1];\n+\tu8 rae[0x1];\n+\tu8 reserved_at_493[0x1];\n+\tu8 page_offset[0x6];\n+\tu8 reserved_at_49a[0x3];\n+\tu8 cd_slave_receive[0x1];\n+\tu8 cd_slave_send[0x1];\n+\tu8 cd_master[0x1];\n+\tu8 reserved_at_4a0[0x3];\n+\tu8 min_rnr_nak[0x5];\n+\tu8 next_rcv_psn[0x18];\n+\tu8 reserved_at_4c0[0x8];\n+\tu8 xrcd[0x18];\n+\tu8 reserved_at_4e0[0x8];\n+\tu8 cqn_rcv[0x18];\n+\tu8 dbr_addr[0x40];\n+\tu8 q_key[0x20];\n+\tu8 reserved_at_560[0x5];\n+\tu8 rq_type[0x3];\n+\tu8 srqn_rmpn_xrqn[0x18];\n+\tu8 reserved_at_580[0x8];\n+\tu8 rmsn[0x18];\n+\tu8 hw_sq_wqebb_counter[0x10];\n+\tu8 sw_sq_wqebb_counter[0x10];\n+\tu8 hw_rq_counter[0x20];\n+\tu8 sw_rq_counter[0x20];\n+\tu8 reserved_at_600[0x20];\n+\tu8 reserved_at_620[0xf];\n+\tu8 cgs[0x1];\n+\tu8 cs_req[0x8];\n+\tu8 cs_res[0x8];\n+\tu8 dc_access_key[0x40];\n+\tu8 reserved_at_680[0x3];\n+\tu8 dbr_umem_valid[0x1];\n+\tu8 reserved_at_684[0x9c];\n+\tu8 dbr_umem_id[0x20];\n+};\n+\n+struct mlx5_ifc_create_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_create_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x40];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 wq_umem_offset[0x40];\n+\tu8 wq_umem_id[0x20];\n+\tu8 wq_umem_valid[0x1];\n+\tu8 reserved_at_861[0x1f];\n+\tu8 pas[0][0x40];\n+};\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n+struct mlx5_ifc_sqerr2rts_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_sqerr2rts_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_sqd2rts_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_sqd2rts_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_rts2rts_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_rts2rts_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_rtr2rts_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_rtr2rts_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_rst2init_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_rst2init_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_init2rtr_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_init2rtr_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+struct mlx5_ifc_init2init_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_init2init_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_query_qp_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tu8 opt_param_mask[0x20];\n+\tu8 reserved_at_a0[0x20];\n+\tstruct mlx5_ifc_qpc_bits qpc;\n+\tu8 reserved_at_800[0x80];\n+\tu8 pas[0][0x40];\n+};\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n+struct mlx5_ifc_query_qp_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 qpn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex f3082ce..df8e064 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -2,6 +2,7 @@ DPDK_20.02 {\n \tglobal:\n \n \tmlx5_devx_cmd_create_cq;\n+\tmlx5_devx_cmd_create_qp;\n \tmlx5_devx_cmd_create_rq;\n \tmlx5_devx_cmd_create_rqt;\n \tmlx5_devx_cmd_create_sq;\n@@ -14,6 +15,7 @@ DPDK_20.02 {\n \tmlx5_devx_cmd_flow_counter_query;\n \tmlx5_devx_cmd_flow_dump;\n \tmlx5_devx_cmd_mkey_create;\n+\tmlx5_devx_cmd_modify_qp_state;\n \tmlx5_devx_cmd_modify_rq;\n \tmlx5_devx_cmd_modify_sq;\n \tmlx5_devx_cmd_modify_virtq;\n", "prefixes": [ "v2", "16/25" ] }