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{
    "id": 65094,
    "url": "http://patches.dpdk.org/api/patches/65094/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579803629-152938-6-git-send-email-akozyrev@mellanox.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1579803629-152938-6-git-send-email-akozyrev@mellanox.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1579803629-152938-6-git-send-email-akozyrev@mellanox.com",
    "date": "2020-01-23T18:20:29",
    "name": "[v2,5/5] net/mlx5: introduce the mlx5 version of the assert",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0b3eaee289dc9d93096c8e8e3c5f79a77bd3b72c",
    "submitter": {
        "id": 1573,
        "url": "http://patches.dpdk.org/api/people/1573/?format=api",
        "name": "Alexander Kozyrev",
        "email": "akozyrev@mellanox.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579803629-152938-6-git-send-email-akozyrev@mellanox.com/mbox/",
    "series": [
        {
            "id": 8278,
            "url": "http://patches.dpdk.org/api/series/8278/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8278",
            "date": "2020-01-23T18:20:24",
            "name": "net/mlx: assert cleanup in mlx drivers",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/8278/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/65094/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/65094/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3DFC6A0530;\n\tThu, 23 Jan 2020 19:21:28 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 765091BC25;\n\tThu, 23 Jan 2020 19:20:43 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 7307634F3\n for <dev@dpdk.org>; Thu, 23 Jan 2020 19:20:35 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n akozyrev@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 23 Jan 2020 20:20:30 +0200",
            "from pegasus02.mtr.labs.mlnx. (pegasus02.mtr.labs.mlnx\n [10.210.16.122])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00NIKUb5026240;\n Thu, 23 Jan 2020 20:20:30 +0200"
        ],
        "From": "Alexander Kozyrev <akozyrev@mellanox.com>",
        "To": "dev@dpdk.org",
        "Cc": "rasland@mellanox.com, matan@mellanox.com, viacheslavo@mellanox.com,\n ferruh.yigit@intel.com, thomas@monjalon.net",
        "Date": "Thu, 23 Jan 2020 20:20:29 +0200",
        "Message-Id": "<1579803629-152938-6-git-send-email-akozyrev@mellanox.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1579803629-152938-1-git-send-email-akozyrev@mellanox.com>",
        "References": "<1579789555-23239-1-git-send-email-akozyrev@mellanox.com>\n <1579803629-152938-1-git-send-email-akozyrev@mellanox.com>",
        "Subject": "[dpdk-dev] [PATCH v2 5/5] net/mlx5: introduce the mlx5 version of\n\tthe assert",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Use the MLX5_ASSERT macros instead of the standard assert clause.\nDepends on the MLX5_DEBUG configuration option to define it.\nIf MLX5_DEBUG is enabled MLX5_ASSERT is equal to RTE_VERIFY\nto bypass the global CONFIG_RTE_ENABLE_ASSERT option.\nIf MLX5_DEBUG is disabled, the global CONFIG_RTE_ENABLE_ASSERT\ncan still enable this assert by calling RTE_VERIFY inside RTE_ASSERT.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c                  |  77 +++++----\n drivers/net/mlx5/mlx5_devx_cmds.c        |   4 +-\n drivers/net/mlx5/mlx5_ethdev.c           |  69 ++++----\n drivers/net/mlx5/mlx5_flow.c             |  69 ++++----\n drivers/net/mlx5/mlx5_flow_dv.c          |  95 ++++++-----\n drivers/net/mlx5/mlx5_flow_meter.c       |  12 +-\n drivers/net/mlx5/mlx5_flow_verbs.c       |   4 +-\n drivers/net/mlx5/mlx5_mac.c              |   5 +-\n drivers/net/mlx5/mlx5_mp.c               |  29 ++--\n drivers/net/mlx5/mlx5_mr.c               |  67 ++++----\n drivers/net/mlx5/mlx5_nl.c               |  24 +--\n drivers/net/mlx5/mlx5_prm.h              |   3 +-\n drivers/net/mlx5/mlx5_rss.c              |   3 +-\n drivers/net/mlx5/mlx5_rxq.c              |  41 +++--\n drivers/net/mlx5/mlx5_rxtx.c             | 281 ++++++++++++++++---------------\n drivers/net/mlx5/mlx5_rxtx_vec.c         |   1 -\n drivers/net/mlx5/mlx5_rxtx_vec.h         |   7 +-\n drivers/net/mlx5/mlx5_rxtx_vec_altivec.h |  11 +-\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h    |  11 +-\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h     |  11 +-\n drivers/net/mlx5/mlx5_socket.c           |   4 +-\n drivers/net/mlx5/mlx5_stats.c            |   2 +-\n drivers/net/mlx5/mlx5_txq.c              |  57 +++----\n drivers/net/mlx5/mlx5_utils.c            |   8 +-\n drivers/net/mlx5/mlx5_utils.h            |  22 ++-\n drivers/net/mlx5/mlx5_vlan.c             |   7 +-\n 26 files changed, 462 insertions(+), 462 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 5124491..961d27f 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -6,7 +6,6 @@\n #include <stddef.h>\n #include <unistd.h>\n #include <string.h>\n-#include <assert.h>\n #include <dlfcn.h>\n #include <stdint.h>\n #include <stdlib.h>\n@@ -290,7 +289,7 @@ struct mlx5_flow_id_pool *\n \tif (pool->curr == pool->last) {\n \t\tsize = pool->curr - pool->free_arr;\n \t\tsize2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;\n-\t\tassert(size2 > size);\n+\t\tMLX5_ASSERT(size2 > size);\n \t\tmem = rte_malloc(\"\", size2 * sizeof(uint32_t), 0);\n \t\tif (!mem) {\n \t\t\tDRV_LOG(ERR, \"can't allocate mem for id pool\");\n@@ -436,7 +435,7 @@ struct mlx5_flow_id_pool *\n \tchar *env;\n \tint value;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \t/* Get environment variable to store. */\n \tenv = getenv(MLX5_SHUT_UP_BF);\n \tvalue = env ? !!strcmp(env, \"0\") : MLX5_ARG_UNSET;\n@@ -451,7 +450,7 @@ struct mlx5_flow_id_pool *\n static void\n mlx5_restore_doorbell_mapping_env(int value)\n {\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \t/* Restore the original environment variable state. */\n \tif (value == MLX5_ARG_UNSET)\n \t\tunsetenv(MLX5_SHUT_UP_BF);\n@@ -491,9 +490,9 @@ struct mlx5_flow_id_pool *\n \tstruct mlx5_devx_tis_attr tis_attr = { 0 };\n #endif\n \n-\tassert(spawn);\n+\tMLX5_ASSERT(spawn);\n \t/* Secondary process should not create the shared context. */\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tpthread_mutex_lock(&mlx5_ibv_list_mutex);\n \t/* Search for IB context by device name. */\n \tLIST_FOREACH(sh, &mlx5_ibv_list, next) {\n@@ -503,7 +502,7 @@ struct mlx5_flow_id_pool *\n \t\t}\n \t}\n \t/* No device found, we have to create new shared context. */\n-\tassert(spawn->max_port);\n+\tMLX5_ASSERT(spawn->max_port);\n \tsh = rte_zmalloc(\"ethdev shared ib context\",\n \t\t\t sizeof(struct mlx5_ibv_shared) +\n \t\t\t spawn->max_port *\n@@ -626,7 +625,7 @@ struct mlx5_flow_id_pool *\n \treturn sh;\n error:\n \tpthread_mutex_unlock(&mlx5_ibv_list_mutex);\n-\tassert(sh);\n+\tMLX5_ASSERT(sh);\n \tif (sh->tis)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(sh->tis));\n \tif (sh->td)\n@@ -638,7 +637,7 @@ struct mlx5_flow_id_pool *\n \tif (sh->flow_id_pool)\n \t\tmlx5_flow_id_pool_release(sh->flow_id_pool);\n \trte_free(sh);\n-\tassert(err > 0);\n+\tMLX5_ASSERT(err > 0);\n \trte_errno = err;\n \treturn NULL;\n }\n@@ -661,16 +660,16 @@ struct mlx5_flow_id_pool *\n \tLIST_FOREACH(lctx, &mlx5_ibv_list, next)\n \t\tif (lctx == sh)\n \t\t\tbreak;\n-\tassert(lctx);\n+\tMLX5_ASSERT(lctx);\n \tif (lctx != sh) {\n \t\tDRV_LOG(ERR, \"Freeing non-existing shared IB context\");\n \t\tgoto exit;\n \t}\n #endif\n-\tassert(sh);\n-\tassert(sh->refcnt);\n+\tMLX5_ASSERT(sh);\n+\tMLX5_ASSERT(sh->refcnt);\n \t/* Secondary process should not free the shared context. */\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tif (--sh->refcnt)\n \t\tgoto exit;\n \t/* Release created Memory Regions. */\n@@ -686,7 +685,7 @@ struct mlx5_flow_id_pool *\n \t *  Only primary process handles async device events.\n \t **/\n \tmlx5_flow_counters_mng_close(sh);\n-\tassert(!sh->intr_cnt);\n+\tMLX5_ASSERT(!sh->intr_cnt);\n \tif (sh->intr_cnt)\n \t\tmlx5_intr_callback_unregister\n \t\t\t(&sh->intr_handle, mlx5_dev_interrupt_handler, sh);\n@@ -742,7 +741,7 @@ struct mlx5_flow_id_pool *\n \tif (pos) {\n \t\ttbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,\n \t\t\t\t\tentry);\n-\t\tassert(tbl_data);\n+\t\tMLX5_ASSERT(tbl_data);\n \t\tmlx5_hlist_remove(sh->flow_tbls, pos);\n \t\trte_free(tbl_data);\n \t}\n@@ -751,7 +750,7 @@ struct mlx5_flow_id_pool *\n \tif (pos) {\n \t\ttbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,\n \t\t\t\t\tentry);\n-\t\tassert(tbl_data);\n+\t\tMLX5_ASSERT(tbl_data);\n \t\tmlx5_hlist_remove(sh->flow_tbls, pos);\n \t\trte_free(tbl_data);\n \t}\n@@ -761,7 +760,7 @@ struct mlx5_flow_id_pool *\n \tif (pos) {\n \t\ttbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,\n \t\t\t\t\tentry);\n-\t\tassert(tbl_data);\n+\t\tMLX5_ASSERT(tbl_data);\n \t\tmlx5_hlist_remove(sh->flow_tbls, pos);\n \t\trte_free(tbl_data);\n \t}\n@@ -785,7 +784,7 @@ struct mlx5_flow_id_pool *\n \tchar s[MLX5_HLIST_NAMESIZE];\n \tint err = 0;\n \n-\tassert(sh);\n+\tMLX5_ASSERT(sh);\n \tsnprintf(s, sizeof(s), \"%s_flow_table\", priv->sh->ibdev_name);\n \tsh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);\n \tif (!sh->flow_tbls) {\n@@ -976,9 +975,9 @@ struct mlx5_flow_id_pool *\n \t\treturn;\n \tpriv->dr_shared = 0;\n \tsh = priv->sh;\n-\tassert(sh);\n+\tMLX5_ASSERT(sh);\n #ifdef HAVE_MLX5DV_DR\n-\tassert(sh->dv_refcnt);\n+\tMLX5_ASSERT(sh->dv_refcnt);\n \tif (sh->dv_refcnt && --sh->dv_refcnt)\n \t\treturn;\n \tif (sh->rx_domain) {\n@@ -1113,7 +1112,7 @@ struct mlx5_flow_id_pool *\n \n \t\tsocket = ctrl->socket;\n \t}\n-\tassert(data != NULL);\n+\tMLX5_ASSERT(data != NULL);\n \tret = rte_malloc_socket(__func__, size, alignment, socket);\n \tif (!ret && size)\n \t\trte_errno = ENOMEM;\n@@ -1131,7 +1130,7 @@ struct mlx5_flow_id_pool *\n static void\n mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)\n {\n-\tassert(data != NULL);\n+\tMLX5_ASSERT(data != NULL);\n \trte_free(ptr);\n }\n \n@@ -1150,7 +1149,7 @@ struct mlx5_flow_id_pool *\n mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,\n \t\t\t struct rte_eth_udp_tunnel *udp_tunnel)\n {\n-\tassert(udp_tunnel != NULL);\n+\tMLX5_ASSERT(udp_tunnel != NULL);\n \tif (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&\n \t    udp_tunnel->udp_port == 4789)\n \t\treturn 0;\n@@ -1662,7 +1661,7 @@ struct mlx5_flow_id_pool *\n \tif (mlx5_init_shared_data())\n \t\treturn -rte_errno;\n \tsd = mlx5_shared_data;\n-\tassert(sd);\n+\tMLX5_ASSERT(sd);\n \trte_spinlock_lock(&sd->lock);\n \tswitch (rte_eal_process_type()) {\n \tcase RTE_PROC_PRIMARY:\n@@ -1844,7 +1843,7 @@ struct mlx5_flow_id_pool *\n \tdefault:\n \t\tmeta = 0;\n \t\tmark = 0;\n-\t\tassert(false);\n+\t\tMLX5_ASSERT(false);\n \t\tbreak;\n \t}\n \tif (sh->dv_mark_mask && sh->dv_mark_mask != mark)\n@@ -1937,7 +1936,7 @@ struct mlx5_flow_id_pool *\n \t\t; /* Empty. */\n \t/* Find the first clear bit. */\n \tj = rte_bsf64(~page->dbr_bitmap[i]);\n-\tassert(i < (MLX5_DBR_PER_PAGE / 64));\n+\tMLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));\n \tpage->dbr_bitmap[i] |= (1 << j);\n \tpage->dbr_count++;\n \t*dbr_page = page;\n@@ -2011,7 +2010,7 @@ struct mlx5_flow_id_pool *\n \tstruct mlx5_dev_config *sh_conf = NULL;\n \tuint16_t port_id;\n \n-\tassert(sh);\n+\tMLX5_ASSERT(sh);\n \t/* Nothing to compare for the single/first device. */\n \tif (sh->refcnt == 1)\n \t\treturn 0;\n@@ -2591,7 +2590,7 @@ struct mlx5_flow_id_pool *\n \t * is permanent throughout the lifetime of device. So, we may store\n \t * the ifindex here and use the cached value further.\n \t */\n-\tassert(spawn->ifindex);\n+\tMLX5_ASSERT(spawn->ifindex);\n \tpriv->if_index = spawn->ifindex;\n \teth_dev->data->dev_private = priv;\n \tpriv->dev_data = eth_dev->data;\n@@ -2766,7 +2765,7 @@ struct mlx5_flow_id_pool *\n \t}\n \tif (sh)\n \t\tmlx5_free_shared_ibctx(sh);\n-\tassert(err > 0);\n+\tMLX5_ASSERT(err > 0);\n \trte_errno = err;\n \treturn NULL;\n }\n@@ -2869,7 +2868,7 @@ struct mlx5_flow_id_pool *\n \tif (!file)\n \t\treturn -1;\n \t/* Use safe format to check maximal buffer length. */\n-\tassert(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);\n+\tMLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);\n \twhile (fscanf(file, \"%\" RTE_STR(IF_NAMESIZE) \"s\", ifname) == 1) {\n \t\tchar tmp_str[IF_NAMESIZE + 32];\n \t\tstruct rte_pci_addr pci_addr;\n@@ -2962,7 +2961,7 @@ struct mlx5_flow_id_pool *\n \t\t\tstrerror(rte_errno));\n \t\treturn -rte_errno;\n \t}\n-\tassert(pci_drv == &mlx5_driver);\n+\tMLX5_ASSERT(pci_drv == &mlx5_driver);\n \terrno = 0;\n \tibv_list = mlx5_glue->get_device_list(&ret);\n \tif (!ibv_list) {\n@@ -3083,10 +3082,10 @@ struct mlx5_flow_id_pool *\n \t\t * it may be E-Switch master device and representors.\n \t\t * We have to perform identification trough the ports.\n \t\t */\n-\t\tassert(nl_rdma >= 0);\n-\t\tassert(ns == 0);\n-\t\tassert(nd == 1);\n-\t\tassert(np);\n+\t\tMLX5_ASSERT(nl_rdma >= 0);\n+\t\tMLX5_ASSERT(ns == 0);\n+\t\tMLX5_ASSERT(nd == 1);\n+\t\tMLX5_ASSERT(np);\n \t\tfor (i = 1; i <= np; ++i) {\n \t\t\tlist[ns].max_port = np;\n \t\t\tlist[ns].ibv_port = i;\n@@ -3261,7 +3260,7 @@ struct mlx5_flow_id_pool *\n \t\t\tgoto exit;\n \t\t}\n \t}\n-\tassert(ns);\n+\tMLX5_ASSERT(ns);\n \t/*\n \t * Sort list to probe devices in natural order for users convenience\n \t * (i.e. master first, then representors from lowest to highest ID).\n@@ -3356,7 +3355,7 @@ struct mlx5_flow_id_pool *\n \t\tclose(nl_route);\n \tif (list)\n \t\trte_free(list);\n-\tassert(ibv_list);\n+\tMLX5_ASSERT(ibv_list);\n \tmlx5_glue->free_device_list(ibv_list);\n \treturn ret;\n }\n@@ -3656,7 +3655,7 @@ struct mlx5_flow_id_pool *\n #ifdef RTE_IBVERBS_LINK_DLOPEN\n \tif (mlx5_glue_init())\n \t\treturn;\n-\tassert(mlx5_glue);\n+\tMLX5_ASSERT(mlx5_glue);\n #endif\n #ifdef MLX5_DEBUG\n \t/* Glue structure must not contain any NULL pointers. */\n@@ -3664,7 +3663,7 @@ struct mlx5_flow_id_pool *\n \t\tunsigned int i;\n \n \t\tfor (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)\n-\t\t\tassert(((const void *const *)mlx5_glue)[i]);\n+\t\t\tMLX5_ASSERT(((const void *const *)mlx5_glue)[i]);\n \t}\n #endif\n \tif (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex 9985d30..a517b6e 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -954,11 +954,11 @@ struct mlx5_devx_obj *\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n-\tassert(sh->rx_domain);\n+\tMLX5_ASSERT(sh->rx_domain);\n \tret = mlx5_glue->dr_dump_domain(file, sh->rx_domain);\n \tif (ret)\n \t\treturn ret;\n-\tassert(sh->tx_domain);\n+\tMLX5_ASSERT(sh->tx_domain);\n \tret = mlx5_glue->dr_dump_domain(file, sh->tx_domain);\n #else\n \tret = ENOTSUP;\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 3b4c5db..0a31dbc 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -4,7 +4,6 @@\n  */\n \n #include <stddef.h>\n-#include <assert.h>\n #include <inttypes.h>\n #include <unistd.h>\n #include <stdbool.h>\n@@ -138,7 +137,7 @@ struct ethtool_link_settings {\n \tunsigned int dev_port_prev = ~0u;\n \tchar match[IF_NAMESIZE] = \"\";\n \n-\tassert(ibdev_path);\n+\tMLX5_ASSERT(ibdev_path);\n \t{\n \t\tMKSTR(path, \"%s/device/net\", ibdev_path);\n \n@@ -223,8 +222,8 @@ struct ethtool_link_settings {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunsigned int ifindex;\n \n-\tassert(priv);\n-\tassert(priv->sh);\n+\tMLX5_ASSERT(priv);\n+\tMLX5_ASSERT(priv->sh);\n \tifindex = mlx5_ifindex(dev);\n \tif (!ifindex) {\n \t\tif (!priv->representor)\n@@ -254,8 +253,8 @@ struct ethtool_link_settings {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunsigned int ifindex;\n \n-\tassert(priv);\n-\tassert(priv->if_index);\n+\tMLX5_ASSERT(priv);\n+\tMLX5_ASSERT(priv->if_index);\n \tifindex = priv->if_index;\n \tif (!ifindex)\n \t\trte_errno = ENXIO;\n@@ -575,7 +574,7 @@ struct ethtool_link_settings {\n \tinlen = (config->txq_inline_max == MLX5_ARG_UNSET) ?\n \t\tMLX5_SEND_DEF_INLINE_LEN :\n \t\t(unsigned int)config->txq_inline_max;\n-\tassert(config->txq_inline_min >= 0);\n+\tMLX5_ASSERT(config->txq_inline_min >= 0);\n \tinlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min);\n \tinlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX +\n \t\t\t       MLX5_ESEG_MIN_INLINE_SIZE -\n@@ -654,7 +653,7 @@ struct ethtool_link_settings {\n \t\t\t    priv->pf_bond > MLX5_PORT_ID_BONDING_PF_MASK) {\n \t\t\t\tDRV_LOG(ERR, \"can't update switch port ID\"\n \t\t\t\t\t     \" for bonding device\");\n-\t\t\t\tassert(false);\n+\t\t\t\tMLX5_ASSERT(false);\n \t\t\t\treturn -ENODEV;\n \t\t\t}\n \t\t\tinfo->switch_info.port_id |=\n@@ -792,7 +791,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \n \tpriv = dev->data->dev_private;\n \tdomain_id = priv->domain_id;\n-\tassert(priv->representor);\n+\tMLX5_ASSERT(priv->representor);\n \tMLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {\n \t\tstruct mlx5_priv *opriv =\n \t\t\trte_eth_devices[port_id].data->dev_private;\n@@ -1283,7 +1282,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\t\tcontinue;\n \t\t}\n \t\tdev = &rte_eth_devices[sh->port[i].ih_port_id];\n-\t\tassert(dev);\n+\t\tMLX5_ASSERT(dev);\n \t\tif (dev->data->dev_conf.intr_conf.rmv)\n \t\t\t_rte_eth_dev_callback_process\n \t\t\t\t(dev, RTE_ETH_EVENT_INTR_RMV, NULL);\n@@ -1322,7 +1321,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\t\tmlx5_dev_interrupt_device_fatal(sh);\n \t\t\tcontinue;\n \t\t}\n-\t\tassert(tmp && (tmp <= sh->max_port));\n+\t\tMLX5_ASSERT(tmp && (tmp <= sh->max_port));\n \t\tif (!tmp) {\n \t\t\t/* Unsupported devive level event. */\n \t\t\tmlx5_glue->ack_async_event(&event);\n@@ -1352,7 +1351,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\t/* Retrieve ethernet device descriptor. */\n \t\ttmp = sh->port[tmp - 1].ih_port_id;\n \t\tdev = &rte_eth_devices[tmp];\n-\t\tassert(dev);\n+\t\tMLX5_ASSERT(dev);\n \t\tif ((event.event_type == IBV_EVENT_PORT_ACTIVE ||\n \t\t     event.event_type == IBV_EVENT_PORT_ERR) &&\n \t\t\tdev->data->dev_conf.intr_conf.lsc) {\n@@ -1407,7 +1406,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\tif (ret != -EAGAIN) {\n \t\t\tDRV_LOG(INFO, \"failed to unregister interrupt\"\n \t\t\t\t      \" handler (error: %d)\", ret);\n-\t\t\tassert(false);\n+\t\t\tMLX5_ASSERT(false);\n \t\t\treturn;\n \t\t}\n \t\tif (twait) {\n@@ -1428,7 +1427,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\t\t * on first iteration.\n \t\t\t */\n \t\t\ttwait = rte_get_timer_hz();\n-\t\t\tassert(twait);\n+\t\t\tMLX5_ASSERT(twait);\n \t\t}\n \t\t/*\n \t\t * Timeout elapsed, show message (once a second) and retry.\n@@ -1492,14 +1491,14 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn;\n \tpthread_mutex_lock(&sh->intr_mutex);\n-\tassert(priv->ibv_port);\n-\tassert(priv->ibv_port <= sh->max_port);\n-\tassert(dev->data->port_id < RTE_MAX_ETHPORTS);\n+\tMLX5_ASSERT(priv->ibv_port);\n+\tMLX5_ASSERT(priv->ibv_port <= sh->max_port);\n+\tMLX5_ASSERT(dev->data->port_id < RTE_MAX_ETHPORTS);\n \tif (sh->port[priv->ibv_port - 1].ih_port_id >= RTE_MAX_ETHPORTS)\n \t\tgoto exit;\n-\tassert(sh->port[priv->ibv_port - 1].ih_port_id ==\n+\tMLX5_ASSERT(sh->port[priv->ibv_port - 1].ih_port_id ==\n \t\t\t\t\t(uint32_t)dev->data->port_id);\n-\tassert(sh->intr_cnt);\n+\tMLX5_ASSERT(sh->intr_cnt);\n \tsh->port[priv->ibv_port - 1].ih_port_id = RTE_MAX_ETHPORTS;\n \tif (!sh->intr_cnt || --sh->intr_cnt)\n \t\tgoto exit;\n@@ -1528,13 +1527,13 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn;\n \tpthread_mutex_lock(&sh->intr_mutex);\n-\tassert(priv->ibv_port);\n-\tassert(priv->ibv_port <= sh->max_port);\n-\tassert(dev->data->port_id < RTE_MAX_ETHPORTS);\n+\tMLX5_ASSERT(priv->ibv_port);\n+\tMLX5_ASSERT(priv->ibv_port <= sh->max_port);\n+\tMLX5_ASSERT(dev->data->port_id < RTE_MAX_ETHPORTS);\n \tif (sh->port[priv->ibv_port - 1].devx_ih_port_id >= RTE_MAX_ETHPORTS)\n \t\tgoto exit;\n-\tassert(sh->port[priv->ibv_port - 1].devx_ih_port_id ==\n-\t\t\t\t\t(uint32_t)dev->data->port_id);\n+\tMLX5_ASSERT(sh->port[priv->ibv_port - 1].devx_ih_port_id ==\n+\t\t    (uint32_t)dev->data->port_id);\n \tsh->port[priv->ibv_port - 1].devx_ih_port_id = RTE_MAX_ETHPORTS;\n \tif (!sh->devx_intr_cnt || --sh->devx_intr_cnt)\n \t\tgoto exit;\n@@ -1572,12 +1571,12 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn;\n \tpthread_mutex_lock(&sh->intr_mutex);\n-\tassert(priv->ibv_port);\n-\tassert(priv->ibv_port <= sh->max_port);\n-\tassert(dev->data->port_id < RTE_MAX_ETHPORTS);\n+\tMLX5_ASSERT(priv->ibv_port);\n+\tMLX5_ASSERT(priv->ibv_port <= sh->max_port);\n+\tMLX5_ASSERT(dev->data->port_id < RTE_MAX_ETHPORTS);\n \tif (sh->port[priv->ibv_port - 1].ih_port_id < RTE_MAX_ETHPORTS) {\n \t\t/* The handler is already installed for this port. */\n-\t\tassert(sh->intr_cnt);\n+\t\tMLX5_ASSERT(sh->intr_cnt);\n \t\tgoto exit;\n \t}\n \tif (sh->intr_cnt) {\n@@ -1587,7 +1586,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \t\tgoto exit;\n \t}\n \t/* No shared handler installed. */\n-\tassert(sh->ctx->async_fd > 0);\n+\tMLX5_ASSERT(sh->ctx->async_fd > 0);\n \tflags = fcntl(sh->ctx->async_fd, F_GETFL);\n \tret = fcntl(sh->ctx->async_fd, F_SETFL, flags | O_NONBLOCK);\n \tif (ret) {\n@@ -1626,12 +1625,12 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn;\n \tpthread_mutex_lock(&sh->intr_mutex);\n-\tassert(priv->ibv_port);\n-\tassert(priv->ibv_port <= sh->max_port);\n-\tassert(dev->data->port_id < RTE_MAX_ETHPORTS);\n+\tMLX5_ASSERT(priv->ibv_port);\n+\tMLX5_ASSERT(priv->ibv_port <= sh->max_port);\n+\tMLX5_ASSERT(dev->data->port_id < RTE_MAX_ETHPORTS);\n \tif (sh->port[priv->ibv_port - 1].devx_ih_port_id < RTE_MAX_ETHPORTS) {\n \t\t/* The handler is already installed for this port. */\n-\t\tassert(sh->devx_intr_cnt);\n+\t\tMLX5_ASSERT(sh->devx_intr_cnt);\n \t\tgoto exit;\n \t}\n \tif (sh->devx_intr_cnt) {\n@@ -1762,7 +1761,7 @@ int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n {\n \teth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;\n \n-\tassert(dev != NULL);\n+\tMLX5_ASSERT(dev != NULL);\n \tif (mlx5_check_vec_rx_support(dev) > 0) {\n \t\trx_pkt_burst = mlx5_rx_burst_vec;\n \t\tDRV_LOG(DEBUG, \"port %u selected Rx vectorized function\",\n@@ -1929,7 +1928,7 @@ struct mlx5_priv *\n \t\tmlx5_sysfs_check_switch_info(device_dir, &data);\n \t}\n \t*info = data;\n-\tassert(!(data.master && data.representor));\n+\tMLX5_ASSERT(!(data.master && data.representor));\n \tif (data.master && data.representor) {\n \t\tDRV_LOG(ERR, \"ifindex %u device is recognized as master\"\n \t\t\t     \" and as representor\", ifindex);\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 970123b..5aac844 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -396,7 +396,7 @@ enum modify_reg\n \t\t */\n \t\treturn priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3;\n \tcase MLX5_MTR_COLOR:\n-\t\tRTE_ASSERT(priv->mtr_color_reg != REG_NONE);\n+\t\tMLX5_ASSERT(priv->mtr_color_reg != REG_NONE);\n \t\treturn priv->mtr_color_reg;\n \tcase MLX5_APP_TAG:\n \t\t/*\n@@ -437,7 +437,7 @@ enum modify_reg\n \t\t}\n \t\treturn config->flow_mreg_c[id + start_reg - REG_C_0];\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n \treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t  NULL, \"invalid feature name\");\n@@ -596,7 +596,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n {\n \tunsigned int i;\n \n-\tassert(nic_mask);\n+\tMLX5_ASSERT(nic_mask);\n \tfor (i = 0; i < size; ++i)\n \t\tif ((nic_mask[i] | mask[i]) != nic_mask[i])\n \t\t\treturn rte_flow_error_set(error, ENOTSUP,\n@@ -785,7 +785,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tconst int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL);\n \tunsigned int i;\n \n-\tassert(dev->data->dev_started);\n+\tMLX5_ASSERT(dev->data->dev_started);\n \tfor (i = 0; i != flow->rss.queue_num; ++i) {\n \t\tint idx = (*flow->rss.queue)[i];\n \t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n@@ -1796,7 +1796,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t      MLX5_FLOW_LAYER_OUTER_L4;\n \tint ret;\n \n-\tassert(flow_mask);\n+\tMLX5_ASSERT(flow_mask);\n \tif (target_protocol != 0xff && target_protocol != IPPROTO_TCP)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t  RTE_FLOW_ERROR_TYPE_ITEM, item,\n@@ -2327,7 +2327,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tret = mlx5_flow_id_get(priv->qrss_id_pool, &qrss_id);\n \tif (ret)\n \t\treturn 0;\n-\tassert(qrss_id);\n+\tMLX5_ASSERT(qrss_id);\n \treturn qrss_id;\n }\n \n@@ -2535,7 +2535,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tconst struct mlx5_flow_driver_ops *fops;\n \tenum mlx5_flow_drv_type type = flow->drv_type;\n \n-\tassert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(type);\n \treturn fops->prepare(attr, items, actions, error);\n }\n@@ -2579,7 +2579,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tconst struct mlx5_flow_driver_ops *fops;\n \tenum mlx5_flow_drv_type type = dev_flow->flow->drv_type;\n \n-\tassert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(type);\n \treturn fops->translate(dev, dev_flow, attr, items, actions, error);\n }\n@@ -2606,7 +2606,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tconst struct mlx5_flow_driver_ops *fops;\n \tenum mlx5_flow_drv_type type = flow->drv_type;\n \n-\tassert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(type);\n \treturn fops->apply(dev, flow, error);\n }\n@@ -2628,7 +2628,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tconst struct mlx5_flow_driver_ops *fops;\n \tenum mlx5_flow_drv_type type = flow->drv_type;\n \n-\tassert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(type);\n \tfops->remove(dev, flow);\n }\n@@ -2650,7 +2650,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tenum mlx5_flow_drv_type type = flow->drv_type;\n \n \tflow_mreg_split_qrss_release(dev, flow);\n-\tassert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(type);\n \tfops->destroy(dev, flow);\n }\n@@ -2688,7 +2688,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n static const struct rte_flow_item *\n find_port_id_item(const struct rte_flow_item *item)\n {\n-\tassert(item);\n+\tMLX5_ASSERT(item);\n \tfor (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {\n \t\tif (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID)\n \t\t\treturn item;\n@@ -2790,7 +2790,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n {\n \tint actions_n = 0;\n \n-\tassert(mtr);\n+\tMLX5_ASSERT(mtr);\n \t*mtr = 0;\n \tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n \t\tswitch (actions->type) {\n@@ -2960,13 +2960,14 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\treturn NULL;\n \tcp_mreg.src = ret;\n \t/* Check if already registered. */\n-\tassert(priv->mreg_cp_tbl);\n+\tMLX5_ASSERT(priv->mreg_cp_tbl);\n \tmcp_res = (void *)mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id);\n \tif (mcp_res) {\n \t\t/* For non-default rule. */\n \t\tif (mark_id != MLX5_DEFAULT_COPY_ID)\n \t\t\tmcp_res->refcnt++;\n-\t\tassert(mark_id != MLX5_DEFAULT_COPY_ID || mcp_res->refcnt == 1);\n+\t\tMLX5_ASSERT(mark_id != MLX5_DEFAULT_COPY_ID ||\n+\t\t\t    mcp_res->refcnt == 1);\n \t\treturn mcp_res;\n \t}\n \t/* Provide the full width of FLAG specific value. */\n@@ -3034,7 +3035,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tmcp_res->hlist_ent.key = mark_id;\n \tret = mlx5_hlist_insert(priv->mreg_cp_tbl,\n \t\t\t\t&mcp_res->hlist_ent);\n-\tassert(!ret);\n+\tMLX5_ASSERT(!ret);\n \tif (ret)\n \t\tgoto error;\n \treturn mcp_res;\n@@ -3063,7 +3064,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tif (!mcp_res || !priv->mreg_cp_tbl)\n \t\treturn;\n \tif (flow->copy_applied) {\n-\t\tassert(mcp_res->appcnt);\n+\t\tMLX5_ASSERT(mcp_res->appcnt);\n \t\tflow->copy_applied = 0;\n \t\t--mcp_res->appcnt;\n \t\tif (!mcp_res->appcnt)\n@@ -3075,7 +3076,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t */\n \tif (--mcp_res->refcnt)\n \t\treturn;\n-\tassert(mcp_res->flow);\n+\tMLX5_ASSERT(mcp_res->flow);\n \tflow_list_destroy(dev, NULL, mcp_res->flow);\n \tmlx5_hlist_remove(priv->mreg_cp_tbl, &mcp_res->hlist_ent);\n \trte_free(mcp_res);\n@@ -3128,7 +3129,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \n \tif (!mcp_res || !flow->copy_applied)\n \t\treturn;\n-\tassert(mcp_res->appcnt);\n+\tMLX5_ASSERT(mcp_res->appcnt);\n \t--mcp_res->appcnt;\n \tflow->copy_applied = 0;\n \tif (!mcp_res->appcnt)\n@@ -3154,7 +3155,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t\t    MLX5_DEFAULT_COPY_ID);\n \tif (!mcp_res)\n \t\treturn;\n-\tassert(mcp_res->flow);\n+\tMLX5_ASSERT(mcp_res->flow);\n \tflow_list_destroy(dev, NULL, mcp_res->flow);\n \tmlx5_hlist_remove(priv->mreg_cp_tbl, &mcp_res->hlist_ent);\n \trte_free(mcp_res);\n@@ -3383,7 +3384,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tactions_rx++;\n \tset_tag = (void *)actions_rx;\n \tset_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL);\n-\tassert(set_tag->id > REG_NONE);\n+\tMLX5_ASSERT(set_tag->id > REG_NONE);\n \tset_tag->data = *flow_id;\n \ttag_action->conf = set_tag;\n \t/* Create Tx item list. */\n@@ -3394,7 +3395,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \ttag_item = (void *)addr;\n \ttag_item->data = *flow_id;\n \ttag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL);\n-\tassert(set_tag->id > REG_NONE);\n+\tMLX5_ASSERT(set_tag->id > REG_NONE);\n \titem->spec = tag_item;\n \taddr += sizeof(struct mlx5_rte_flow_item_tag);\n \ttag_item = (void *)addr;\n@@ -3862,7 +3863,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t      external, error);\n \tif (ret < 0)\n \t\tgoto exit;\n-\tassert(dev_flow);\n+\tMLX5_ASSERT(dev_flow);\n \tif (qrss) {\n \t\tconst struct rte_flow_attr q_attr = {\n \t\t\t.group = MLX5_FLOW_MREG_ACT_TABLE_GROUP,\n@@ -3902,7 +3903,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t */\n \t\tif (qrss_id) {\n \t\t\t/* Not meter subflow. */\n-\t\t\tassert(!mtr_sfx);\n+\t\t\tMLX5_ASSERT(!mtr_sfx);\n \t\t\t/*\n \t\t\t * Put unique id in prefix flow due to it is destroyed\n \t\t\t * after suffix flow and id will be freed after there\n@@ -3926,7 +3927,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t\t      external, error);\n \t\tif (ret < 0)\n \t\t\tgoto exit;\n-\t\tassert(dev_flow);\n+\t\tMLX5_ASSERT(dev_flow);\n \t\tdev_flow->hash_fields = hash_fields;\n \t}\n \n@@ -4106,7 +4107,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \n \tret = flow_create_split_meter(dev, flow, attr, items,\n \t\t\t\t\t actions, external, error);\n-\tassert(ret <= 0);\n+\tMLX5_ASSERT(ret <= 0);\n \treturn ret;\n }\n \n@@ -4200,8 +4201,8 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tflow->drv_type = flow_get_drv_type(dev, attr);\n \tif (hairpin_id != 0)\n \t\tflow->hairpin_flow_id = hairpin_id;\n-\tassert(flow->drv_type > MLX5_FLOW_TYPE_MIN &&\n-\t       flow->drv_type < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN &&\n+\t\t    flow->drv_type < MLX5_FLOW_TYPE_MAX);\n \tflow->rss.queue = (void *)(flow + 1);\n \tif (rss) {\n \t\t/*\n@@ -4221,7 +4222,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t\t  items, rss->types,\n \t\t\t\t\t  mlx5_support_expansion,\n \t\t\t\t\t  graph_root);\n-\t\tassert(ret > 0 &&\n+\t\tMLX5_ASSERT(ret > 0 &&\n \t\t       (unsigned int)ret < sizeof(expand_buffer.buffer));\n \t} else {\n \t\tbuf->entries = 1;\n@@ -4289,13 +4290,13 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \t\t\t\t     hairpin_id);\n \treturn NULL;\n error:\n-\tassert(flow);\n+\tMLX5_ASSERT(flow);\n \tflow_mreg_del_copy_action(dev, flow);\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n \tif (flow->hairpin_flow_id)\n \t\tmlx5_flow_id_release(priv->sh->flow_id_pool,\n \t\t\t\t     flow->hairpin_flow_id);\n-\tassert(flow);\n+\tMLX5_ASSERT(flow);\n \tflow_drv_destroy(dev, flow);\n \trte_free(flow);\n \trte_errno = ret; /* Restore rte_errno. */\n@@ -4747,7 +4748,7 @@ struct rte_flow *\n \tconst struct mlx5_flow_driver_ops *fops;\n \tenum mlx5_flow_drv_type ftype = flow->drv_type;\n \n-\tassert(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX);\n+\tMLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX);\n \tfops = flow_get_drv_ops(ftype);\n \n \treturn fops->query(dev, flow, actions, data, error);\n@@ -5012,7 +5013,7 @@ struct rte_flow *\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct rte_flow *flow = NULL;\n \n-\tassert(fdir_flow);\n+\tMLX5_ASSERT(fdir_flow);\n \tTAILQ_FOREACH(flow, &priv->flows, next) {\n \t\tif (flow->fdir && !flow_fdir_cmp(flow->fdir, fdir_flow)) {\n \t\t\tDRV_LOG(DEBUG, \"port %u found FDIR flow %p\",\n@@ -5061,7 +5062,7 @@ struct rte_flow *\n \t\t\t\tNULL);\n \tif (!flow)\n \t\tgoto error;\n-\tassert(!flow->fdir);\n+\tMLX5_ASSERT(!flow->fdir);\n \tflow->fdir = fdir_flow;\n \tDRV_LOG(DEBUG, \"port %u created FDIR flow %p\",\n \t\tdev->data->port_id, (void *)flow);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 93e7c37..72959b5 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -198,8 +198,8 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t  uint8_t next_protocol, uint64_t *item_flags,\n \t\t\t  int *tunnel)\n {\n-\tassert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||\n-\t       item->type == RTE_FLOW_ITEM_TYPE_IPV6);\n+\tMLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||\n+\t\t    item->type == RTE_FLOW_ITEM_TYPE_IPV6);\n \tif (next_protocol == IPPROTO_IPIP) {\n \t\t*item_flags |= MLX5_FLOW_LAYER_IPIP;\n \t\t*tunnel = 1;\n@@ -229,7 +229,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tint ret;\n \n \t\tret = pthread_mutex_lock(&sh->dv_mutex);\n-\t\tassert(!ret);\n+\t\tMLX5_ASSERT(!ret);\n \t\t(void)ret;\n \t}\n }\n@@ -244,7 +244,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tint ret;\n \n \t\tret = pthread_mutex_unlock(&sh->dv_mutex);\n-\t\tassert(!ret);\n+\t\tMLX5_ASSERT(!ret);\n \t\t(void)ret;\n \t}\n }\n@@ -308,7 +308,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);\n \t\tbreak;\n \tdefault:\n-\t\tassert(false);\n+\t\tMLX5_ASSERT(false);\n \t\tret = 0;\n \t\tbreak;\n \t}\n@@ -358,8 +358,8 @@ struct field_modify_info modify_tcp[] = {\n \t * The fields should be presented as in big-endian format either.\n \t * Mask must be always present, it defines the actual field width.\n \t */\n-\tassert(item->mask);\n-\tassert(field->size);\n+\tMLX5_ASSERT(item->mask);\n+\tMLX5_ASSERT(field->size);\n \tdo {\n \t\tunsigned int size_b;\n \t\tunsigned int off_b;\n@@ -381,7 +381,7 @@ struct field_modify_info modify_tcp[] = {\n \t\toff_b = rte_bsf32(mask);\n \t\tsize_b = sizeof(uint32_t) * CHAR_BIT -\n \t\t\t off_b - __builtin_clz(mask);\n-\t\tassert(size_b);\n+\t\tMLX5_ASSERT(size_b);\n \t\tsize_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;\n \t\tactions[i].action_type = type;\n \t\tactions[i].field = field->id;\n@@ -390,14 +390,14 @@ struct field_modify_info modify_tcp[] = {\n \t\t/* Convert entire record to expected big-endian format. */\n \t\tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n \t\tif (type == MLX5_MODIFICATION_TYPE_COPY) {\n-\t\t\tassert(dcopy);\n+\t\t\tMLX5_ASSERT(dcopy);\n \t\t\tactions[i].dst_field = dcopy->id;\n \t\t\tactions[i].dst_offset =\n \t\t\t\t(int)dcopy->offset < 0 ? off_b : dcopy->offset;\n \t\t\t/* Convert entire record to big-endian format. */\n \t\t\tactions[i].data1 = rte_cpu_to_be_32(actions[i].data1);\n \t\t} else {\n-\t\t\tassert(item->spec);\n+\t\t\tMLX5_ASSERT(item->spec);\n \t\t\tdata = flow_dv_fetch_field((const uint8_t *)item->spec +\n \t\t\t\t\t\t   field->offset, field->size);\n \t\t\t/* Shift out the trailing masked bits from data. */\n@@ -909,8 +909,8 @@ struct field_modify_info modify_tcp[] = {\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t  RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n \t\t\t\t\t  \"too many items to modify\");\n-\tassert(conf->id != REG_NONE);\n-\tassert(conf->id < RTE_DIM(reg_to_field));\n+\tMLX5_ASSERT(conf->id != REG_NONE);\n+\tMLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));\n \tactions[i].action_type = MLX5_MODIFICATION_TYPE_SET;\n \tactions[i].field = reg_to_field[conf->id];\n \tactions[i].data0 = rte_cpu_to_be_32(actions[i].data0);\n@@ -957,10 +957,10 @@ struct field_modify_info modify_tcp[] = {\n \tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);\n \tif (ret < 0)\n \t\treturn ret;\n-\tassert(ret != REG_NONE);\n-\tassert((unsigned int)ret < RTE_DIM(reg_to_field));\n+\tMLX5_ASSERT(ret != REG_NONE);\n+\tMLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));\n \treg_type = reg_to_field[ret];\n-\tassert(reg_type > 0);\n+\tMLX5_ASSERT(reg_type > 0);\n \treg_c_x[0] = (struct field_modify_info){4, 0, reg_type};\n \treturn flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,\n \t\t\t\t\t     MLX5_MODIFICATION_TYPE_SET, error);\n@@ -1006,8 +1006,8 @@ struct field_modify_info modify_tcp[] = {\n \t\tstruct mlx5_priv *priv = dev->data->dev_private;\n \t\tuint32_t reg_c0 = priv->sh->dv_regc0_mask;\n \n-\t\tassert(reg_c0);\n-\t\tassert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);\n+\t\tMLX5_ASSERT(reg_c0);\n+\t\tMLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);\n \t\tif (conf->dst == REG_C_0) {\n \t\t\t/* Copy to reg_c[0], within mask only. */\n \t\t\treg_dst.offset = rte_bsf32(reg_c0);\n@@ -1086,7 +1086,7 @@ struct field_modify_info modify_tcp[] = {\n \treg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);\n \tif (reg < 0)\n \t\treturn reg;\n-\tassert(reg > 0);\n+\tMLX5_ASSERT(reg > 0);\n \tif (reg == REG_C_0) {\n \t\tuint32_t msk_c0 = priv->sh->dv_regc0_mask;\n \t\tuint32_t shl_c0 = rte_bsf32(msk_c0);\n@@ -1181,7 +1181,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tuint32_t msk_c0 = priv->sh->dv_regc0_mask;\n \t\tuint32_t shl_c0;\n \n-\t\tassert(msk_c0);\n+\t\tMLX5_ASSERT(msk_c0);\n #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n \t\tshl_c0 = rte_bsf32(msk_c0);\n #else\n@@ -1189,7 +1189,7 @@ struct field_modify_info modify_tcp[] = {\n #endif\n \t\tmask <<= shl_c0;\n \t\tdata <<= shl_c0;\n-\t\tassert(!(~msk_c0 & rte_cpu_to_be_32(mask)));\n+\t\tMLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));\n \t}\n \treg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};\n \t/* The routine expects parameters in memory as big-endian ones. */\n@@ -1463,7 +1463,7 @@ struct field_modify_info modify_tcp[] = {\n \tret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);\n \tif (ret < 0)\n \t\treturn ret;\n-\tassert(ret != REG_NONE);\n+\tMLX5_ASSERT(ret != REG_NONE);\n \treturn 0;\n }\n \n@@ -1920,7 +1920,7 @@ struct field_modify_info modify_tcp[] = {\n \tret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);\n \tif (ret < 0)\n \t\treturn ret;\n-\tassert(ret > 0);\n+\tMLX5_ASSERT(ret > 0);\n \tif (action_flags & MLX5_FLOW_ACTION_DROP)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t  RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n@@ -1984,7 +1984,7 @@ struct field_modify_info modify_tcp[] = {\n \tret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);\n \tif (ret < 0)\n \t\treturn ret;\n-\tassert(ret > 0);\n+\tMLX5_ASSERT(ret > 0);\n \tif (!mark)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t  RTE_FLOW_ERROR_TYPE_ACTION, action,\n@@ -2453,7 +2453,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tcontainer_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);\n \tint cnt;\n \n-\tassert(tbl);\n+\tMLX5_ASSERT(tbl);\n \tcnt = rte_atomic32_read(&tbl_data->jump.refcnt);\n \tif (!cnt) {\n \t\ttbl_data->jump.action =\n@@ -2466,7 +2466,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tDRV_LOG(DEBUG, \"new jump table resource %p: refcnt %d++\",\n \t\t\t(void *)&tbl_data->jump, cnt);\n \t} else {\n-\t\tassert(tbl_data->jump.action);\n+\t\tMLX5_ASSERT(tbl_data->jump.action);\n \t\tDRV_LOG(DEBUG, \"existed jump table resource %p: refcnt %d++\",\n \t\t\t(void *)&tbl_data->jump, cnt);\n \t}\n@@ -6044,7 +6044,7 @@ struct field_modify_info modify_tcp[] = {\n \t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);\n \t\tbreak;\n \tdefault:\n-\t\tassert(false);\n+\t\tMLX5_ASSERT(false);\n \t\tbreak;\n \t}\n }\n@@ -6075,14 +6075,14 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t    &rte_flow_item_mark_mask;\n \tmask = mark->id & priv->sh->dv_mark_mask;\n \tmark = (const void *)item->spec;\n-\tassert(mark);\n+\tMLX5_ASSERT(mark);\n \tvalue = mark->id & priv->sh->dv_mark_mask & mask;\n \tif (mask) {\n \t\tenum modify_reg reg;\n \n \t\t/* Get the metadata register index for the mark. */\n \t\treg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);\n-\t\tassert(reg > 0);\n+\t\tMLX5_ASSERT(reg > 0);\n \t\tif (reg == REG_C_0) {\n \t\t\tstruct mlx5_priv *priv = dev->data->dev_private;\n \t\t\tuint32_t msk_c0 = priv->sh->dv_regc0_mask;\n@@ -6150,8 +6150,8 @@ struct field_modify_info modify_tcp[] = {\n #endif\n \t\t\tvalue <<= shl_c0;\n \t\t\tmask <<= shl_c0;\n-\t\t\tassert(msk_c0);\n-\t\t\tassert(!(~msk_c0 & mask));\n+\t\t\tMLX5_ASSERT(msk_c0);\n+\t\t\tMLX5_ASSERT(!(~msk_c0 & mask));\n \t\t}\n \t\tflow_dv_match_meta_reg(matcher, key, reg, value, mask);\n \t}\n@@ -6195,7 +6195,7 @@ struct field_modify_info modify_tcp[] = {\n \tconst struct mlx5_rte_flow_item_tag *tag_m = item->mask;\n \tuint32_t mask, value;\n \n-\tassert(tag_v);\n+\tMLX5_ASSERT(tag_v);\n \tvalue = tag_v->data;\n \tmask = tag_m ? tag_m->data : UINT32_MAX;\n \tif (tag_v->id == REG_C_0) {\n@@ -6231,11 +6231,11 @@ struct field_modify_info modify_tcp[] = {\n \tconst struct rte_flow_item_tag *tag_m = item->mask;\n \tenum modify_reg reg;\n \n-\tassert(tag_v);\n+\tMLX5_ASSERT(tag_v);\n \ttag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;\n \t/* Get the metadata register index for the tag. */\n \treg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);\n-\tassert(reg > 0);\n+\tMLX5_ASSERT(reg > 0);\n \tflow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);\n }\n \n@@ -6802,7 +6802,7 @@ struct field_modify_info modify_tcp[] = {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_ibv_shared *sh = priv->sh;\n \n-\tassert(tag);\n+\tMLX5_ASSERT(tag);\n \tDRV_LOG(DEBUG, \"port %u tag %p: refcnt %d--\",\n \t\tdev->data->port_id, (void *)tag,\n \t\trte_atomic32_read(&tag->refcnt));\n@@ -7152,14 +7152,14 @@ struct field_modify_info modify_tcp[] = {\n \t\t\taction_flags |= MLX5_FLOW_ACTION_DROP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n-\t\t\tassert(flow->rss.queue);\n+\t\t\tMLX5_ASSERT(flow->rss.queue);\n \t\t\tqueue = actions->conf;\n \t\t\tflow->rss.queue_num = 1;\n \t\t\t(*flow->rss.queue)[0] = queue->index;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_QUEUE;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n-\t\t\tassert(flow->rss.queue);\n+\t\t\tMLX5_ASSERT(flow->rss.queue);\n \t\t\trss = actions->conf;\n \t\t\tif (flow->rss.queue)\n \t\t\t\tmemcpy((*flow->rss.queue), rss->queue,\n@@ -7233,7 +7233,8 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:\n \t\t\t/* of_vlan_push action handled this action */\n-\t\t\tassert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);\n+\t\t\tMLX5_ASSERT(action_flags &\n+\t\t\t\t    MLX5_FLOW_ACTION_OF_PUSH_VLAN);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:\n \t\t\tif (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)\n@@ -7657,8 +7658,10 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\t\t\t   match_value, NULL))\n \t\t\treturn -rte_errno;\n \t}\n-\tassert(!flow_dv_check_valid_spec(matcher.mask.buf,\n-\t\t\t\t\t dev_flow->dv.value.buf));\n+#ifdef MLX5_DEBUG\n+\tMLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,\n+\t\t\t\t\t      dev_flow->dv.value.buf));\n+#endif\n \tdev_flow->layers = item_flags;\n \tif (action_flags & MLX5_FLOW_ACTION_RSS)\n \t\tflow_dv_hashfields_set(dev_flow);\n@@ -7722,7 +7725,7 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t   (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {\n \t\t\tstruct mlx5_hrxq *hrxq;\n \n-\t\t\tassert(flow->rss.queue);\n+\t\t\tMLX5_ASSERT(flow->rss.queue);\n \t\t\thrxq = mlx5_hrxq_get(dev, flow->rss.key,\n \t\t\t\t\t     MLX5_RSS_HASH_KEY_LEN,\n \t\t\t\t\t     dev_flow->hash_fields,\n@@ -7808,7 +7811,7 @@ struct field_modify_info modify_tcp[] = {\n {\n \tstruct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;\n \n-\tassert(matcher->matcher_object);\n+\tMLX5_ASSERT(matcher->matcher_object);\n \tDRV_LOG(DEBUG, \"port %u matcher %p: refcnt %d--\",\n \t\tdev->data->port_id, (void *)matcher,\n \t\trte_atomic32_read(&matcher->refcnt));\n@@ -7841,7 +7844,7 @@ struct field_modify_info modify_tcp[] = {\n \tstruct mlx5_flow_dv_encap_decap_resource *cache_resource =\n \t\t\t\t\t\tflow->dv.encap_decap;\n \n-\tassert(cache_resource->verbs_action);\n+\tMLX5_ASSERT(cache_resource->verbs_action);\n \tDRV_LOG(DEBUG, \"encap/decap resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n \t\trte_atomic32_read(&cache_resource->refcnt));\n@@ -7877,7 +7880,7 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tcontainer_of(cache_resource,\n \t\t\t\t     struct mlx5_flow_tbl_data_entry, jump);\n \n-\tassert(cache_resource->action);\n+\tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"jump table resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n \t\trte_atomic32_read(&cache_resource->refcnt));\n@@ -7908,7 +7911,7 @@ struct field_modify_info modify_tcp[] = {\n \tstruct mlx5_flow_dv_modify_hdr_resource *cache_resource =\n \t\t\t\t\t\tflow->dv.modify_hdr;\n \n-\tassert(cache_resource->verbs_action);\n+\tMLX5_ASSERT(cache_resource->verbs_action);\n \tDRV_LOG(DEBUG, \"modify-header resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n \t\trte_atomic32_read(&cache_resource->refcnt));\n@@ -7939,7 +7942,7 @@ struct field_modify_info modify_tcp[] = {\n \tstruct mlx5_flow_dv_port_id_action_resource *cache_resource =\n \t\tflow->dv.port_id_action;\n \n-\tassert(cache_resource->action);\n+\tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"port ID action resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n \t\trte_atomic32_read(&cache_resource->refcnt));\n@@ -7970,7 +7973,7 @@ struct field_modify_info modify_tcp[] = {\n \tstruct mlx5_flow_dv_push_vlan_action_resource *cache_resource =\n \t\tflow->dv.push_vlan_res;\n \n-\tassert(cache_resource->action);\n+\tMLX5_ASSERT(cache_resource->action);\n \tDRV_LOG(DEBUG, \"push VLAN action resource %p: refcnt %d--\",\n \t\t(void *)cache_resource,\n \t\trte_atomic32_read(&cache_resource->refcnt));\ndiff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c\nindex c4d28b2..04dc46a 100644\n--- a/drivers/net/mlx5/mlx5_flow_meter.c\n+++ b/drivers/net/mlx5/mlx5_flow_meter.c\n@@ -732,7 +732,7 @@\n \t\t\t\t\t  NULL, \"Meter object is being used.\");\n \t/* Get the meter profile. */\n \tfmp = fm->profile;\n-\tRTE_ASSERT(fmp);\n+\tMLX5_ASSERT(fmp);\n \t/* Update dependencies. */\n \tfmp->ref_cnt--;\n \t/* Remove from the flow meter list. */\n@@ -1177,7 +1177,7 @@ struct mlx5_flow_meter *\n \t\tgoto error;\n \t}\n \tif (!fm->ref_cnt++) {\n-\t\tRTE_ASSERT(!fm->mfts->meter_action);\n+\t\tMLX5_ASSERT(!fm->mfts->meter_action);\n \t\tfm->attr = *attr;\n \t\t/* This also creates the meter object. */\n \t\tfm->mfts->meter_action = mlx5_flow_meter_action_create(priv,\n@@ -1185,7 +1185,7 @@ struct mlx5_flow_meter *\n \t\tif (!fm->mfts->meter_action)\n \t\t\tgoto error_detach;\n \t} else {\n-\t\tRTE_ASSERT(fm->mfts->meter_action);\n+\t\tMLX5_ASSERT(fm->mfts->meter_action);\n \t\tif (attr->transfer != fm->attr.transfer ||\n \t\t    attr->ingress != fm->attr.ingress ||\n \t\t    attr->egress != fm->attr.egress) {\n@@ -1215,7 +1215,7 @@ struct mlx5_flow_meter *\n {\n \tconst struct rte_flow_attr attr = { 0 };\n \n-\tRTE_ASSERT(fm->ref_cnt);\n+\tMLX5_ASSERT(fm->ref_cnt);\n \tif (--fm->ref_cnt)\n \t\treturn;\n \tif (fm->mfts->meter_action)\n@@ -1253,7 +1253,7 @@ struct mlx5_flow_meter *\n \n \tTAILQ_FOREACH_SAFE(fm, fms, next, tmp) {\n \t\t/* Meter object must not have any owner. */\n-\t\tRTE_ASSERT(!fm->ref_cnt);\n+\t\tMLX5_ASSERT(!fm->ref_cnt);\n \t\t/* Get meter profile. */\n \t\tfmp = fm->profile;\n \t\tif (fmp == NULL)\n@@ -1276,7 +1276,7 @@ struct mlx5_flow_meter *\n \t}\n \tTAILQ_FOREACH_SAFE(fmp, fmps, next, tmp) {\n \t\t/* Check unused. */\n-\t\tRTE_ASSERT(!fmp->ref_cnt);\n+\t\tMLX5_ASSERT(!fmp->ref_cnt);\n \t\t/* Remove from list. */\n \t\tTAILQ_REMOVE(&priv->flow_meter_profiles, fmp, next);\n \t\trte_free(fmp);\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex c787c98..5fbedbf 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -258,7 +258,7 @@\n \n \tif (!verbs)\n \t\treturn;\n-\tassert(verbs->specs);\n+\tMLX5_ASSERT(verbs->specs);\n \tdst = (void *)(verbs->specs + verbs->size);\n \tmemcpy(dst, src, size);\n \t++verbs->attr->num_of_specs;\n@@ -1696,7 +1696,7 @@\n \t\t} else {\n \t\t\tstruct mlx5_hrxq *hrxq;\n \n-\t\t\tassert(flow->rss.queue);\n+\t\t\tMLX5_ASSERT(flow->rss.queue);\n \t\t\thrxq = mlx5_hrxq_get(dev, flow->rss.key,\n \t\t\t\t\t     MLX5_RSS_HASH_KEY_LEN,\n \t\t\t\t\t     dev_flow->hash_fields,\ndiff --git a/drivers/net/mlx5/mlx5_mac.c b/drivers/net/mlx5/mlx5_mac.c\nindex 7bdaa2a..de12b7f 100644\n--- a/drivers/net/mlx5/mlx5_mac.c\n+++ b/drivers/net/mlx5/mlx5_mac.c\n@@ -4,7 +4,6 @@\n  */\n \n #include <stddef.h>\n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <inttypes.h>\n@@ -70,7 +69,7 @@\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst int vf = priv->config.vf;\n \n-\tassert(index < MLX5_MAX_MAC_ADDRESSES);\n+\tMLX5_ASSERT(index < MLX5_MAX_MAC_ADDRESSES);\n \tif (rte_is_zero_ether_addr(&dev->data->mac_addrs[index]))\n \t\treturn;\n \tif (vf)\n@@ -100,7 +99,7 @@\n \tconst int vf = priv->config.vf;\n \tunsigned int i;\n \n-\tassert(index < MLX5_MAX_MAC_ADDRESSES);\n+\tMLX5_ASSERT(index < MLX5_MAX_MAC_ADDRESSES);\n \tif (rte_is_zero_ether_addr(mac)) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\ndiff --git a/drivers/net/mlx5/mlx5_mp.c b/drivers/net/mlx5/mlx5_mp.c\nindex 2a031e2..55d408f 100644\n--- a/drivers/net/mlx5/mlx5_mp.c\n+++ b/drivers/net/mlx5/mlx5_mp.c\n@@ -3,7 +3,6 @@\n  * Copyright 2019 Mellanox Technologies, Ltd\n  */\n \n-#include <assert.h>\n #include <stdio.h>\n #include <time.h>\n \n@@ -62,7 +61,7 @@\n \tuint32_t lkey;\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tif (!rte_eth_dev_is_valid_port(param->port_id)) {\n \t\trte_errno = ENODEV;\n \t\tDRV_LOG(ERR, \"port %u invalid port ID\", param->port_id);\n@@ -121,7 +120,7 @@\n \tstruct rte_eth_dev *dev;\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \tif (!rte_eth_dev_is_valid_port(param->port_id)) {\n \t\trte_errno = ENODEV;\n \t\tDRV_LOG(ERR, \"port %u invalid port ID\", param->port_id);\n@@ -175,7 +174,7 @@\n \tint ret;\n \tint i;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tif (!mlx5_shared_data->secondary_cnt)\n \t\treturn;\n \tif (type != MLX5_MP_REQ_START_RXTX && type != MLX5_MP_REQ_STOP_RXTX) {\n@@ -258,7 +257,7 @@\n \tstruct timespec ts = {.tv_sec = MLX5_MP_REQ_TIMEOUT_SEC, .tv_nsec = 0};\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \tmp_init_msg(dev, &mp_req, MLX5_MP_REQ_CREATE_MR);\n \treq->args.addr = addr;\n \tret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);\n@@ -267,7 +266,7 @@\n \t\t\tdev->data->port_id);\n \t\treturn -rte_errno;\n \t}\n-\tassert(mp_rep.nb_received == 1);\n+\tMLX5_ASSERT(mp_rep.nb_received == 1);\n \tmp_res = &mp_rep.msgs[0];\n \tres = (struct mlx5_mp_param *)mp_res->param;\n \tret = res->result;\n@@ -300,7 +299,7 @@\n \tstruct timespec ts = {.tv_sec = MLX5_MP_REQ_TIMEOUT_SEC, .tv_nsec = 0};\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \tmp_init_msg(dev, &mp_req, MLX5_MP_REQ_QUEUE_STATE_MODIFY);\n \treq->args.state_modify = *sm;\n \tret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);\n@@ -309,7 +308,7 @@\n \t\t\tdev->data->port_id);\n \t\treturn -rte_errno;\n \t}\n-\tassert(mp_rep.nb_received == 1);\n+\tMLX5_ASSERT(mp_rep.nb_received == 1);\n \tmp_res = &mp_rep.msgs[0];\n \tres = (struct mlx5_mp_param *)mp_res->param;\n \tret = res->result;\n@@ -336,7 +335,7 @@\n \tstruct timespec ts = {.tv_sec = MLX5_MP_REQ_TIMEOUT_SEC, .tv_nsec = 0};\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \tmp_init_msg(dev, &mp_req, MLX5_MP_REQ_VERBS_CMD_FD);\n \tret = rte_mp_request_sync(&mp_req, &mp_rep, &ts);\n \tif (ret) {\n@@ -344,7 +343,7 @@\n \t\t\tdev->data->port_id);\n \t\treturn -rte_errno;\n \t}\n-\tassert(mp_rep.nb_received == 1);\n+\tMLX5_ASSERT(mp_rep.nb_received == 1);\n \tmp_res = &mp_rep.msgs[0];\n \tres = (struct mlx5_mp_param *)mp_res->param;\n \tif (res->result) {\n@@ -355,7 +354,7 @@\n \t\tret = -rte_errno;\n \t\tgoto exit;\n \t}\n-\tassert(mp_res->num_fds == 1);\n+\tMLX5_ASSERT(mp_res->num_fds == 1);\n \tret = mp_res->fds[0];\n \tDRV_LOG(DEBUG, \"port %u command FD from primary is %d\",\n \t\tdev->data->port_id, ret);\n@@ -372,7 +371,7 @@\n {\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \n \t/* primary is allowed to not support IPC */\n \tret = rte_mp_action_register(MLX5_MP_NAME, mp_primary_handle);\n@@ -387,7 +386,7 @@\n void\n mlx5_mp_uninit_primary(void)\n {\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \trte_mp_action_unregister(MLX5_MP_NAME);\n }\n \n@@ -397,7 +396,7 @@\n int\n mlx5_mp_init_secondary(void)\n {\n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \treturn rte_mp_action_register(MLX5_MP_NAME, mp_secondary_handle);\n }\n \n@@ -407,6 +406,6 @@\n void\n mlx5_mp_uninit_secondary(void)\n {\n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \trte_mp_action_unregister(MLX5_MP_NAME);\n }\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex e423947..119764d 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -98,12 +98,12 @@ struct mr_update_mp_data {\n \tuint16_t n;\n \tuint16_t base = 0;\n \n-\tassert(bt != NULL);\n+\tMLX5_ASSERT(bt != NULL);\n \tlkp_tbl = *bt->table;\n \tn = bt->len;\n \t/* First entry must be NULL for comparison. */\n-\tassert(bt->len > 0 || (lkp_tbl[0].start == 0 &&\n-\t\t\t       lkp_tbl[0].lkey == UINT32_MAX));\n+\tMLX5_ASSERT(bt->len > 0 || (lkp_tbl[0].start == 0 &&\n+\t\t\t\t    lkp_tbl[0].lkey == UINT32_MAX));\n \t/* Binary search. */\n \tdo {\n \t\tregister uint16_t delta = n >> 1;\n@@ -115,7 +115,7 @@ struct mr_update_mp_data {\n \t\t\tn -= delta;\n \t\t}\n \t} while (n > 1);\n-\tassert(addr >= lkp_tbl[base].start);\n+\tMLX5_ASSERT(addr >= lkp_tbl[base].start);\n \t*idx = base;\n \tif (addr < lkp_tbl[base].end)\n \t\treturn lkp_tbl[base].lkey;\n@@ -141,9 +141,9 @@ struct mr_update_mp_data {\n \tuint16_t idx = 0;\n \tsize_t shift;\n \n-\tassert(bt != NULL);\n-\tassert(bt->len <= bt->size);\n-\tassert(bt->len > 0);\n+\tMLX5_ASSERT(bt != NULL);\n+\tMLX5_ASSERT(bt->len <= bt->size);\n+\tMLX5_ASSERT(bt->len > 0);\n \tlkp_tbl = *bt->table;\n \t/* Find out the slot for insertion. */\n \tif (mr_btree_lookup(bt, &idx, entry->start) != UINT32_MAX) {\n@@ -193,7 +193,7 @@ struct mr_update_mp_data {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\tassert(!bt->table && !bt->size);\n+\tMLX5_ASSERT(!bt->table && !bt->size);\n \tmemset(bt, 0, sizeof(*bt));\n \tbt->table = rte_calloc_socket(\"B-tree table\",\n \t\t\t\t      n, sizeof(struct mlx5_mr_cache),\n@@ -283,9 +283,9 @@ struct mr_update_mp_data {\n \tif (mr->msl == NULL) {\n \t\tstruct ibv_mr *ibv_mr = mr->ibv_mr;\n \n-\t\tassert(mr->ms_bmp_n == 1);\n-\t\tassert(mr->ms_n == 1);\n-\t\tassert(base_idx == 0);\n+\t\tMLX5_ASSERT(mr->ms_bmp_n == 1);\n+\t\tMLX5_ASSERT(mr->ms_n == 1);\n+\t\tMLX5_ASSERT(base_idx == 0);\n \t\t/*\n \t\t * Can't search it from memseg list but get it directly from\n \t\t * verbs MR as there's only one chunk.\n@@ -304,7 +304,7 @@ struct mr_update_mp_data {\n \t\t\tmsl = mr->msl;\n \t\t\tms = rte_fbarray_get(&msl->memseg_arr,\n \t\t\t\t\t     mr->ms_base_idx + idx);\n-\t\t\tassert(msl->page_sz == ms->hugepage_sz);\n+\t\t\tMLX5_ASSERT(msl->page_sz == ms->hugepage_sz);\n \t\t\tif (!start)\n \t\t\t\tstart = ms->addr_64;\n \t\t\tend = ms->addr_64 + ms->hugepage_sz;\n@@ -438,8 +438,8 @@ struct mr_update_mp_data {\n \t\tif (mr != NULL)\n \t\t\tlkey = entry->lkey;\n \t}\n-\tassert(lkey == UINT32_MAX || (addr >= entry->start &&\n-\t\t\t\t      addr < entry->end));\n+\tMLX5_ASSERT(lkey == UINT32_MAX || (addr >= entry->start &&\n+\t\t\t\t\t   addr < entry->end));\n \treturn lkey;\n }\n \n@@ -476,7 +476,7 @@ struct mr_update_mp_data {\n \tstruct mlx5_mr_list free_list = LIST_HEAD_INITIALIZER(free_list);\n \n \t/* Must be called from the primary process. */\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \t/*\n \t * MR can't be freed with holding the lock because rte_free() could call\n \t * memory free callback function. This will be a deadlock situation.\n@@ -549,7 +549,7 @@ struct mr_update_mp_data {\n \t/* Fill in output data. */\n \tmr_lookup_dev(priv->sh, entry, addr);\n \t/* Lookup can't fail. */\n-\tassert(entry->lkey != UINT32_MAX);\n+\tMLX5_ASSERT(entry->lkey != UINT32_MAX);\n \trte_rwlock_read_unlock(&priv->sh->mr.rwlock);\n \tDEBUG(\"port %u MR CREATED by primary process for %p:\\n\"\n \t      \"  [0x%\" PRIxPTR \", 0x%\" PRIxPTR \"), lkey=0x%x\",\n@@ -634,12 +634,12 @@ struct mr_update_mp_data {\n \t}\n alloc_resources:\n \t/* Addresses must be page-aligned. */\n-\tassert(rte_is_aligned((void *)data.start, data.msl->page_sz));\n-\tassert(rte_is_aligned((void *)data.end, data.msl->page_sz));\n+\tMLX5_ASSERT(rte_is_aligned((void *)data.start, data.msl->page_sz));\n+\tMLX5_ASSERT(rte_is_aligned((void *)data.end, data.msl->page_sz));\n \tmsl = data.msl;\n \tms = rte_mem_virt2memseg((void *)data.start, msl);\n \tlen = data.end - data.start;\n-\tassert(msl->page_sz == ms->hugepage_sz);\n+\tMLX5_ASSERT(msl->page_sz == ms->hugepage_sz);\n \t/* Number of memsegs in the range. */\n \tms_n = len / msl->page_sz;\n \tDEBUG(\"port %u extending %p to [0x%\" PRIxPTR \", 0x%\" PRIxPTR \"),\"\n@@ -706,7 +706,7 @@ struct mr_update_mp_data {\n \t\tmr_free(mr);\n \t\tgoto alloc_resources;\n \t}\n-\tassert(data.msl == data_re.msl);\n+\tMLX5_ASSERT(data.msl == data_re.msl);\n \trte_rwlock_write_lock(&sh->mr.rwlock);\n \t/*\n \t * Check the address is really missing. If other thread already created\n@@ -759,7 +759,7 @@ struct mr_update_mp_data {\n \t}\n \tlen = data.end - data.start;\n \tmr->ms_bmp_n = len / msl->page_sz;\n-\tassert(ms_idx_shift + mr->ms_bmp_n <= ms_n);\n+\tMLX5_ASSERT(ms_idx_shift + mr->ms_bmp_n <= ms_n);\n \t/*\n \t * Finally create a verbs MR for the memory chunk. ibv_reg_mr() can be\n \t * called with holding the memory lock because it doesn't use\n@@ -774,8 +774,8 @@ struct mr_update_mp_data {\n \t\trte_errno = EINVAL;\n \t\tgoto err_mrlock;\n \t}\n-\tassert((uintptr_t)mr->ibv_mr->addr == data.start);\n-\tassert(mr->ibv_mr->length == len);\n+\tMLX5_ASSERT((uintptr_t)mr->ibv_mr->addr == data.start);\n+\tMLX5_ASSERT(mr->ibv_mr->length == len);\n \tLIST_INSERT_HEAD(&sh->mr.mr_list, mr, mr);\n \tDEBUG(\"port %u MR CREATED (%p) for %p:\\n\"\n \t      \"  [0x%\" PRIxPTR \", 0x%\" PRIxPTR \"),\"\n@@ -788,7 +788,7 @@ struct mr_update_mp_data {\n \t/* Fill in output data. */\n \tmr_lookup_dev(sh, entry, addr);\n \t/* Lookup can't fail. */\n-\tassert(entry->lkey != UINT32_MAX);\n+\tMLX5_ASSERT(entry->lkey != UINT32_MAX);\n \trte_rwlock_write_unlock(&sh->mr.rwlock);\n \trte_mcfg_mem_read_unlock();\n \treturn entry->lkey;\n@@ -894,8 +894,9 @@ struct mr_update_mp_data {\n \t      sh->ibdev_name, addr, len);\n \tmsl = rte_mem_virt2memseg_list(addr);\n \t/* addr and len must be page-aligned. */\n-\tassert((uintptr_t)addr == RTE_ALIGN((uintptr_t)addr, msl->page_sz));\n-\tassert(len == RTE_ALIGN(len, msl->page_sz));\n+\tMLX5_ASSERT((uintptr_t)addr ==\n+\t\t    RTE_ALIGN((uintptr_t)addr, msl->page_sz));\n+\tMLX5_ASSERT(len == RTE_ALIGN(len, msl->page_sz));\n \tms_n = len / msl->page_sz;\n \trte_rwlock_write_lock(&sh->mr.rwlock);\n \t/* Clear bits of freed memsegs from MR. */\n@@ -911,14 +912,14 @@ struct mr_update_mp_data {\n \t\tmr = mr_lookup_dev_list(sh, &entry, start);\n \t\tif (mr == NULL)\n \t\t\tcontinue;\n-\t\tassert(mr->msl); /* Can't be external memory. */\n+\t\tMLX5_ASSERT(mr->msl); /* Can't be external memory. */\n \t\tms = rte_mem_virt2memseg((void *)start, msl);\n-\t\tassert(ms != NULL);\n-\t\tassert(msl->page_sz == ms->hugepage_sz);\n+\t\tMLX5_ASSERT(ms != NULL);\n+\t\tMLX5_ASSERT(msl->page_sz == ms->hugepage_sz);\n \t\tms_idx = rte_fbarray_find_idx(&msl->memseg_arr, ms);\n \t\tpos = ms_idx - mr->ms_base_idx;\n-\t\tassert(rte_bitmap_get(mr->ms_bmp, pos));\n-\t\tassert(pos < mr->ms_bmp_n);\n+\t\tMLX5_ASSERT(rte_bitmap_get(mr->ms_bmp, pos));\n+\t\tMLX5_ASSERT(pos < mr->ms_bmp_n);\n \t\tDEBUG(\"device %s MR(%p): clear bitmap[%u] for addr %p\",\n \t\t      sh->ibdev_name, (void *)mr, pos, (void *)start);\n \t\trte_bitmap_clear(mr->ms_bmp, pos);\n@@ -972,7 +973,7 @@ struct mr_update_mp_data {\n \tstruct mlx5_dev_list *dev_list = &mlx5_shared_data->mem_event_cb_list;\n \n \t/* Must be called from the primary process. */\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tswitch (event_type) {\n \tcase RTE_MEM_EVENT_FREE:\n \t\trte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);\n@@ -1266,7 +1267,7 @@ struct mr_update_mp_data {\n \tstruct mlx5_mr_cache entry;\n \tuint32_t lkey;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \t/* If already registered, it should return. */\n \trte_rwlock_read_lock(&sh->mr.rwlock);\n \tlkey = mr_lookup_dev(sh, &entry, addr);\ndiff --git a/drivers/net/mlx5/mlx5_nl.c b/drivers/net/mlx5/mlx5_nl.c\nindex 2e6d29c..95a56e0 100644\n--- a/drivers/net/mlx5/mlx5_nl.c\n+++ b/drivers/net/mlx5/mlx5_nl.c\n@@ -610,8 +610,10 @@ struct mlx5_nl_ifindex_data {\n \tint ret;\n \n \tret = mlx5_nl_mac_addr_modify(dev, mac, 1);\n-\tif (!ret)\n+\tif (!ret) {\n+\t\tMLX5_ASSERT((size_t)(index) < sizeof(priv->mac_own) * CHAR_BIT);\n \t\tBITFIELD_SET(priv->mac_own, index);\n+\t}\n \tif (ret == -EEXIST)\n \t\treturn 0;\n \treturn ret;\n@@ -636,6 +638,7 @@ struct mlx5_nl_ifindex_data {\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n+\tMLX5_ASSERT((size_t)(index) < sizeof(priv->mac_own) * CHAR_BIT);\n \tBITFIELD_RESET(priv->mac_own, index);\n \treturn mlx5_nl_mac_addr_modify(dev, mac, 0);\n }\n@@ -692,6 +695,7 @@ struct mlx5_nl_ifindex_data {\n \tfor (i = MLX5_MAX_MAC_ADDRESSES - 1; i >= 0; --i) {\n \t\tstruct rte_ether_addr *m = &dev->data->mac_addrs[i];\n \n+\t\tMLX5_ASSERT((size_t)(i) < sizeof(priv->mac_own) * CHAR_BIT);\n \t\tif (BITFIELD_ISSET(priv->mac_own, i))\n \t\t\tmlx5_nl_mac_addr_remove(dev, m, i);\n \t}\n@@ -733,7 +737,7 @@ struct mlx5_nl_ifindex_data {\n \tint fd;\n \tint ret;\n \n-\tassert(!(flags & ~(IFF_PROMISC | IFF_ALLMULTI)));\n+\tMLX5_ASSERT(!(flags & ~(IFF_PROMISC | IFF_ALLMULTI)));\n \tif (priv->nl_socket_route < 0)\n \t\treturn 0;\n \tfd = priv->nl_socket_route;\n@@ -1050,7 +1054,7 @@ struct mlx5_nl_ifindex_data {\n \t\t/* We have some E-Switch configuration. */\n \t\tmlx5_nl_check_switch_info(num_vf_set, &info);\n \t}\n-\tassert(!(info.master && info.representor));\n+\tMLX5_ASSERT(!(info.master && info.representor));\n \tmemcpy(arg, &info, sizeof(info));\n \treturn 0;\n error:\n@@ -1250,7 +1254,7 @@ struct mlx5_nl_ifindex_data {\n \tnl_attr_put(nlh, IFLA_VLAN_ID, &tag, sizeof(tag));\n \tnl_attr_nest_end(nlh, na_vlan);\n \tnl_attr_nest_end(nlh, na_info);\n-\tassert(sizeof(buf) >= nlh->nlmsg_len);\n+\tMLX5_ASSERT(sizeof(buf) >= nlh->nlmsg_len);\n \tret = mlx5_nl_send(vmwa->nl_socket, nlh, vmwa->nl_sn);\n \tif (ret >= 0)\n \t\tret = mlx5_nl_recv(vmwa->nl_socket, vmwa->nl_sn, NULL, NULL);\n@@ -1285,12 +1289,12 @@ void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,\n \tstruct mlx5_vlan_vmwa_context *vmwa = priv->vmwa_context;\n \tstruct mlx5_vlan_dev *vlan_dev = &vmwa->vlan_dev[0];\n \n-\tassert(vlan->created);\n-\tassert(priv->vmwa_context);\n+\tMLX5_ASSERT(vlan->created);\n+\tMLX5_ASSERT(priv->vmwa_context);\n \tif (!vlan->created || !vmwa)\n \t\treturn;\n \tvlan->created = 0;\n-\tassert(vlan_dev[vlan->tag].refcnt);\n+\tMLX5_ASSERT(vlan_dev[vlan->tag].refcnt);\n \tif (--vlan_dev[vlan->tag].refcnt == 0 &&\n \t    vlan_dev[vlan->tag].ifindex) {\n \t\tmlx5_vlan_vmwa_delete(vmwa, vlan_dev[vlan->tag].ifindex);\n@@ -1313,12 +1317,12 @@ void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,\n \tstruct mlx5_vlan_vmwa_context *vmwa = priv->vmwa_context;\n \tstruct mlx5_vlan_dev *vlan_dev = &vmwa->vlan_dev[0];\n \n-\tassert(!vlan->created);\n-\tassert(priv->vmwa_context);\n+\tMLX5_ASSERT(!vlan->created);\n+\tMLX5_ASSERT(priv->vmwa_context);\n \tif (vlan->created || !vmwa)\n \t\treturn;\n \tif (vlan_dev[vlan->tag].refcnt == 0) {\n-\t\tassert(!vlan_dev[vlan->tag].ifindex);\n+\t\tMLX5_ASSERT(!vlan_dev[vlan->tag].ifindex);\n \t\tvlan_dev[vlan->tag].ifindex =\n \t\t\tmlx5_vlan_vmwa_create(vmwa,\n \t\t\t\t\t      vmwa->vf_ifindex,\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 6ad214b..af0dd3c 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -6,7 +6,6 @@\n #ifndef RTE_PMD_MLX5_PRM_H_\n #define RTE_PMD_MLX5_PRM_H_\n \n-#include <assert.h>\n \n /* Verbs header. */\n /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */\n@@ -545,7 +544,7 @@ struct mlx5_modification_cmd {\n \n #define MLX5_SET64(typ, p, fld, v) \\\n \tdo { \\\n-\t\tassert(__mlx5_bit_sz(typ, fld) == 64); \\\n+\t\tMLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \\\n \t\t*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \\\n \t\t\trte_cpu_to_be_64(v); \\\n \t} while (0)\ndiff --git a/drivers/net/mlx5/mlx5_rss.c b/drivers/net/mlx5/mlx5_rss.c\nindex 1028264..58bc17f 100644\n--- a/drivers/net/mlx5/mlx5_rss.c\n+++ b/drivers/net/mlx5/mlx5_rss.c\n@@ -7,7 +7,6 @@\n #include <stdint.h>\n #include <errno.h>\n #include <string.h>\n-#include <assert.h>\n \n /* Verbs header. */\n /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */\n@@ -218,7 +217,7 @@\n \t\tpos = i % RTE_RETA_GROUP_SIZE;\n \t\tif (((reta_conf[idx].mask >> i) & 0x1) == 0)\n \t\t\tcontinue;\n-\t\tassert(reta_conf[idx].reta[pos] < priv->rxqs_n);\n+\t\tMLX5_ASSERT(reta_conf[idx].reta[pos] < priv->rxqs_n);\n \t\t(*priv->reta_idx)[i] = reta_conf[idx].reta[pos];\n \t}\n \tif (dev->data->dev_started) {\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 4092cb7..0f88cf0 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -4,7 +4,6 @@\n  */\n \n #include <stddef.h>\n-#include <assert.h>\n #include <errno.h>\n #include <string.h>\n #include <stdint.h>\n@@ -124,7 +123,7 @@\n \t\t\t++n;\n \t}\n \t/* Multi-Packet RQ can't be partially configured. */\n-\tassert(n == 0 || n == n_ibv);\n+\tMLX5_ASSERT(n == 0 || n == n_ibv);\n \treturn n == n_ibv;\n }\n \n@@ -207,11 +206,11 @@\n \t\t\tgoto error;\n \t\t}\n \t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n-\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n+\t\tMLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n \t\t/* Buffer is supposed to be empty. */\n-\t\tassert(rte_pktmbuf_data_len(buf) == 0);\n-\t\tassert(rte_pktmbuf_pkt_len(buf) == 0);\n-\t\tassert(!buf->next);\n+\t\tMLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);\n+\t\tMLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);\n+\t\tMLX5_ASSERT(!buf->next);\n \t\t/* Only the first segment keeps headroom. */\n \t\tif (i % sges_n)\n \t\t\tSET_DATA_OFF(buf, 0);\n@@ -300,7 +299,7 @@\n \t\trxq->port_id, rxq->idx);\n \tif (rxq->mprq_bufs == NULL)\n \t\treturn;\n-\tassert(mlx5_rxq_check_vec_support(rxq) < 0);\n+\tMLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);\n \tfor (i = 0; (i != (1u << rxq->elts_n)); ++i) {\n \t\tif ((*rxq->mprq_bufs)[i] != NULL)\n \t\t\tmlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);\n@@ -657,7 +656,7 @@\n {\n \tstruct mlx5_devx_modify_rq_attr rq_attr = { 0 };\n \n-\tassert(rxq_obj);\n+\tMLX5_ASSERT(rxq_obj);\n \trq_attr.state = MLX5_RQC_STATE_RST;\n \trq_attr.rq_state = MLX5_RQC_STATE_RDY;\n \tmlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);\n@@ -676,26 +675,26 @@\n static int\n mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)\n {\n-\tassert(rxq_obj);\n+\tMLX5_ASSERT(rxq_obj);\n \tif (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {\n \t\tswitch (rxq_obj->type) {\n \t\tcase MLX5_RXQ_OBJ_TYPE_IBV:\n-\t\t\tassert(rxq_obj->wq);\n-\t\t\tassert(rxq_obj->cq);\n+\t\t\tMLX5_ASSERT(rxq_obj->wq);\n+\t\t\tMLX5_ASSERT(rxq_obj->cq);\n \t\t\trxq_free_elts(rxq_obj->rxq_ctrl);\n \t\t\tclaim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));\n \t\t\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));\n \t\t\tbreak;\n \t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_RQ:\n-\t\t\tassert(rxq_obj->cq);\n-\t\t\tassert(rxq_obj->rq);\n+\t\t\tMLX5_ASSERT(rxq_obj->cq);\n+\t\t\tMLX5_ASSERT(rxq_obj->rq);\n \t\t\trxq_free_elts(rxq_obj->rxq_ctrl);\n \t\t\tclaim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));\n \t\t\trxq_release_rq_resources(rxq_obj->rxq_ctrl);\n \t\t\tclaim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));\n \t\t\tbreak;\n \t\tcase MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:\n-\t\t\tassert(rxq_obj->rq);\n+\t\t\tMLX5_ASSERT(rxq_obj->rq);\n \t\t\trxq_obj_hairpin_release(rxq_obj);\n \t\t\tbreak;\n \t\t}\n@@ -1267,8 +1266,8 @@\n \tstruct mlx5_rxq_obj *tmpl = NULL;\n \tint ret = 0;\n \n-\tassert(rxq_data);\n-\tassert(!rxq_ctrl->obj);\n+\tMLX5_ASSERT(rxq_data);\n+\tMLX5_ASSERT(!rxq_ctrl->obj);\n \ttmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,\n \t\t\t\t rxq_ctrl->socket);\n \tif (!tmpl) {\n@@ -1339,8 +1338,8 @@ struct mlx5_rxq_obj *\n \tint ret = 0;\n \tstruct mlx5dv_obj obj;\n \n-\tassert(rxq_data);\n-\tassert(!rxq_ctrl->obj);\n+\tMLX5_ASSERT(rxq_data);\n+\tMLX5_ASSERT(!rxq_ctrl->obj);\n \tif (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)\n \t\treturn mlx5_rxq_obj_hairpin_new(dev, idx);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;\n@@ -1634,7 +1633,7 @@ struct mlx5_rxq_obj *\n \t\tif (strd_sz_n < rxq->strd_sz_n)\n \t\t\tstrd_sz_n = rxq->strd_sz_n;\n \t}\n-\tassert(strd_num_n && strd_sz_n);\n+\tMLX5_ASSERT(strd_num_n && strd_sz_n);\n \tbuf_len = (1 << strd_num_n) * (1 << strd_sz_n);\n \tobj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *\n \t\tsizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;\n@@ -1739,7 +1738,7 @@ struct mlx5_rxq_obj *\n \t    MLX5_MAX_TCP_HDR_OFFSET)\n \t\tmax_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;\n \tmax_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);\n-\tassert(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);\n+\tMLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);\n \tmax_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;\n \tif (priv->max_lro_msg_size)\n \t\tpriv->max_lro_msg_size =\n@@ -2072,7 +2071,7 @@ struct mlx5_rxq_ctrl *\n \tif (!(*priv->rxqs)[idx])\n \t\treturn 0;\n \trxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);\n-\tassert(rxq_ctrl->priv);\n+\tMLX5_ASSERT(rxq_ctrl->priv);\n \tif (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))\n \t\trxq_ctrl->obj = NULL;\n \tif (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 2f775bd..ee8e772 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -3,7 +3,6 @@\n  * Copyright 2015-2019 Mellanox Technologies, Ltd\n  */\n \n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <stdlib.h>\n@@ -778,7 +777,7 @@ enum mlx5_txcmp_code {\n \t\t\tbyte_count = DATA_LEN(buf);\n \t\t}\n \t\t/* scat->addr must be able to store a pointer. */\n-\t\tassert(sizeof(scat->addr) >= sizeof(uintptr_t));\n+\t\tMLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));\n \t\t*scat = (struct mlx5_wqe_data_seg){\n \t\t\t.addr = rte_cpu_to_be_64(addr),\n \t\t\t.byte_count = rte_cpu_to_be_32(byte_count),\n@@ -1319,7 +1318,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tbreak;\n \t\t\t}\n \t\t\twhile (pkt != seg) {\n-\t\t\t\tassert(pkt != (*rxq->elts)[idx]);\n+\t\t\t\tMLX5_ASSERT(pkt != (*rxq->elts)[idx]);\n \t\t\t\trep = NEXT(pkt);\n \t\t\t\tNEXT(pkt) = NULL;\n \t\t\t\tNB_SEGS(pkt) = 1;\n@@ -1336,7 +1335,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tbreak;\n \t\t\t}\n \t\t\tpkt = seg;\n-\t\t\tassert(len >= (rxq->crc_present << 2));\n+\t\t\tMLX5_ASSERT(len >= (rxq->crc_present << 2));\n \t\t\tpkt->ol_flags &= EXT_ATTACHED_MBUF;\n \t\t\t/* If compressed, take hash result from mini-CQE. */\n \t\t\trss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?\n@@ -1527,7 +1526,7 @@ enum mlx5_txcmp_code {\n \t\t&((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;\n \tvoid *addr;\n \n-\tassert(rep != NULL);\n+\tMLX5_ASSERT(rep != NULL);\n \t/* Replace MPRQ buf. */\n \t(*rxq->mprq_bufs)[rq_idx] = rep;\n \t/* Replace WQE. */\n@@ -1617,7 +1616,7 @@ enum mlx5_txcmp_code {\n \t\tbyte_cnt = ret;\n \t\tstrd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>\n \t\t\t   MLX5_MPRQ_STRIDE_NUM_SHIFT;\n-\t\tassert(strd_cnt);\n+\t\tMLX5_ASSERT(strd_cnt);\n \t\tconsumed_strd += strd_cnt;\n \t\tif (byte_cnt & MLX5_MPRQ_FILLER_MASK)\n \t\t\tcontinue;\n@@ -1628,8 +1627,9 @@ enum mlx5_txcmp_code {\n \t\t\t/* mini-CQE for MPRQ doesn't have hash result. */\n \t\t\tstrd_idx = rte_be_to_cpu_16(mcqe->stride_idx);\n \t\t}\n-\t\tassert(strd_idx < strd_n);\n-\t\tassert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));\n+\t\tMLX5_ASSERT(strd_idx < strd_n);\n+\t\tMLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &\n+\t\t\t    wq_mask));\n \t\tlro_num_seg = cqe->lro_num_seg;\n \t\t/*\n \t\t * Currently configured to receive a packet per a stride. But if\n@@ -1648,7 +1648,7 @@ enum mlx5_txcmp_code {\n \t\t\tbreak;\n \t\t}\n \t\tlen = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;\n-\t\tassert((int)len >= (rxq->crc_present << 2));\n+\t\tMLX5_ASSERT((int)len >= (rxq->crc_present << 2));\n \t\tif (rxq->crc_present)\n \t\t\tlen -= RTE_ETHER_CRC_LEN;\n \t\toffset = strd_idx * strd_sz + strd_shift;\n@@ -1678,8 +1678,8 @@ enum mlx5_txcmp_code {\n \n \t\t\t/* Increment the refcnt of the whole chunk. */\n \t\t\trte_atomic16_add_return(&buf->refcnt, 1);\n-\t\t\tassert((uint16_t)rte_atomic16_read(&buf->refcnt) <=\n-\t\t\t       strd_n + 1);\n+\t\t\tMLX5_ASSERT((uint16_t)rte_atomic16_read(&buf->refcnt) <=\n+\t\t\t\t    strd_n + 1);\n \t\t\tbuf_addr = RTE_PTR_SUB(addr, headroom_sz);\n \t\t\t/*\n \t\t\t * MLX5 device doesn't use iova but it is necessary in a\n@@ -1700,7 +1700,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\t\t  buf_len, shinfo);\n \t\t\t/* Set mbuf head-room. */\n \t\t\tpkt->data_off = headroom_sz;\n-\t\t\tassert(pkt->ol_flags == EXT_ATTACHED_MBUF);\n+\t\t\tMLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);\n \t\t\t/*\n \t\t\t * Prevent potential overflow due to MTU change through\n \t\t\t * kernel interface.\n@@ -1866,8 +1866,8 @@ enum mlx5_txcmp_code {\n \t * copying pointers to temporary array\n \t * for rte_mempool_put_bulk() calls.\n \t */\n-\tassert(pkts);\n-\tassert(pkts_n);\n+\tMLX5_ASSERT(pkts);\n+\tMLX5_ASSERT(pkts_n);\n \tfor (;;) {\n \t\tfor (;;) {\n \t\t\t/*\n@@ -1876,7 +1876,7 @@ enum mlx5_txcmp_code {\n \t\t\t */\n \t\t\tmbuf = rte_pktmbuf_prefree_seg(*pkts);\n \t\t\tif (likely(mbuf != NULL)) {\n-\t\t\t\tassert(mbuf == *pkts);\n+\t\t\t\tMLX5_ASSERT(mbuf == *pkts);\n \t\t\t\tif (likely(n_free != 0)) {\n \t\t\t\t\tif (unlikely(pool != mbuf->pool))\n \t\t\t\t\t\t/* From different pool. */\n@@ -1913,9 +1913,9 @@ enum mlx5_txcmp_code {\n \t\t\t * This loop is implemented to avoid multiple\n \t\t\t * inlining of rte_mempool_put_bulk().\n \t\t\t */\n-\t\t\tassert(pool);\n-\t\t\tassert(p_free);\n-\t\t\tassert(n_free);\n+\t\t\tMLX5_ASSERT(pool);\n+\t\t\tMLX5_ASSERT(p_free);\n+\t\t\tMLX5_ASSERT(n_free);\n \t\t\t/*\n \t\t\t * Free the array of pre-freed mbufs\n \t\t\t * belonging to the same memory pool.\n@@ -1963,8 +1963,8 @@ enum mlx5_txcmp_code {\n {\n \tuint16_t n_elts = tail - txq->elts_tail;\n \n-\tassert(n_elts);\n-\tassert(n_elts <= txq->elts_s);\n+\tMLX5_ASSERT(n_elts);\n+\tMLX5_ASSERT(n_elts <= txq->elts_s);\n \t/*\n \t * Implement a loop to support ring buffer wraparound\n \t * with single inlining of mlx5_tx_free_mbuf().\n@@ -1974,8 +1974,8 @@ enum mlx5_txcmp_code {\n \n \t\tpart = txq->elts_s - (txq->elts_tail & txq->elts_m);\n \t\tpart = RTE_MIN(part, n_elts);\n-\t\tassert(part);\n-\t\tassert(part <= txq->elts_s);\n+\t\tMLX5_ASSERT(part);\n+\t\tMLX5_ASSERT(part <= txq->elts_s);\n \t\tmlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],\n \t\t\t\t  part, olx);\n \t\ttxq->elts_tail += part;\n@@ -2006,11 +2006,11 @@ enum mlx5_txcmp_code {\n \tunsigned int part;\n \tstruct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;\n \n-\tassert(pkts);\n-\tassert(pkts_n);\n+\tMLX5_ASSERT(pkts);\n+\tMLX5_ASSERT(pkts_n);\n \tpart = txq->elts_s - (txq->elts_head & txq->elts_m);\n-\tassert(part);\n-\tassert(part <= txq->elts_s);\n+\tMLX5_ASSERT(part);\n+\tMLX5_ASSERT(part <= txq->elts_s);\n \t/* This code is a good candidate for vectorizing with SIMD. */\n \trte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),\n \t\t   (void *)pkts,\n@@ -2046,7 +2046,7 @@ enum mlx5_txcmp_code {\n \t\ttail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];\n \t\tif (likely(tail != txq->elts_tail)) {\n \t\t\tmlx5_tx_free_elts(txq, tail, olx);\n-\t\t\tassert(tail == txq->elts_tail);\n+\t\t\tMLX5_ASSERT(tail == txq->elts_tail);\n \t\t}\n \t}\n }\n@@ -2084,7 +2084,7 @@ enum mlx5_txcmp_code {\n \t\tif (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {\n \t\t\tif (likely(ret != MLX5_CQE_STATUS_ERR)) {\n \t\t\t\t/* No new CQEs in completion queue. */\n-\t\t\t\tassert(ret == MLX5_CQE_STATUS_HW_OWN);\n+\t\t\t\tMLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);\n \t\t\t\tbreak;\n \t\t\t}\n \t\t\t/*\n@@ -2116,8 +2116,9 @@ enum mlx5_txcmp_code {\n \t\t\tcontinue;\n \t\t}\n \t\t/* Normal transmit completion. */\n-\t\tassert(ci != txq->cq_pi);\n-\t\tassert((txq->fcqs[ci & txq->cqe_m] >> 16) == cqe->wqe_counter);\n+\t\tMLX5_ASSERT(ci != txq->cq_pi);\n+\t\tMLX5_ASSERT((txq->fcqs[ci & txq->cqe_m] >> 16) ==\n+\t\t\t    cqe->wqe_counter);\n \t\t++ci;\n \t\tlast_cqe = cqe;\n \t\t/*\n@@ -2186,7 +2187,7 @@ enum mlx5_txcmp_code {\n \t\ttxq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;\n #endif\n \t\t/* A CQE slot must always be available. */\n-\t\tassert((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);\n+\t\tMLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);\n \t}\n }\n \n@@ -2300,7 +2301,7 @@ enum mlx5_txcmp_code {\n \t\t * We should get here only if device support\n \t\t * this feature correctly.\n \t\t */\n-\t\tassert(txq->vlan_en);\n+\t\tMLX5_ASSERT(txq->vlan_en);\n \t\tes->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |\n \t\t\t\t\t\t  loc->mbuf->vlan_tci);\n \t} else {\n@@ -2378,7 +2379,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\t\t loc->mbuf->vlan_tci);\n \t\tpdst += sizeof(struct rte_vlan_hdr);\n \t\t/* Copy the rest two bytes from packet data. */\n-\t\tassert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));\n+\t\tMLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));\n \t\t*(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;\n \t} else {\n \t\t/* Fill the gap in the title WQEBB with inline data. */\n@@ -2471,7 +2472,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\t\t loc->mbuf->vlan_tci);\n \t\tpdst += sizeof(struct rte_vlan_hdr);\n \t\t/* Copy the rest two bytes from packet data. */\n-\t\tassert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));\n+\t\tMLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));\n \t\t*(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;\n \t\tpsrc += sizeof(uint16_t);\n \t} else {\n@@ -2480,11 +2481,11 @@ enum mlx5_txcmp_code {\n \t\tpsrc += sizeof(rte_v128u32_t);\n \t}\n \tpdst = (uint8_t *)(es + 2);\n-\tassert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);\n-\tassert(pdst < (uint8_t *)txq->wqes_end);\n+\tMLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\tMLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);\n \tinlen -= MLX5_ESEG_MIN_INLINE_SIZE;\n \tif (!inlen) {\n-\t\tassert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));\n+\t\tMLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));\n \t\treturn (struct mlx5_wqe_dseg *)pdst;\n \t}\n \t/*\n@@ -2539,7 +2540,7 @@ enum mlx5_txcmp_code {\n \tunsigned int part, dlen;\n \tuint8_t *psrc;\n \n-\tassert(len);\n+\tMLX5_ASSERT(len);\n \tdo {\n \t\t/* Allow zero length packets, must check first. */\n \t\tdlen = rte_pktmbuf_data_len(loc->mbuf);\n@@ -2549,8 +2550,8 @@ enum mlx5_txcmp_code {\n \t\t\tloc->mbuf = mbuf->next;\n \t\t\trte_pktmbuf_free_seg(mbuf);\n \t\t\tloc->mbuf_off = 0;\n-\t\t\tassert(loc->mbuf_nseg > 1);\n-\t\t\tassert(loc->mbuf);\n+\t\t\tMLX5_ASSERT(loc->mbuf_nseg > 1);\n+\t\t\tMLX5_ASSERT(loc->mbuf);\n \t\t\t--loc->mbuf_nseg;\n \t\t\tcontinue;\n \t\t}\n@@ -2569,7 +2570,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tloc->mbuf = mbuf->next;\n \t\t\t\trte_pktmbuf_free_seg(mbuf);\n \t\t\t\tloc->mbuf_off = 0;\n-\t\t\t\tassert(loc->mbuf_nseg >= 1);\n+\t\t\t\tMLX5_ASSERT(loc->mbuf_nseg >= 1);\n \t\t\t\t--loc->mbuf_nseg;\n \t\t\t}\n \t\t\treturn;\n@@ -2649,7 +2650,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t sizeof(struct rte_vlan_hdr) +\n \t\t\t\t 2 * RTE_ETHER_ADDR_LEN),\n \t\t      \"invalid Ethernet Segment data size\");\n-\tassert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\tMLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);\n \tes->inline_hdr_sz = rte_cpu_to_be_16(inlen);\n \tpdst = (uint8_t *)&es->inline_data;\n \tif (MLX5_TXOFF_CONFIG(VLAN) && vlan) {\n@@ -2662,14 +2663,14 @@ enum mlx5_txcmp_code {\n \t\tpdst += sizeof(struct rte_vlan_hdr);\n \t\tinlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);\n \t}\n-\tassert(pdst < (uint8_t *)txq->wqes_end);\n+\tMLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);\n \t/*\n \t * The WQEBB space availability is checked by caller.\n \t * Here we should be aware of WQE ring buffer wraparound only.\n \t */\n \tpart = (uint8_t *)txq->wqes_end - pdst;\n \tpart = RTE_MIN(part, inlen);\n-\tassert(part);\n+\tMLX5_ASSERT(part);\n \tdo {\n \t\tmlx5_tx_mseg_memcpy(pdst, loc, part, olx);\n \t\tinlen -= part;\n@@ -2709,7 +2710,7 @@ enum mlx5_txcmp_code {\n \t\t unsigned int olx __rte_unused)\n \n {\n-\tassert(len);\n+\tMLX5_ASSERT(len);\n \tdseg->bcount = rte_cpu_to_be_32(len);\n \tdseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);\n \tdseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);\n@@ -2745,7 +2746,7 @@ enum mlx5_txcmp_code {\n {\n \tuintptr_t dst, src;\n \n-\tassert(len);\n+\tMLX5_ASSERT(len);\n \tif (len > MLX5_DSEG_MIN_INLINE_SIZE) {\n \t\tdseg->bcount = rte_cpu_to_be_32(len);\n \t\tdseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);\n@@ -2759,7 +2760,7 @@ enum mlx5_txcmp_code {\n \tsrc = (uintptr_t)buf;\n \tif (len & 0x08) {\n #ifdef RTE_ARCH_STRICT_ALIGN\n-\t\tassert(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));\n+\t\tMLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));\n \t\t*(uint32_t *)dst = *(unaligned_uint32_t *)src;\n \t\tdst += sizeof(uint32_t);\n \t\tsrc += sizeof(uint32_t);\n@@ -2878,7 +2879,7 @@ enum mlx5_txcmp_code {\n \tunsigned int part;\n \tuint8_t *pdst;\n \n-\tassert(len > MLX5_ESEG_MIN_INLINE_SIZE);\n+\tMLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);\n \tstatic_assert(MLX5_DSEG_MIN_INLINE_SIZE ==\n \t\t\t\t (2 * RTE_ETHER_ADDR_LEN),\n \t\t      \"invalid Data Segment data size\");\n@@ -2890,7 +2891,7 @@ enum mlx5_txcmp_code {\n \tpdst += MLX5_DSEG_MIN_INLINE_SIZE;\n \tlen -= MLX5_DSEG_MIN_INLINE_SIZE;\n \t/* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */\n-\tassert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));\n+\tMLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));\n \tif (unlikely(pdst >= (uint8_t *)txq->wqes_end))\n \t\tpdst = (uint8_t *)txq->wqes;\n \t*(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |\n@@ -2958,7 +2959,7 @@ enum mlx5_txcmp_code {\n \tstruct mlx5_wqe_dseg *restrict dseg;\n \tunsigned int ds;\n \n-\tassert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);\n+\tMLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);\n \tloc->mbuf_nseg = NB_SEGS(loc->mbuf);\n \tloc->mbuf_off = 0;\n \n@@ -2979,8 +2980,8 @@ enum mlx5_txcmp_code {\n \t\t * Non-zero offset means there are some data\n \t\t * remained in the packet.\n \t\t */\n-\t\tassert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));\n-\t\tassert(rte_pktmbuf_data_len(loc->mbuf));\n+\t\tMLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));\n+\t\tMLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));\n \t\tdptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,\n \t\t\t\t\t       loc->mbuf_off);\n \t\tdlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;\n@@ -2992,7 +2993,7 @@ enum mlx5_txcmp_code {\n \t\t\tdseg = (struct mlx5_wqe_dseg *)txq->wqes;\n \t\tmlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);\n \t\t/* Store the mbuf to be freed on completion. */\n-\t\tassert(loc->elts_free);\n+\t\tMLX5_ASSERT(loc->elts_free);\n \t\ttxq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;\n \t\t--loc->elts_free;\n \t\t++dseg;\n@@ -3018,7 +3019,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t(txq, loc, dseg,\n \t\t\t\t rte_pktmbuf_mtod(loc->mbuf, uint8_t *),\n \t\t\t\t rte_pktmbuf_data_len(loc->mbuf), olx);\n-\t\t\tassert(loc->elts_free);\n+\t\t\tMLX5_ASSERT(loc->elts_free);\n \t\t\ttxq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;\n \t\t\t--loc->elts_free;\n \t\t\t++dseg;\n@@ -3085,7 +3086,7 @@ enum mlx5_txcmp_code {\n \t\t     inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||\n \t\t     inlen > (dlen + vlan)))\n \t\treturn MLX5_TXCMP_CODE_ERROR;\n-\tassert(inlen >= txq->inlen_mode);\n+\tMLX5_ASSERT(inlen >= txq->inlen_mode);\n \t/*\n \t * Check whether there are enough free WQEBBs:\n \t * - Control Segment\n@@ -3157,7 +3158,7 @@ enum mlx5_txcmp_code {\n \tstruct mlx5_wqe *restrict wqe;\n \tunsigned int ds, nseg;\n \n-\tassert(NB_SEGS(loc->mbuf) > 1);\n+\tMLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);\n \t/*\n \t * No inline at all, it means the CPU cycles saving\n \t * is prioritized at configuration, we should not\n@@ -3264,8 +3265,8 @@ enum mlx5_txcmp_code {\n \tstruct mlx5_wqe *restrict wqe;\n \tunsigned int ds, inlen, dlen, vlan = 0;\n \n-\tassert(MLX5_TXOFF_CONFIG(INLINE));\n-\tassert(NB_SEGS(loc->mbuf) > 1);\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n+\tMLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);\n \t/*\n \t * First calculate data length to be inlined\n \t * to estimate the required space for WQE.\n@@ -3277,7 +3278,7 @@ enum mlx5_txcmp_code {\n \t/* Check against minimal length. */\n \tif (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)\n \t\treturn MLX5_TXCMP_CODE_ERROR;\n-\tassert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\tMLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);\n \tif (inlen > txq->inlen_send) {\n \t\tstruct rte_mbuf *mbuf;\n \t\tunsigned int nxlen;\n@@ -3289,8 +3290,9 @@ enum mlx5_txcmp_code {\n \t\t * inlining is required.\n \t\t */\n \t\tif (txq->inlen_mode) {\n-\t\t\tassert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);\n-\t\t\tassert(txq->inlen_mode <= txq->inlen_send);\n+\t\t\tMLX5_ASSERT(txq->inlen_mode >=\n+\t\t\t\t    MLX5_ESEG_MIN_INLINE_SIZE);\n+\t\t\tMLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);\n \t\t\tinlen = txq->inlen_mode;\n \t\t} else {\n \t\t\tif (!vlan || txq->vlan_en) {\n@@ -3322,7 +3324,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tdo {\n \t\t\t\t\tsmlen = nxlen;\n \t\t\t\t\tmbuf = NEXT(mbuf);\n-\t\t\t\t\tassert(mbuf);\n+\t\t\t\t\tMLX5_ASSERT(mbuf);\n \t\t\t\t\tnxlen = rte_pktmbuf_data_len(mbuf);\n \t\t\t\t\tnxlen += smlen;\n \t\t\t\t} while (unlikely(nxlen < inlen));\n@@ -3338,7 +3340,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tinlen = nxlen;\n \t\t\t\tmbuf = NEXT(mbuf);\n \t\t\t\t/* There should be not end of packet. */\n-\t\t\t\tassert(mbuf);\n+\t\t\t\tMLX5_ASSERT(mbuf);\n \t\t\t\tnxlen = inlen + rte_pktmbuf_data_len(mbuf);\n \t\t\t} while (unlikely(nxlen < txq->inlen_send));\n \t\t}\n@@ -3366,7 +3368,7 @@ enum mlx5_txcmp_code {\n \t * Estimate the number of Data Segments conservatively,\n \t * supposing no any mbufs is being freed during inlining.\n \t */\n-\tassert(inlen <= txq->inlen_send);\n+\tMLX5_ASSERT(inlen <= txq->inlen_send);\n \tds = NB_SEGS(loc->mbuf) + 2 + (inlen -\n \t\t\t\t       MLX5_ESEG_MIN_INLINE_SIZE +\n \t\t\t\t       MLX5_WSEG_SIZE +\n@@ -3425,14 +3427,14 @@ enum mlx5_txcmp_code {\n \t\t   struct mlx5_txq_local *restrict loc,\n \t\t   unsigned int olx)\n {\n-\tassert(loc->elts_free && loc->wqe_free);\n-\tassert(pkts_n > loc->pkts_sent);\n+\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n+\tMLX5_ASSERT(pkts_n > loc->pkts_sent);\n \tpkts += loc->pkts_sent + 1;\n \tpkts_n -= loc->pkts_sent;\n \tfor (;;) {\n \t\tenum mlx5_txcmp_code ret;\n \n-\t\tassert(NB_SEGS(loc->mbuf) > 1);\n+\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);\n \t\t/*\n \t\t * Estimate the number of free elts quickly but\n \t\t * conservatively. Some segment may be fully inlined\n@@ -3472,7 +3474,7 @@ enum mlx5_txcmp_code {\n \t\t\treturn MLX5_TXCMP_CODE_TSO;\n \t\treturn MLX5_TXCMP_CODE_SINGLE;\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n }\n \n /**\n@@ -3514,8 +3516,8 @@ enum mlx5_txcmp_code {\n \t\t  struct mlx5_txq_local *restrict loc,\n \t\t  unsigned int olx)\n {\n-\tassert(loc->elts_free && loc->wqe_free);\n-\tassert(pkts_n > loc->pkts_sent);\n+\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n+\tMLX5_ASSERT(pkts_n > loc->pkts_sent);\n \tpkts += loc->pkts_sent + 1;\n \tpkts_n -= loc->pkts_sent;\n \tfor (;;) {\n@@ -3524,7 +3526,7 @@ enum mlx5_txcmp_code {\n \t\tunsigned int ds, dlen, hlen, ntcp, vlan = 0;\n \t\tuint8_t *dptr;\n \n-\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\tdlen = rte_pktmbuf_data_len(loc->mbuf);\n \t\tif (MLX5_TXOFF_CONFIG(VLAN) &&\n \t\t    loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {\n@@ -3608,7 +3610,7 @@ enum mlx5_txcmp_code {\n \t\t\treturn MLX5_TXCMP_CODE_SINGLE;\n \t\t/* Continue with the next TSO packet. */\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n }\n \n /**\n@@ -3715,7 +3717,7 @@ enum mlx5_txcmp_code {\n \t\treturn false;\n \t/* There must be no VLAN packets in eMPW loop. */\n \tif (MLX5_TXOFF_CONFIG(VLAN))\n-\t\tassert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));\n+\t\tMLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));\n \treturn true;\n }\n \n@@ -3747,7 +3749,7 @@ enum mlx5_txcmp_code {\n \t\t   unsigned int slen,\n \t\t   unsigned int olx __rte_unused)\n {\n-\tassert(!MLX5_TXOFF_CONFIG(INLINE));\n+\tMLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t/* Update sent data bytes counter. */\n \t txq->stats.obytes += slen;\n@@ -3790,8 +3792,8 @@ enum mlx5_txcmp_code {\n \t\t   unsigned int slen,\n \t\t   unsigned int olx __rte_unused)\n {\n-\tassert(MLX5_TXOFF_CONFIG(INLINE));\n-\tassert((len % MLX5_WSEG_SIZE) == 0);\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n+\tMLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t/* Update sent data bytes counter. */\n \t txq->stats.obytes += slen;\n@@ -3863,10 +3865,10 @@ enum mlx5_txcmp_code {\n \t * and sends single-segment packet with eMPW opcode\n \t * without data inlining.\n \t */\n-\tassert(!MLX5_TXOFF_CONFIG(INLINE));\n-\tassert(MLX5_TXOFF_CONFIG(EMPW));\n-\tassert(loc->elts_free && loc->wqe_free);\n-\tassert(pkts_n > loc->pkts_sent);\n+\tMLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));\n+\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n+\tMLX5_ASSERT(pkts_n > loc->pkts_sent);\n \tstatic_assert(MLX5_EMPW_MIN_PACKETS >= 2, \"invalid min size\");\n \tpkts += loc->pkts_sent + 1;\n \tpkts_n -= loc->pkts_sent;\n@@ -3878,7 +3880,7 @@ enum mlx5_txcmp_code {\n \t\tunsigned int slen = 0;\n \n next_empw:\n-\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\tpart = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?\n \t\t\t\t       MLX5_MPW_MAX_PACKETS :\n \t\t\t\t       MLX5_EMPW_MAX_PACKETS);\n@@ -3944,7 +3946,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\t\t\treturn MLX5_TXCMP_CODE_MULTI;\n \t\t\t}\n-\t\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\t\tif (ret == MLX5_TXCMP_CODE_TSO) {\n \t\t\t\tpart -= loop;\n \t\t\t\tmlx5_tx_sdone_empw(txq, loc, part, slen, olx);\n@@ -3962,7 +3964,7 @@ enum mlx5_txcmp_code {\n \t\t\t\treturn MLX5_TXCMP_CODE_SINGLE;\n \t\t\t}\n \t\t\tif (ret != MLX5_TXCMP_CODE_EMPW) {\n-\t\t\t\tassert(false);\n+\t\t\t\tMLX5_ASSERT(false);\n \t\t\t\tpart -= loop;\n \t\t\t\tmlx5_tx_sdone_empw(txq, loc, part, slen, olx);\n \t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n@@ -3976,7 +3978,7 @@ enum mlx5_txcmp_code {\n \t\t\t * - packets length (legacy MPW only)\n \t\t\t */\n \t\t\tif (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {\n-\t\t\t\tassert(loop);\n+\t\t\t\tMLX5_ASSERT(loop);\n \t\t\t\tpart -= loop;\n \t\t\t\tmlx5_tx_sdone_empw(txq, loc, part, slen, olx);\n \t\t\t\tif (unlikely(!loc->elts_free ||\n@@ -3991,8 +3993,8 @@ enum mlx5_txcmp_code {\n \t\t\t\tdseg = (struct mlx5_wqe_dseg *)txq->wqes;\n \t\t}\n \t\t/* eMPW is built successfully, update loop parameters. */\n-\t\tassert(!loop);\n-\t\tassert(pkts_n >= part);\n+\t\tMLX5_ASSERT(!loop);\n+\t\tMLX5_ASSERT(pkts_n >= part);\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t\t/* Update sent data bytes counter. */\n \t\ttxq->stats.obytes += slen;\n@@ -4010,7 +4012,7 @@ enum mlx5_txcmp_code {\n \t\t\treturn ret;\n \t\t/* Continue sending eMPW batches. */\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n }\n \n /**\n@@ -4029,10 +4031,10 @@ enum mlx5_txcmp_code {\n \t * and sends single-segment packet with eMPW opcode\n \t * with data inlining.\n \t */\n-\tassert(MLX5_TXOFF_CONFIG(INLINE));\n-\tassert(MLX5_TXOFF_CONFIG(EMPW));\n-\tassert(loc->elts_free && loc->wqe_free);\n-\tassert(pkts_n > loc->pkts_sent);\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));\n+\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n+\tMLX5_ASSERT(pkts_n > loc->pkts_sent);\n \tstatic_assert(MLX5_EMPW_MIN_PACKETS >= 2, \"invalid min size\");\n \tpkts += loc->pkts_sent + 1;\n \tpkts_n -= loc->pkts_sent;\n@@ -4043,7 +4045,7 @@ enum mlx5_txcmp_code {\n \t\tunsigned int room, part, nlim;\n \t\tunsigned int slen = 0;\n \n-\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\t/*\n \t\t * Limits the amount of packets in one WQE\n \t\t * to improve CQE latency generation.\n@@ -4084,9 +4086,9 @@ enum mlx5_txcmp_code {\n \t\t\tuint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);\n \t\t\tunsigned int tlen;\n \n-\t\t\tassert(room >= MLX5_WQE_DSEG_SIZE);\n-\t\t\tassert((room % MLX5_WQE_DSEG_SIZE) == 0);\n-\t\t\tassert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);\n+\t\t\tMLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);\n+\t\t\tMLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);\n+\t\t\tMLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);\n \t\t\t/*\n \t\t\t * Some Tx offloads may cause an error if\n \t\t\t * packet is not long enough, check against\n@@ -4115,8 +4117,9 @@ enum mlx5_txcmp_code {\n \t\t\t\t * mlx5_tx_able_to_empw() and packet\n \t\t\t\t * fits into inline length guaranteed.\n \t\t\t\t */\n-\t\t\t\tassert((dlen + sizeof(struct rte_vlan_hdr)) <=\n-\t\t\t\t\ttxq->inlen_empw);\n+\t\t\t\tMLX5_ASSERT((dlen +\n+\t\t\t\t\t     sizeof(struct rte_vlan_hdr)) <=\n+\t\t\t\t\t    txq->inlen_empw);\n \t\t\t\ttlen += sizeof(struct rte_vlan_hdr);\n \t\t\t\tif (room < tlen)\n \t\t\t\t\tbreak;\n@@ -4133,7 +4136,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\t\t\t dptr, dlen, olx);\n \t\t\t}\n \t\t\ttlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);\n-\t\t\tassert(room >= tlen);\n+\t\t\tMLX5_ASSERT(room >= tlen);\n \t\t\troom -= tlen;\n \t\t\t/*\n \t\t\t * Packet data are completely inlined,\n@@ -4146,10 +4149,10 @@ enum mlx5_txcmp_code {\n \t\t\t * Not inlinable VLAN packets are\n \t\t\t * proceeded outside of this routine.\n \t\t\t */\n-\t\t\tassert(room >= MLX5_WQE_DSEG_SIZE);\n+\t\t\tMLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);\n \t\t\tif (MLX5_TXOFF_CONFIG(VLAN))\n-\t\t\t\tassert(!(loc->mbuf->ol_flags &\n-\t\t\t\t\t PKT_TX_VLAN_PKT));\n+\t\t\t\tMLX5_ASSERT(!(loc->mbuf->ol_flags &\n+\t\t\t\t\t    PKT_TX_VLAN_PKT));\n \t\t\tmlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);\n \t\t\t/* We have to store mbuf in elts.*/\n \t\t\ttxq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;\n@@ -4190,7 +4193,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\t\t\treturn MLX5_TXCMP_CODE_MULTI;\n \t\t\t}\n-\t\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\t\tif (ret == MLX5_TXCMP_CODE_TSO) {\n \t\t\t\tpart -= room;\n \t\t\t\tmlx5_tx_idone_empw(txq, loc, part, slen, olx);\n@@ -4208,7 +4211,7 @@ enum mlx5_txcmp_code {\n \t\t\t\treturn MLX5_TXCMP_CODE_SINGLE;\n \t\t\t}\n \t\t\tif (ret != MLX5_TXCMP_CODE_EMPW) {\n-\t\t\t\tassert(false);\n+\t\t\t\tMLX5_ASSERT(false);\n \t\t\t\tpart -= room;\n \t\t\t\tmlx5_tx_idone_empw(txq, loc, part, slen, olx);\n \t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n@@ -4235,7 +4238,7 @@ enum mlx5_txcmp_code {\n \t\t * We get here to close an existing eMPW\n \t\t * session and start the new one.\n \t\t */\n-\t\tassert(pkts_n);\n+\t\tMLX5_ASSERT(pkts_n);\n \t\tpart -= room;\n \t\tif (unlikely(!part))\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n@@ -4245,7 +4248,7 @@ enum mlx5_txcmp_code {\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\t/* Continue the loop with new eMPW session. */\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n }\n \n /**\n@@ -4263,15 +4266,15 @@ enum mlx5_txcmp_code {\n \t * Subroutine is the part of mlx5_tx_burst_single()\n \t * and sends single-segment packet with SEND opcode.\n \t */\n-\tassert(loc->elts_free && loc->wqe_free);\n-\tassert(pkts_n > loc->pkts_sent);\n+\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n+\tMLX5_ASSERT(pkts_n > loc->pkts_sent);\n \tpkts += loc->pkts_sent + 1;\n \tpkts_n -= loc->pkts_sent;\n \tfor (;;) {\n \t\tstruct mlx5_wqe *restrict wqe;\n \t\tenum mlx5_txcmp_code ret;\n \n-\t\tassert(NB_SEGS(loc->mbuf) == 1);\n+\t\tMLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);\n \t\tif (MLX5_TXOFF_CONFIG(INLINE)) {\n \t\t\tunsigned int inlen, vlan = 0;\n \n@@ -4291,7 +4294,8 @@ enum mlx5_txcmp_code {\n \t\t\t * Otherwise we would do extra check for data\n \t\t\t * size to avoid crashes due to length overflow.\n \t\t\t */\n-\t\t\tassert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\t\t\tMLX5_ASSERT(txq->inlen_send >=\n+\t\t\t\t    MLX5_ESEG_MIN_INLINE_SIZE);\n \t\t\tif (inlen <= txq->inlen_send) {\n \t\t\t\tunsigned int seg_n, wqe_n;\n \n@@ -4349,10 +4353,10 @@ enum mlx5_txcmp_code {\n \t\t\t\t * We should check the free space in\n \t\t\t\t * WQE ring buffer to inline partially.\n \t\t\t\t */\n-\t\t\t\tassert(txq->inlen_send >= txq->inlen_mode);\n-\t\t\t\tassert(inlen > txq->inlen_mode);\n-\t\t\t\tassert(txq->inlen_mode >=\n-\t\t\t\t\t\tMLX5_ESEG_MIN_INLINE_SIZE);\n+\t\t\t\tMLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);\n+\t\t\t\tMLX5_ASSERT(inlen > txq->inlen_mode);\n+\t\t\t\tMLX5_ASSERT(txq->inlen_mode >=\n+\t\t\t\t\t    MLX5_ESEG_MIN_INLINE_SIZE);\n \t\t\t\t/*\n \t\t\t\t * Check whether there are enough free WQEBBs:\n \t\t\t\t * - Control Segment\n@@ -4395,7 +4399,7 @@ enum mlx5_txcmp_code {\n \t\t\t\ttxq->wqe_ci += (ds + 3) / 4;\n \t\t\t\tloc->wqe_free -= (ds + 3) / 4;\n \t\t\t\t/* We have to store mbuf in elts.*/\n-\t\t\t\tassert(MLX5_TXOFF_CONFIG(INLINE));\n+\t\t\t\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n \t\t\t\ttxq->elts[txq->elts_head++ & txq->elts_m] =\n \t\t\t\t\t\tloc->mbuf;\n \t\t\t\t--loc->elts_free;\n@@ -4428,14 +4432,14 @@ enum mlx5_txcmp_code {\n \t\t\t\t * comparing with txq->inlen_send. We should\n \t\t\t\t * not get overflow here.\n \t\t\t\t */\n-\t\t\t\tassert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);\n+\t\t\t\tMLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);\n \t\t\t\tdlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;\n \t\t\t\tmlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],\n \t\t\t\t\t\t dptr, dlen, olx);\n \t\t\t\t++txq->wqe_ci;\n \t\t\t\t--loc->wqe_free;\n \t\t\t\t/* We have to store mbuf in elts.*/\n-\t\t\t\tassert(MLX5_TXOFF_CONFIG(INLINE));\n+\t\t\t\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));\n \t\t\t\ttxq->elts[txq->elts_head++ & txq->elts_m] =\n \t\t\t\t\t\tloc->mbuf;\n \t\t\t\t--loc->elts_free;\n@@ -4472,7 +4476,7 @@ enum mlx5_txcmp_code {\n \t\t\t * if no inlining is configured, this is done\n \t\t\t * by calling routine in a batch copy.\n \t\t\t */\n-\t\t\tassert(!MLX5_TXOFF_CONFIG(INLINE));\n+\t\t\tMLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));\n \t\t\t--loc->elts_free;\n #ifdef MLX5_PMD_SOFT_COUNTERS\n \t\t\t/* Update sent data bytes counter. */\n@@ -4494,7 +4498,7 @@ enum mlx5_txcmp_code {\n \t\tif (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))\n \t\t\treturn ret;\n \t}\n-\tassert(false);\n+\tMLX5_ASSERT(false);\n }\n \n static __rte_always_inline enum mlx5_txcmp_code\n@@ -4509,7 +4513,7 @@ enum mlx5_txcmp_code {\n \tret = mlx5_tx_able_to_empw(txq, loc, olx, false);\n \tif (ret == MLX5_TXCMP_CODE_SINGLE)\n \t\tgoto ordinary_send;\n-\tassert(ret == MLX5_TXCMP_CODE_EMPW);\n+\tMLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);\n \tfor (;;) {\n \t\t/* Optimize for inline/no inline eMPW send. */\n \t\tret = (MLX5_TXOFF_CONFIG(INLINE)) ?\n@@ -4520,14 +4524,14 @@ enum mlx5_txcmp_code {\n \t\tif (ret != MLX5_TXCMP_CODE_SINGLE)\n \t\t\treturn ret;\n \t\t/* The resources to send one packet should remain. */\n-\t\tassert(loc->elts_free && loc->wqe_free);\n+\t\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n ordinary_send:\n \t\tret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);\n-\t\tassert(ret != MLX5_TXCMP_CODE_SINGLE);\n+\t\tMLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);\n \t\tif (ret != MLX5_TXCMP_CODE_EMPW)\n \t\t\treturn ret;\n \t\t/* The resources to send one packet should remain. */\n-\t\tassert(loc->elts_free && loc->wqe_free);\n+\t\tMLX5_ASSERT(loc->elts_free && loc->wqe_free);\n \t}\n }\n \n@@ -4561,8 +4565,8 @@ enum mlx5_txcmp_code {\n \tenum mlx5_txcmp_code ret;\n \tunsigned int part;\n \n-\tassert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n-\tassert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n+\tMLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n+\tMLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n \tif (unlikely(!pkts_n))\n \t\treturn 0;\n \tloc.pkts_sent = 0;\n@@ -4588,10 +4592,10 @@ enum mlx5_txcmp_code {\n \t * - data inlining into WQEs, one packet may require multiple\n \t *   WQEBBs, the WQEs become the limiting factor.\n \t */\n-\tassert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n+\tMLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n \tloc.elts_free = txq->elts_s -\n \t\t\t\t(uint16_t)(txq->elts_head - txq->elts_tail);\n-\tassert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n+\tMLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n \tloc.wqe_free = txq->wqe_s -\n \t\t\t\t(uint16_t)(txq->wqe_ci - txq->wqe_pi);\n \tif (unlikely(!loc.elts_free || !loc.wqe_free))\n@@ -4613,7 +4617,7 @@ enum mlx5_txcmp_code {\n \t\t\t * per WQE, do it in dedicated routine.\n \t\t\t */\n enter_send_multi:\n-\t\t\tassert(loc.pkts_sent >= loc.pkts_copy);\n+\t\t\tMLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);\n \t\t\tpart = loc.pkts_sent - loc.pkts_copy;\n \t\t\tif (!MLX5_TXOFF_CONFIG(INLINE) && part) {\n \t\t\t\t/*\n@@ -4627,7 +4631,7 @@ enum mlx5_txcmp_code {\n \t\t\t\t\t\t  part, olx);\n \t\t\t\tloc.pkts_copy = loc.pkts_sent;\n \t\t\t}\n-\t\t\tassert(pkts_n > loc.pkts_sent);\n+\t\t\tMLX5_ASSERT(pkts_n > loc.pkts_sent);\n \t\t\tret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);\n \t\t\tif (!MLX5_TXOFF_CONFIG(INLINE))\n \t\t\t\tloc.pkts_copy = loc.pkts_sent;\n@@ -4669,7 +4673,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tgoto enter_send_tso;\n \t\t\t}\n \t\t\t/* We must not get here. Something is going wrong. */\n-\t\t\tassert(false);\n+\t\t\tMLX5_ASSERT(false);\n \t\t\ttxq->stats.oerrors++;\n \t\t\tbreak;\n \t\t}\n@@ -4683,8 +4687,8 @@ enum mlx5_txcmp_code {\n \t\t\t * in dedicated branch.\n \t\t\t */\n enter_send_tso:\n-\t\t\tassert(NB_SEGS(loc.mbuf) == 1);\n-\t\t\tassert(pkts_n > loc.pkts_sent);\n+\t\t\tMLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);\n+\t\t\tMLX5_ASSERT(pkts_n > loc.pkts_sent);\n \t\t\tret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);\n \t\t\t/*\n \t\t\t * These returned code checks are supposed\n@@ -4707,7 +4711,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tgoto enter_send_multi;\n \t\t\t}\n \t\t\t/* We must not get here. Something is going wrong. */\n-\t\t\tassert(false);\n+\t\t\tMLX5_ASSERT(false);\n \t\t\ttxq->stats.oerrors++;\n \t\t\tbreak;\n \t\t}\n@@ -4720,7 +4724,7 @@ enum mlx5_txcmp_code {\n \t\t * offloads are requested at SQ configuration time).\n \t\t */\n enter_send_single:\n-\t\tassert(pkts_n > loc.pkts_sent);\n+\t\tMLX5_ASSERT(pkts_n > loc.pkts_sent);\n \t\tret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);\n \t\t/*\n \t\t * These returned code checks are supposed\n@@ -4749,7 +4753,7 @@ enum mlx5_txcmp_code {\n \t\t\tgoto enter_send_tso;\n \t\t}\n \t\t/* We must not get here. Something is going wrong. */\n-\t\tassert(false);\n+\t\tMLX5_ASSERT(false);\n \t\ttxq->stats.oerrors++;\n \t\tbreak;\n \t}\n@@ -4759,7 +4763,8 @@ enum mlx5_txcmp_code {\n \t * - doorbell the hardware\n \t * - copy the rest of mbufs to elts (if any)\n \t */\n-\tassert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);\n+\tMLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||\n+\t\t    loc.pkts_sent >= loc.pkts_copy);\n \t/* Take a shortcut if nothing is sent. */\n \tif (unlikely(loc.pkts_sent == loc.pkts_loop))\n \t\tgoto burst_exit;\n@@ -4812,8 +4817,8 @@ enum mlx5_txcmp_code {\n \t\tmlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);\n \t\tloc.pkts_copy = loc.pkts_sent;\n \t}\n-\tassert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n-\tassert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n+\tMLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));\n+\tMLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));\n \tif (pkts_n > loc.pkts_sent) {\n \t\t/*\n \t\t * If burst size is large there might be no enough CQE\n@@ -5184,7 +5189,7 @@ enum mlx5_txcmp_code {\n \t\t      \"invalid WQE Data Segment size\");\n \tstatic_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,\n \t\t      \"invalid WQE size\");\n-\tassert(priv);\n+\tMLX5_ASSERT(priv);\n \tif (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {\n \t\t/* We should support Multi-Segment Packets. */\n \t\tolx |= MLX5_TXOFF_CONFIG_MULTI;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c\nindex d85f908..c99d632 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c\n@@ -3,7 +3,6 @@\n  * Copyright 2017 Mellanox Technologies, Ltd\n  */\n \n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <stdlib.h>\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h\nindex d8c07f2..915fafc 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.h\n@@ -84,9 +84,10 @@\n \t\t&((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[elts_idx];\n \tunsigned int i;\n \n-\tassert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n));\n-\tassert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));\n-\tassert(MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n) > MLX5_VPMD_DESCS_PER_LOOP);\n+\tMLX5_ASSERT(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n));\n+\tMLX5_ASSERT(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));\n+\tMLX5_ASSERT(MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n) >\n+\t\t    MLX5_VPMD_DESCS_PER_LOOP);\n \t/* Not to cross queue end. */\n \tn = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);\n \tif (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\nindex 9e5c6ee..6404cc2 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n@@ -6,7 +6,6 @@\n #ifndef RTE_PMD_MLX5_RXTX_VEC_ALTIVEC_H_\n #define RTE_PMD_MLX5_RXTX_VEC_ALTIVEC_H_\n \n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <stdlib.h>\n@@ -615,8 +614,8 @@\n \tconst vector unsigned short cqe_sel_mask2 =\n \t\t(vector unsigned short){0, 0, 0xffff, 0, 0, 0, 0, 0};\n \n-\tassert(rxq->sges_n == 0);\n-\tassert(rxq->cqe_n == rxq->elts_n);\n+\tMLX5_ASSERT(rxq->sges_n == 0);\n+\tMLX5_ASSERT(rxq->cqe_n == rxq->elts_n);\n \tcq = &(*rxq->cqes)[cq_idx];\n \trte_prefetch0(cq);\n \trte_prefetch0(cq + 1);\n@@ -646,7 +645,7 @@\n \tif (!pkts_n)\n \t\treturn rcvd_pkt;\n \t/* At this point, there shouldn't be any remaining packets. */\n-\tassert(rxq->decompressed == 0);\n+\tMLX5_ASSERT(rxq->decompressed == 0);\n \n \t/*\n \t * A. load first Qword (8bytes) in one loop.\n@@ -1062,7 +1061,7 @@\n \tif (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))\n \t\treturn rcvd_pkt;\n \t/* Update the consumer indexes for non-compressed CQEs. */\n-\tassert(nocmp_n <= pkts_n);\n+\tMLX5_ASSERT(nocmp_n <= pkts_n);\n \trxq->cq_ci += nocmp_n;\n \trxq->rq_pi += nocmp_n;\n \trcvd_pkt += nocmp_n;\n@@ -1072,7 +1071,7 @@\n #endif\n \t/* Decompress the last CQE if compressed. */\n \tif (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {\n-\t\tassert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n+\t\tMLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n \t\trxq->decompressed =\n \t\t\trxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);\n \t\t/* Return more packets if needed. */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex 332e9ac..f31c6f7 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -6,7 +6,6 @@\n #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_\n #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_\n \n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <stdlib.h>\n@@ -439,8 +438,8 @@\n \t};\n \tconst uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };\n \n-\tassert(rxq->sges_n == 0);\n-\tassert(rxq->cqe_n == rxq->elts_n);\n+\tMLX5_ASSERT(rxq->sges_n == 0);\n+\tMLX5_ASSERT(rxq->cqe_n == rxq->elts_n);\n \tcq = &(*rxq->cqes)[cq_idx];\n \trte_prefetch_non_temporal(cq);\n \trte_prefetch_non_temporal(cq + 1);\n@@ -469,7 +468,7 @@\n \tif (!pkts_n)\n \t\treturn rcvd_pkt;\n \t/* At this point, there shouldn't be any remained packets. */\n-\tassert(rxq->decompressed == 0);\n+\tMLX5_ASSERT(rxq->decompressed == 0);\n \t/*\n \t * Note that vectors have reverse order - {v3, v2, v1, v0}, because\n \t * there's no instruction to count trailing zeros. __builtin_clzl() is\n@@ -727,7 +726,7 @@\n \tif (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))\n \t\treturn rcvd_pkt;\n \t/* Update the consumer indexes for non-compressed CQEs. */\n-\tassert(nocmp_n <= pkts_n);\n+\tMLX5_ASSERT(nocmp_n <= pkts_n);\n \trxq->cq_ci += nocmp_n;\n \trxq->rq_pi += nocmp_n;\n \trcvd_pkt += nocmp_n;\n@@ -737,7 +736,7 @@\n #endif\n \t/* Decompress the last CQE if compressed. */\n \tif (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {\n-\t\tassert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n+\t\tMLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n \t\trxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],\n \t\t\t\t\t\t\t&elts[nocmp_n]);\n \t\t/* Return more packets if needed. */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex 07d40d5..f529933 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -6,7 +6,6 @@\n #ifndef RTE_PMD_MLX5_RXTX_VEC_SSE_H_\n #define RTE_PMD_MLX5_RXTX_VEC_SSE_H_\n \n-#include <assert.h>\n #include <stdint.h>\n #include <string.h>\n #include <stdlib.h>\n@@ -426,8 +425,8 @@\n \t\t\t      rxq->crc_present * RTE_ETHER_CRC_LEN);\n \tconst __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);\n \n-\tassert(rxq->sges_n == 0);\n-\tassert(rxq->cqe_n == rxq->elts_n);\n+\tMLX5_ASSERT(rxq->sges_n == 0);\n+\tMLX5_ASSERT(rxq->cqe_n == rxq->elts_n);\n \tcq = &(*rxq->cqes)[cq_idx];\n \trte_prefetch0(cq);\n \trte_prefetch0(cq + 1);\n@@ -456,7 +455,7 @@\n \tif (!pkts_n)\n \t\treturn rcvd_pkt;\n \t/* At this point, there shouldn't be any remained packets. */\n-\tassert(rxq->decompressed == 0);\n+\tMLX5_ASSERT(rxq->decompressed == 0);\n \t/*\n \t * A. load first Qword (8bytes) in one loop.\n \t * B. copy 4 mbuf pointers from elts ring to returing pkts.\n@@ -677,7 +676,7 @@\n \tif (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))\n \t\treturn rcvd_pkt;\n \t/* Update the consumer indexes for non-compressed CQEs. */\n-\tassert(nocmp_n <= pkts_n);\n+\tMLX5_ASSERT(nocmp_n <= pkts_n);\n \trxq->cq_ci += nocmp_n;\n \trxq->rq_pi += nocmp_n;\n \trcvd_pkt += nocmp_n;\n@@ -687,7 +686,7 @@\n #endif\n \t/* Decompress the last CQE if compressed. */\n \tif (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {\n-\t\tassert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n+\t\tMLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n \t\trxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],\n \t\t\t\t\t\t\t&elts[nocmp_n]);\n \t\t/* Return more packets if needed. */\ndiff --git a/drivers/net/mlx5/mlx5_socket.c b/drivers/net/mlx5/mlx5_socket.c\nindex b037f77..cf2b433 100644\n--- a/drivers/net/mlx5/mlx5_socket.c\n+++ b/drivers/net/mlx5/mlx5_socket.c\n@@ -126,7 +126,7 @@\n static int\n mlx5_pmd_interrupt_handler_install(void)\n {\n-\tassert(server_socket);\n+\tMLX5_ASSERT(server_socket);\n \tserver_intr_handle.fd = server_socket;\n \tserver_intr_handle.type = RTE_INTR_HANDLE_EXT;\n \treturn rte_intr_callback_register(&server_intr_handle,\n@@ -166,7 +166,7 @@\n \tint ret = -1;\n \tint flags;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tif (server_socket)\n \t\treturn 0;\n \t/*\ndiff --git a/drivers/net/mlx5/mlx5_stats.c b/drivers/net/mlx5/mlx5_stats.c\nindex 205e4fe..a40646a 100644\n--- a/drivers/net/mlx5/mlx5_stats.c\n+++ b/drivers/net/mlx5/mlx5_stats.c\n@@ -303,7 +303,7 @@\n \t\t\txstats_ctrl->info[idx] = mlx5_counters_init[i];\n \t\t}\n \t}\n-\tassert(xstats_ctrl->mlx5_stats_n <= MLX5_MAX_XSTATS);\n+\tMLX5_ASSERT(xstats_ctrl->mlx5_stats_n <= MLX5_MAX_XSTATS);\n \txstats_ctrl->stats_n = dev_stats_n;\n \t/* Copy to base at first time. */\n \tret = mlx5_read_dev_counters(dev, xstats_ctrl->base);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 5c48dcf..d52a246 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -4,7 +4,6 @@\n  */\n \n #include <stddef.h>\n-#include <assert.h>\n #include <errno.h>\n #include <string.h>\n #include <stdint.h>\n@@ -80,7 +79,7 @@\n \twhile (elts_tail != elts_head) {\n \t\tstruct rte_mbuf *elt = (*elts)[elts_tail & elts_m];\n \n-\t\tassert(elt != NULL);\n+\t\tMLX5_ASSERT(elt != NULL);\n \t\trte_pktmbuf_free_seg(elt);\n #ifdef MLX5_DEBUG\n \t\t/* Poisoning. */\n@@ -344,8 +343,8 @@\n \n \tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\treturn;\n-\tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n-\tassert(ppriv);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tMLX5_ASSERT(ppriv);\n \tppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;\n \ttxq_uar_ncattr_init(txq_ctrl, page_size);\n #ifndef RTE_ARCH_64\n@@ -383,7 +382,7 @@\n \n \tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\treturn 0;\n-\tassert(ppriv);\n+\tMLX5_ASSERT(ppriv);\n \t/*\n \t * As rdma-core, UARs are mapped in size of OS page\n \t * size. Ref to libmlx5 function: mlx5_init_context()\n@@ -444,7 +443,7 @@\n \tunsigned int i;\n \tint ret;\n \n-\tassert(rte_eal_process_type() == RTE_PROC_SECONDARY);\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_SECONDARY);\n \tfor (i = 0; i != priv->txqs_n; ++i) {\n \t\tif (!(*priv->txqs)[i])\n \t\t\tcontinue;\n@@ -452,7 +451,7 @@\n \t\ttxq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);\n \t\tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n \t\t\tcontinue;\n-\t\tassert(txq->idx == (uint16_t)i);\n+\t\tMLX5_ASSERT(txq->idx == (uint16_t)i);\n \t\tret = txq_uar_init_secondary(txq_ctrl, fd);\n \t\tif (ret)\n \t\t\tgoto error;\n@@ -492,8 +491,8 @@\n \tstruct mlx5_txq_obj *tmpl = NULL;\n \tint ret = 0;\n \n-\tassert(txq_data);\n-\tassert(!txq_ctrl->obj);\n+\tMLX5_ASSERT(txq_data);\n+\tMLX5_ASSERT(!txq_ctrl->obj);\n \ttmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,\n \t\t\t\t txq_ctrl->socket);\n \tif (!tmpl) {\n@@ -578,7 +577,7 @@ struct mlx5_txq_obj *\n \tif (priv->config.devx && !priv->sh->tdn)\n \t\tqp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;\n #endif\n-\tassert(txq_data);\n+\tMLX5_ASSERT(txq_data);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_TX_QUEUE;\n \tpriv->verbs_alloc_ctx.obj = txq_ctrl;\n \tif (mlx5_getenv_int(\"MLX5_ENABLE_CQE_COMPRESSION\")) {\n@@ -829,7 +828,7 @@ struct mlx5_txq_obj *\n int\n mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)\n {\n-\tassert(txq_obj);\n+\tMLX5_ASSERT(txq_obj);\n \tif (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {\n \t\tif (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {\n \t\t\tif (txq_obj->tis)\n@@ -1047,12 +1046,12 @@ struct mlx5_txq_obj *\n \t\t * beginning of inlining buffer in Ethernet\n \t\t * Segment.\n \t\t */\n-\t\tassert(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);\n-\t\tassert(inlen_send <= MLX5_WQE_SIZE_MAX +\n-\t\t\t\t     MLX5_ESEG_MIN_INLINE_SIZE -\n-\t\t\t\t     MLX5_WQE_CSEG_SIZE -\n-\t\t\t\t     MLX5_WQE_ESEG_SIZE -\n-\t\t\t\t     MLX5_WQE_DSEG_SIZE * 2);\n+\t\tMLX5_ASSERT(inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\t\tMLX5_ASSERT(inlen_send <= MLX5_WQE_SIZE_MAX +\n+\t\t\t\t\t  MLX5_ESEG_MIN_INLINE_SIZE -\n+\t\t\t\t\t  MLX5_WQE_CSEG_SIZE -\n+\t\t\t\t\t  MLX5_WQE_ESEG_SIZE -\n+\t\t\t\t\t  MLX5_WQE_DSEG_SIZE * 2);\n \t} else if (inlen_mode) {\n \t\t/*\n \t\t * If minimal inlining is requested we must\n@@ -1102,12 +1101,12 @@ struct mlx5_txq_obj *\n \t\t\t\tPORT_ID(priv), inlen_empw, temp);\n \t\t\tinlen_empw = temp;\n \t\t}\n-\t\tassert(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);\n-\t\tassert(inlen_empw <= MLX5_WQE_SIZE_MAX +\n-\t\t\t\t     MLX5_DSEG_MIN_INLINE_SIZE -\n-\t\t\t\t     MLX5_WQE_CSEG_SIZE -\n-\t\t\t\t     MLX5_WQE_ESEG_SIZE -\n-\t\t\t\t     MLX5_WQE_DSEG_SIZE);\n+\t\tMLX5_ASSERT(inlen_empw >= MLX5_ESEG_MIN_INLINE_SIZE);\n+\t\tMLX5_ASSERT(inlen_empw <= MLX5_WQE_SIZE_MAX +\n+\t\t\t\t\t  MLX5_DSEG_MIN_INLINE_SIZE -\n+\t\t\t\t\t  MLX5_WQE_CSEG_SIZE -\n+\t\t\t\t\t  MLX5_WQE_ESEG_SIZE -\n+\t\t\t\t\t  MLX5_WQE_DSEG_SIZE);\n \t\ttxq_ctrl->txq.inlen_empw = inlen_empw;\n \t}\n \ttxq_ctrl->max_inline_data = RTE_MAX(inlen_send, inlen_empw);\n@@ -1222,11 +1221,11 @@ struct mlx5_txq_obj *\n \t}\n \ttxq_ctrl->max_inline_data = RTE_MAX(txq_ctrl->txq.inlen_send,\n \t\t\t\t\t    txq_ctrl->txq.inlen_empw);\n-\tassert(txq_ctrl->max_inline_data <= max_inline);\n-\tassert(txq_ctrl->txq.inlen_mode <= max_inline);\n-\tassert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);\n-\tassert(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||\n-\t       !txq_ctrl->txq.inlen_empw);\n+\tMLX5_ASSERT(txq_ctrl->max_inline_data <= max_inline);\n+\tMLX5_ASSERT(txq_ctrl->txq.inlen_mode <= max_inline);\n+\tMLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_send);\n+\tMLX5_ASSERT(txq_ctrl->txq.inlen_mode <= txq_ctrl->txq.inlen_empw ||\n+\t\t    !txq_ctrl->txq.inlen_empw);\n \treturn 0;\n error:\n \trte_errno = ENOMEM;\n@@ -1272,7 +1271,7 @@ struct mlx5_txq_ctrl *\n \t}\n \t/* Save pointer of global generation number to check memory event. */\n \ttmpl->txq.mr_ctrl.dev_gen_ptr = &priv->sh->mr.dev_gen;\n-\tassert(desc > MLX5_TX_COMP_THRESH);\n+\tMLX5_ASSERT(desc > MLX5_TX_COMP_THRESH);\n \ttmpl->txq.offloads = conf->offloads |\n \t\t\t     dev->data->dev_conf.txmode.offloads;\n \ttmpl->priv = priv;\ndiff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex 5d86615..4b4fc3c 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -49,7 +49,7 @@ struct mlx5_hlist_entry *\n \tstruct mlx5_hlist_head *first;\n \tstruct mlx5_hlist_entry *node;\n \n-\tassert(h);\n+\tMLX5_ASSERT(h);\n \tidx = rte_hash_crc_8byte(key, 0) & h->mask;\n \tfirst = &h->heads[idx];\n \tLIST_FOREACH(node, first, next) {\n@@ -66,7 +66,7 @@ struct mlx5_hlist_entry *\n \tstruct mlx5_hlist_head *first;\n \tstruct mlx5_hlist_entry *node;\n \n-\tassert(h && entry);\n+\tMLX5_ASSERT(h && entry);\n \tidx = rte_hash_crc_8byte(entry->key, 0) & h->mask;\n \tfirst = &h->heads[idx];\n \t/* No need to reuse the lookup function. */\n@@ -82,7 +82,7 @@ struct mlx5_hlist_entry *\n mlx5_hlist_remove(struct mlx5_hlist *h __rte_unused,\n \t\t  struct mlx5_hlist_entry *entry)\n {\n-\tassert(entry && entry->next.le_prev);\n+\tMLX5_ASSERT(entry && entry->next.le_prev);\n \tLIST_REMOVE(entry, next);\n \t/* Set to NULL to get rid of removing action for more than once. */\n \tentry->next.le_prev = NULL;\n@@ -95,7 +95,7 @@ struct mlx5_hlist_entry *\n \tuint32_t idx;\n \tstruct mlx5_hlist_entry *entry;\n \n-\tassert(h);\n+\tMLX5_ASSERT(h);\n \tfor (idx = 0; idx < h->table_sz; ++idx) {\n \t\t/* no LIST_FOREACH_SAFE, using while instead */\n \t\twhile (!LIST_EMPTY(&h->heads[idx])) {\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 8b12bce..ad03cdf 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -10,7 +10,6 @@\n #include <stdint.h>\n #include <stdio.h>\n #include <limits.h>\n-#include <assert.h>\n #include <errno.h>\n \n #include \"mlx5_defs.h\"\n@@ -32,17 +31,14 @@\n #define BITFIELD_DEFINE(bf, type, size) \\\n \tBITFIELD_DECLARE((bf), type, (size)) = { 0 }\n #define BITFIELD_SET(bf, b) \\\n-\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \\\n-\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \\\n-\t\t((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n+\t ((void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \\\n+\t\t ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n #define BITFIELD_RESET(bf, b) \\\n-\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \\\n-\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \\\n-\t\t~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n+\t ((void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \\\n+\t\t ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n #define BITFIELD_ISSET(bf, b) \\\n-\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \\\n-\t !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \\\n-\t     ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))\n+\t (!!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \\\n+\t      ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))\n \n /* Convert a bit number to the corresponding 64-bit mask */\n #define MLX5_BITSHIFT(v) (UINT64_C(1) << (v))\n@@ -114,12 +110,14 @@\n #ifdef MLX5_DEBUG\n \n #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)\n-#define claim_zero(...) assert((__VA_ARGS__) == 0)\n-#define claim_nonzero(...) assert((__VA_ARGS__) != 0)\n+#define MLX5_ASSERT(exp) RTE_VERIFY(exp)\n+#define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)\n+#define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)\n \n #else /* MLX5_DEBUG */\n \n #define DEBUG(...) (void)0\n+#define MLX5_ASSERT(exp) RTE_ASSERT(exp)\n #define claim_zero(...) (__VA_ARGS__)\n #define claim_nonzero(...) (__VA_ARGS__)\n \ndiff --git a/drivers/net/mlx5/mlx5_vlan.c b/drivers/net/mlx5/mlx5_vlan.c\nindex 5f6554a..e26e746 100644\n--- a/drivers/net/mlx5/mlx5_vlan.c\n+++ b/drivers/net/mlx5/mlx5_vlan.c\n@@ -5,7 +5,6 @@\n \n #include <stddef.h>\n #include <errno.h>\n-#include <assert.h>\n #include <stdint.h>\n \n /*\n@@ -54,7 +53,7 @@\n \n \tDRV_LOG(DEBUG, \"port %u %s VLAN filter ID %\" PRIu16,\n \t\tdev->data->port_id, (on ? \"enable\" : \"disable\"), vlan_id);\n-\tassert(priv->vlan_filter_n <= RTE_DIM(priv->vlan_filter));\n+\tMLX5_ASSERT(priv->vlan_filter_n <= RTE_DIM(priv->vlan_filter));\n \tfor (i = 0; (i != priv->vlan_filter_n); ++i)\n \t\tif (priv->vlan_filter[i] == vlan_id)\n \t\t\tbreak;\n@@ -64,7 +63,7 @@\n \t\treturn -rte_errno;\n \t}\n \tif (i < priv->vlan_filter_n) {\n-\t\tassert(priv->vlan_filter_n != 0);\n+\t\tMLX5_ASSERT(priv->vlan_filter_n != 0);\n \t\t/* Enabling an existing VLAN filter has no effect. */\n \t\tif (on)\n \t\t\tgoto out;\n@@ -76,7 +75,7 @@\n \t\t\t(priv->vlan_filter_n - i));\n \t\tpriv->vlan_filter[priv->vlan_filter_n] = 0;\n \t} else {\n-\t\tassert(i == priv->vlan_filter_n);\n+\t\tMLX5_ASSERT(i == priv->vlan_filter_n);\n \t\t/* Disabling an unknown VLAN filter has no effect. */\n \t\tif (!on)\n \t\t\tgoto out;\n",
    "prefixes": [
        "v2",
        "5/5"
    ]
}