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GET /api/patches/64955/?format=api
{ "id": 64955, "url": "http://patches.dpdk.org/api/patches/64955/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-18-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1579539790-3882-18-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1579539790-3882-18-git-send-email-matan@mellanox.com", "date": "2020-01-20T17:02:49", "name": "[v1,17/38] common/mlx5: add DevX virtio emulation commands", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "12e8be5cfac44e1b1da3016a5faae5494ba2cd58", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-18-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8223, "url": "http://patches.dpdk.org/api/series/8223/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8223", "date": "2020-01-20T17:02:37", "name": "Introduce mlx5 vDPA driver", "version": 1, "mbox": "http://patches.dpdk.org/series/8223/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64955/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64955/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 823C1A0526;\n\tMon, 20 Jan 2020 18:06:24 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 756B21C01F;\n\tMon, 20 Jan 2020 18:03:49 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 4503E1BFA1\n for <dev@dpdk.org>; Mon, 20 Jan 2020 18:03:14 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 20 Jan 2020 19:03:13 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00KH3BGa024424;\n Mon, 20 Jan 2020 19:03:13 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n Thomas Monjalon <thomas@monjalon.net>", "Date": "Mon, 20 Jan 2020 17:02:49 +0000", "Message-Id": "<1579539790-3882-18-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v1 17/38] common/mlx5: add DevX virtio emulation\n\tcommands", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Virtio emulation offload allows SW to offload the I/O operations of a\nvirtio virtqueue, using the device, allowing an improved performance\nfor its users.\nWhile supplying all the relevant Virtqueue information (type, size,\nmemory location, doorbell information, etc.). The device can then\noffload the I/O operation of this queue, according to its device type\ncharacteristics.\n\nSome of the virtio features can be supported according to the device\ncapability, for example, TSO and checksum.\n\nAdd virtio queue create, modify and query DevX commands.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 199 +++++++++++++++++++++---\n drivers/common/mlx5/mlx5_devx_cmds.h | 48 +++++-\n drivers/common/mlx5/mlx5_prm.h | 117 ++++++++++++++\n drivers/common/mlx5/rte_common_mlx5_version.map | 3 +\n 4 files changed, 343 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex ef7d70c..f843606 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -377,24 +377,18 @@ struct mlx5_devx_obj *\n \t\tvdpa_attr->max_num_virtio_queues =\n \t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n \t\t\t\t max_num_virtio_queues);\n-\t\tvdpa_attr->umem_1_buffer_param_a =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_1_buffer_param_a);\n-\t\tvdpa_attr->umem_1_buffer_param_b =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_1_buffer_param_b);\n-\t\tvdpa_attr->umem_2_buffer_param_a =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_2_buffer_param_a);\n-\t\tvdpa_attr->umem_2_buffer_param_b =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_2_buffer_param_a);\n-\t\tvdpa_attr->umem_3_buffer_param_a =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_3_buffer_param_a);\n-\t\tvdpa_attr->umem_3_buffer_param_b =\n-\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n-\t\t\t\t umem_3_buffer_param_b);\n+\t\tvdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_1_buffer_param_a);\n+\t\tvdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_1_buffer_param_b);\n+\t\tvdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_2_buffer_param_a);\n+\t\tvdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_2_buffer_param_b);\n+\t\tvdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_3_buffer_param_a);\n+\t\tvdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t umem_3_buffer_param_b);\n \t}\n }\n \n@@ -1148,3 +1142,172 @@ struct mlx5_devx_obj *\n \tcq_obj->id = MLX5_GET(create_cq_out, out, cqn);\n \treturn cq_obj;\n }\n+\n+/**\n+ * Create VIRTQ using DevX API.\n+ *\n+ * @param[in] ctx\n+ * ibv_context returned from mlx5dv_open_device.\n+ * @param [in] attr\n+ * Pointer to VIRTQ attributes structure.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,\n+\t\t\t struct mlx5_devx_virtq_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tstruct mlx5_devx_obj *virtq_obj = rte_zmalloc(__func__,\n+\t\t\t\t\t\t sizeof(*virtq_obj), 0);\n+\tvoid *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);\n+\tvoid *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);\n+\tvoid *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);\n+\n+\tif (!virtq_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate virtq data.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_VIRTQ);\n+\tMLX5_SET16(virtio_net_q, virtq, hw_available_index,\n+\t\t attr->hw_available_index);\n+\tMLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);\n+\tMLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);\n+\tMLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);\n+\tMLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);\n+\tMLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);\n+\tMLX5_SET16(virtio_q, virtctx, virtio_version_1_0,\n+\t\t attr->virtio_version_1_0);\n+\tMLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);\n+\tMLX5_SET(virtio_q, virtctx, event_cqn_or_msix, attr->cq_id);\n+\tMLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);\n+\tMLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);\n+\tMLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);\n+\tMLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);\n+\tMLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);\n+\tMLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);\n+\tMLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);\n+\tMLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);\n+\tMLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);\n+\tMLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);\n+\tMLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);\n+\tMLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);\n+\tMLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);\n+\tMLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);\n+\tMLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);\n+\tMLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);\n+\tvirtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n+\t\t\t\t\t\t sizeof(out));\n+\tif (!virtq_obj->obj) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create VIRTQ Obj using DevX.\");\n+\t\trte_free(virtq_obj);\n+\t\treturn NULL;\n+\t}\n+\tvirtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);\n+\treturn virtq_obj;\n+}\n+\n+/**\n+ * Modify VIRTQ using DevX API.\n+ *\n+ * @param[in] virtq_obj\n+ * Pointer to virtq object structure.\n+ * @param [in] attr\n+ * Pointer to modify virtq attributes structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,\n+\t\t\t struct mlx5_devx_virtq_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n+\tvoid *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);\n+\tvoid *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);\n+\tvoid *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);\n+\tint ret;\n+\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_VIRTQ);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);\n+\tMLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);\n+\tMLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);\n+\tswitch (attr->type) {\n+\tcase MLX5_VIRTQ_MODIFY_TYPE_STATE:\n+\t\tMLX5_SET16(virtio_net_q, virtq, state, attr->state);\n+\t\tbreak;\n+\tcase MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:\n+\t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,\n+\t\t\t attr->dirty_bitmap_mkey);\n+\t\tMLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,\n+\t\t\t attr->dirty_bitmap_addr);\n+\t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,\n+\t\t\t attr->dirty_bitmap_size);\n+\t\tbreak;\n+\tcase MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:\n+\t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,\n+\t\t\t attr->dirty_bitmap_dump_enable);\n+\t\tbreak;\n+\tdefault:\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to modify VIRTQ using DevX.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * Query VIRTQ using DevX API.\n+ *\n+ * @param[in] virtq_obj\n+ * Pointer to virtq object structure.\n+ * @param [in/out] attr\n+ * Pointer to virtq attributes structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,\n+\t\t\t struct mlx5_devx_virtq_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};\n+\tvoid *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);\n+\tvoid *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);\n+\tint ret;\n+\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n+\t\t MLX5_CMD_OP_QUERY_GENERAL_OBJECT);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n+\t\t MLX5_GENERAL_OBJ_TYPE_VIRTQ);\n+\tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);\n+\tret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to modify VIRTQ using DevX.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\tattr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,\n+\t\t\t\t\t hw_available_index);\n+\tattr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);\n+\treturn ret;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 7b50861..63c84f8 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -56,12 +56,10 @@ struct mlx5_hca_vdpa_attr {\n \tuint32_t log_doorbell_stride:5;\n \tuint32_t log_doorbell_bar_size:5;\n \tuint32_t max_num_virtio_queues;\n-\tuint32_t umem_1_buffer_param_a;\n-\tuint32_t umem_1_buffer_param_b;\n-\tuint32_t umem_2_buffer_param_a;\n-\tuint32_t umem_2_buffer_param_b;\n-\tuint32_t umem_3_buffer_param_a;\n-\tuint32_t umem_3_buffer_param_b;\n+\tstruct {\n+\t\tuint32_t a;\n+\t\tuint32_t b;\n+\t} umems[3];\n \tuint64_t doorbell_bar_offset;\n };\n \n@@ -241,6 +239,37 @@ struct mlx5_devx_cq_attr {\n \tuint64_t db_addr;\n };\n \n+/* Virtq attributes structure, used by VIRTQ operations. */\n+struct mlx5_devx_virtq_attr {\n+\tuint16_t hw_available_index;\n+\tuint16_t hw_used_index;\n+\tuint16_t q_size;\n+\tuint32_t virtio_version_1_0:1;\n+\tuint32_t tso_ipv4:1;\n+\tuint32_t tso_ipv6:1;\n+\tuint32_t tx_csum:1;\n+\tuint32_t rx_csum:1;\n+\tuint32_t event_mode:3;\n+\tuint32_t state:4;\n+\tuint32_t dirty_bitmap_dump_enable:1;\n+\tuint32_t dirty_bitmap_mkey;\n+\tuint32_t dirty_bitmap_size;\n+\tuint32_t mkey;\n+\tuint32_t cq_id;\n+\tuint32_t queue_index;\n+\tuint32_t tis_id;\n+\tuint64_t dirty_bitmap_addr;\n+\tuint64_t type;\n+\tuint64_t desc_addr;\n+\tuint64_t used_addr;\n+\tuint64_t available_addr;\n+\tstruct {\n+\t\tuint32_t id;\n+\t\tuint32_t size;\n+\t\tuint64_t offset;\n+\t} umems[3];\n+};\n+\n /* mlx5_devx_cmds.c */\n \n struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n@@ -279,4 +308,11 @@ int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,\n \t\t\t FILE *file);\n struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx,\n \t\t\t\t\t struct mlx5_devx_cq_attr *attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_virtq_attr *attr);\n+int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,\n+\t\t\t struct mlx5_devx_virtq_attr *attr);\n+int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,\n+\t\t\t struct mlx5_devx_virtq_attr *attr);\n+\n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 0206a8e..6db89bb 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -527,6 +527,8 @@ struct mlx5_modification_cmd {\n #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \\\n \t\t\t\t (__mlx5_bit_off(typ, fld) & 0xf))\n #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))\n+#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \\\n+\t\t\t\t __mlx5_16_bit_off(typ, fld))\n #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)\n #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)\n #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)\n@@ -551,6 +553,17 @@ struct mlx5_modification_cmd {\n \t\t\trte_cpu_to_be_64(v); \\\n \t} while (0)\n \n+#define MLX5_SET16(typ, p, fld, v) \\\n+\tdo { \\\n+\t\tu16 _v = v; \\\n+\t\t*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \\\n+\t\trte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \\\n+\t\t\t\t __mlx5_16_off(typ, fld))) & \\\n+\t\t\t\t (~__mlx5_16_mask(typ, fld))) | \\\n+\t\t\t\t (((_v) & __mlx5_mask16(typ, fld)) << \\\n+\t\t\t\t __mlx5_16_bit_off(typ, fld))); \\\n+\t} while (0)\n+\n #define MLX5_GET(typ, p, fld) \\\n \t((rte_be_to_cpu_32(*((__be32 *)(p) +\\\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n@@ -723,6 +736,9 @@ enum {\n \tMLX5_CMD_OP_CREATE_RQT = 0x916,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n+\tMLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,\n+\tMLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,\n+\tMLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,\n };\n \n enum {\n@@ -1689,6 +1705,11 @@ struct mlx5_ifc_create_tir_in_bits {\n \tstruct mlx5_ifc_tirc_bits ctx;\n };\n \n+enum {\n+\tMLX5_INLINE_Q_TYPE_RQ = 0x0,\n+\tMLX5_INLINE_Q_TYPE_VIRTQ = 0x1,\n+};\n+\n struct mlx5_ifc_rq_num_bits {\n \tu8 reserved_at_0[0x8];\n \tu8 rq_num[0x18];\n@@ -1915,6 +1936,102 @@ struct mlx5_ifc_create_cq_in_bits {\n \tu8 pas[];\n };\n \n+enum {\n+\tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n+};\n+\n+struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x20];\n+\tu8 obj_type[0x10];\n+\tu8 obj_id[0x20];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 obj_id[0x20];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+enum {\n+\tMLX5_VIRTQ_STATE_INIT = 0,\n+\tMLX5_VIRTQ_STATE_RDY = 1,\n+\tMLX5_VIRTQ_STATE_SUSPEND = 2,\n+\tMLX5_VIRTQ_STATE_ERROR = 3,\n+};\n+\n+enum {\n+\tMLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),\n+\tMLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),\n+\tMLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),\n+};\n+\n+struct mlx5_ifc_virtio_q_bits {\n+\tu8 virtio_q_type[0x8];\n+\tu8 reserved_at_8[0x5];\n+\tu8 event_mode[0x3];\n+\tu8 queue_index[0x10];\n+\tu8 full_emulation[0x1];\n+\tu8 virtio_version_1_0[0x1];\n+\tu8 reserved_at_22[0x2];\n+\tu8 offload_type[0x4];\n+\tu8 event_cqn_or_msix[0x18];\n+\tu8 doorbell_stride_idx[0x10];\n+\tu8 queue_size[0x10];\n+\tu8 device_emulation_id[0x20];\n+\tu8 desc_addr[0x40];\n+\tu8 used_addr[0x40];\n+\tu8 available_addr[0x40];\n+\tu8 virtio_q_mkey[0x20];\n+\tu8 reserved_at_160[0x20];\n+\tu8 umem_1_id[0x20];\n+\tu8 umem_1_size[0x20];\n+\tu8 umem_1_offset[0x40];\n+\tu8 umem_2_id[0x20];\n+\tu8 umem_2_size[0x20];\n+\tu8 umem_2_offset[0x40];\n+\tu8 umem_3_id[0x20];\n+\tu8 umem_3_size[0x20];\n+\tu8 umem_3_offset[0x40];\n+\tu8 reserved_at_300[0x100];\n+};\n+\n+struct mlx5_ifc_virtio_net_q_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x40];\n+\tu8 tso_ipv4[0x1];\n+\tu8 tso_ipv6[0x1];\n+\tu8 tx_csum[0x1];\n+\tu8 rx_csum[0x1];\n+\tu8 reserved_at_84[0x6];\n+\tu8 dirty_bitmap_dump_enable[0x1];\n+\tu8 vhost_log_page[0x5];\n+\tu8 reserved_at_90[0xc];\n+\tu8 state[0x4];\n+\tu8 error_type[0x8];\n+\tu8 tisn_or_qpn[0x18];\n+\tu8 dirty_bitmap_mkey[0x20];\n+\tu8 dirty_bitmap_size[0x20];\n+\tu8 dirty_bitmap_addr[0x40];\n+\tu8 hw_available_index[0x10];\n+\tu8 hw_used_index[0x10];\n+\tu8 reserved_at_160[0xa0];\n+\tstruct mlx5_ifc_virtio_q_bits virtio_q_context;\n+};\n+\n+struct mlx5_ifc_create_virtq_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_virtio_net_q_bits virtq;\n+};\n+\n+struct mlx5_ifc_query_virtq_out_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_virtio_net_q_bits virtq;\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex c6a203d..f3082ce 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -8,6 +8,7 @@ DPDK_20.02 {\n \tmlx5_devx_cmd_create_tir;\n \tmlx5_devx_cmd_create_td;\n \tmlx5_devx_cmd_create_tis;\n+\tmlx5_devx_cmd_create_virtq;\n \tmlx5_devx_cmd_destroy;\n \tmlx5_devx_cmd_flow_counter_alloc;\n \tmlx5_devx_cmd_flow_counter_query;\n@@ -15,8 +16,10 @@ DPDK_20.02 {\n \tmlx5_devx_cmd_mkey_create;\n \tmlx5_devx_cmd_modify_rq;\n \tmlx5_devx_cmd_modify_sq;\n+\tmlx5_devx_cmd_modify_virtq;\n \tmlx5_devx_cmd_qp_query_tis_td;\n \tmlx5_devx_cmd_query_hca_attr;\n+\tmlx5_devx_cmd_query_virtq;\n \tmlx5_devx_get_out_command_status;\n \n \tmlx5_dev_to_pci_addr;\n", "prefixes": [ "v1", "17/38" ] }