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GET /api/patches/64951/?format=api
{ "id": 64951, "url": "http://patches.dpdk.org/api/patches/64951/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-20-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1579539790-3882-20-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1579539790-3882-20-git-send-email-matan@mellanox.com", "date": "2020-01-20T17:02:51", "name": "[v1,19/38] mlx5: share CQ entry check", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a20c11094c01a5aaa8683d5750000ca9e9fac70f", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-20-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8223, "url": "http://patches.dpdk.org/api/series/8223/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8223", "date": "2020-01-20T17:02:37", "name": "Introduce mlx5 vDPA driver", "version": 1, "mbox": "http://patches.dpdk.org/series/8223/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64951/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 573EDA0526;\n\tMon, 20 Jan 2020 18:05:38 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A75981BFF3;\n\tMon, 20 Jan 2020 18:03:42 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 4BC111BFA3\n for <dev@dpdk.org>; Mon, 20 Jan 2020 18:03:14 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 20 Jan 2020 19:03:13 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00KH3BGc024424;\n Mon, 20 Jan 2020 19:03:13 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n Thomas Monjalon <thomas@monjalon.net>", "Date": "Mon, 20 Jan 2020 17:02:51 +0000", "Message-Id": "<1579539790-3882-20-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v1 19/38] mlx5: share CQ entry check", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The CQE has owner bit to indicate if it is in SW control or HW.\n\nShare a CQE check for all the mlx5 drivers.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_common.h | 41 +++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rxtx.h | 39 +------------------------------------\n 2 files changed, 42 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex 0f57a27..9d464d4 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -9,8 +9,11 @@\n #include <stdio.h>\n \n #include <rte_pci.h>\n+#include <rte_atomic.h>\n #include <rte_log.h>\n \n+#include \"mlx5_prm.h\"\n+\n \n /*\n * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant\n@@ -107,6 +110,44 @@ enum {\n \tPCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,\n };\n \n+/* CQE status. */\n+enum mlx5_cqe_status {\n+\tMLX5_CQE_STATUS_SW_OWN = -1,\n+\tMLX5_CQE_STATUS_HW_OWN = -2,\n+\tMLX5_CQE_STATUS_ERR = -3,\n+};\n+\n+/**\n+ * Check whether CQE is valid.\n+ *\n+ * @param cqe\n+ * Pointer to CQE.\n+ * @param cqes_n\n+ * Size of completion queue.\n+ * @param ci\n+ * Consumer index.\n+ *\n+ * @return\n+ * The CQE status.\n+ */\n+static __rte_always_inline enum mlx5_cqe_status\n+check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,\n+\t const uint16_t ci)\n+{\n+\tconst uint16_t idx = ci & cqes_n;\n+\tconst uint8_t op_own = cqe->op_own;\n+\tconst uint8_t op_owner = MLX5_CQE_OWNER(op_own);\n+\tconst uint8_t op_code = MLX5_CQE_OPCODE(op_own);\n+\n+\tif (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))\n+\t\treturn MLX5_CQE_STATUS_HW_OWN;\n+\trte_cio_rmb();\n+\tif (unlikely(op_code == MLX5_CQE_RESP_ERR ||\n+\t\t op_code == MLX5_CQE_REQ_ERR))\n+\t\treturn MLX5_CQE_STATUS_ERR;\n+\treturn MLX5_CQE_STATUS_SW_OWN;\n+}\n+\n int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);\n \n #endif /* RTE_PMD_MLX5_COMMON_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 84b1fce..9242497 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -33,6 +33,7 @@\n \n #include <mlx5_glue.h>\n #include <mlx5_prm.h>\n+#include <mlx5_common.h>\n \n #include \"mlx5_defs.h\"\n #include \"mlx5_utils.h\"\n@@ -549,44 +550,6 @@ int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,\n #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)\n #endif\n \n-/* CQE status. */\n-enum mlx5_cqe_status {\n-\tMLX5_CQE_STATUS_SW_OWN = -1,\n-\tMLX5_CQE_STATUS_HW_OWN = -2,\n-\tMLX5_CQE_STATUS_ERR = -3,\n-};\n-\n-/**\n- * Check whether CQE is valid.\n- *\n- * @param cqe\n- * Pointer to CQE.\n- * @param cqes_n\n- * Size of completion queue.\n- * @param ci\n- * Consumer index.\n- *\n- * @return\n- * The CQE status.\n- */\n-static __rte_always_inline enum mlx5_cqe_status\n-check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,\n-\t const uint16_t ci)\n-{\n-\tconst uint16_t idx = ci & cqes_n;\n-\tconst uint8_t op_own = cqe->op_own;\n-\tconst uint8_t op_owner = MLX5_CQE_OWNER(op_own);\n-\tconst uint8_t op_code = MLX5_CQE_OPCODE(op_own);\n-\n-\tif (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))\n-\t\treturn MLX5_CQE_STATUS_HW_OWN;\n-\trte_cio_rmb();\n-\tif (unlikely(op_code == MLX5_CQE_RESP_ERR ||\n-\t\t op_code == MLX5_CQE_REQ_ERR))\n-\t\treturn MLX5_CQE_STATUS_ERR;\n-\treturn MLX5_CQE_STATUS_SW_OWN;\n-}\n-\n /**\n * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the\n * cloned mbuf is allocated is returned instead.\n", "prefixes": [ "v1", "19/38" ] }