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GET /api/patches/64943/?format=api
{ "id": 64943, "url": "http://patches.dpdk.org/api/patches/64943/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-8-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1579539790-3882-8-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1579539790-3882-8-git-send-email-matan@mellanox.com", "date": "2020-01-20T17:02:39", "name": "[v1,07/38] common/mlx5: expose vDPA DevX capabilities", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ce7f541bbe6e2ea450d654875760d1ea6c399754", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-8-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8223, "url": "http://patches.dpdk.org/api/series/8223/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8223", "date": "2020-01-20T17:02:37", "name": "Introduce mlx5 vDPA driver", "version": 1, "mbox": "http://patches.dpdk.org/series/8223/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64943/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64943/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32F5BA0526;\n\tMon, 20 Jan 2020 18:04:08 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2F6BE1BFB5;\n\tMon, 20 Jan 2020 18:03:28 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 152831BF80\n for <dev@dpdk.org>; Mon, 20 Jan 2020 18:03:13 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 20 Jan 2020 19:03:12 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00KH3BGQ024424;\n Mon, 20 Jan 2020 19:03:12 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n Thomas Monjalon <thomas@monjalon.net>", "Date": "Mon, 20 Jan 2020 17:02:39 +0000", "Message-Id": "<1579539790-3882-8-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v1 07/38] common/mlx5: expose vDPA DevX\n\tcapabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the DevX capabilities for vDPA configuration and information of\nMellanox devices.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 90 ++++++++++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 24 ++++++++++\n drivers/common/mlx5/mlx5_prm.h | 45 ++++++++++++++++++\n 3 files changed, 159 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 67e5929..c6965da 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -285,6 +285,91 @@ struct mlx5_devx_obj *\n }\n \n /**\n+ * Query NIC vDPA attributes.\n+ *\n+ * @param[in] ctx\n+ * ibv contexts returned from mlx5dv_open_device.\n+ * @param[out] vdpa_attr\n+ * vDPA Attributes structure to fill.\n+ */\n+static void\n+mlx5_devx_cmd_query_hca_vdpa_attr(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5_hca_vdpa_attr *vdpa_attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};\n+\tvoid *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n+\tint status, syndrome, rc;\n+\n+\tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\tstatus = MLX5_GET(query_hca_cap_out, out, status);\n+\tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n+\tif (rc || status) {\n+\t\tRTE_LOG(DEBUG, PMD, \"Failed to query devx VDPA capabilities,\"\n+\t\t\t\" status %x, syndrome = %x\", status, syndrome);\n+\t\tvdpa_attr->valid = 0;\n+\t} else {\n+\t\tvdpa_attr->valid = 1;\n+\t\tvdpa_attr->desc_tunnel_offload_type =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t desc_tunnel_offload_type);\n+\t\tvdpa_attr->eth_frame_offload_type =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t eth_frame_offload_type);\n+\t\tvdpa_attr->virtio_version_1_0 =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t virtio_version_1_0);\n+\t\tvdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t tso_ipv4);\n+\t\tvdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t tso_ipv6);\n+\t\tvdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t tx_csum);\n+\t\tvdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t rx_csum);\n+\t\tvdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t\t\t event_mode);\n+\t\tvdpa_attr->virtio_queue_type =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t virtio_queue_type);\n+\t\tvdpa_attr->log_doorbell_stride =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t log_doorbell_stride);\n+\t\tvdpa_attr->log_doorbell_bar_size =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t log_doorbell_bar_size);\n+\t\tvdpa_attr->doorbell_bar_offset =\n+\t\t\tMLX5_GET64(virtio_emulation_cap, hcattr,\n+\t\t\t\t doorbell_bar_offset);\n+\t\tvdpa_attr->max_num_virtio_queues =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t max_num_virtio_queues);\n+\t\tvdpa_attr->umem_1_buffer_param_a =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_1_buffer_param_a);\n+\t\tvdpa_attr->umem_1_buffer_param_b =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_1_buffer_param_b);\n+\t\tvdpa_attr->umem_2_buffer_param_a =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_2_buffer_param_a);\n+\t\tvdpa_attr->umem_2_buffer_param_b =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_2_buffer_param_a);\n+\t\tvdpa_attr->umem_3_buffer_param_a =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_3_buffer_param_a);\n+\t\tvdpa_attr->umem_3_buffer_param_b =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t umem_3_buffer_param_b);\n+\t}\n+}\n+\n+/**\n * Query HCA attributes.\n * Using those attributes we can check on run time if the device\n * is having the required capabilities.\n@@ -343,6 +428,9 @@ struct mlx5_devx_obj *\n \tattr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t flex_parser_protocols);\n \tattr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);\n+\tattr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\n@@ -365,6 +453,8 @@ struct mlx5_devx_obj *\n \t\tattr->qos.flow_meter_reg_c_ids =\n \t\t\tMLX5_GET(qos_cap, hcattr, flow_meter_reg_id);\n \t}\n+\tif (attr->vdpa.valid)\n+\t\tmlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);\n \tif (!attr->eth_net_offloads)\n \t\treturn 0;\n \ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 0c5afde..dea1597 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -31,6 +31,29 @@ struct mlx5_hca_qos_attr {\n \n };\n \n+struct mlx5_hca_vdpa_attr {\n+\tuint8_t virtio_queue_type;\n+\tuint32_t valid:1;\n+\tuint32_t desc_tunnel_offload_type:1;\n+\tuint32_t eth_frame_offload_type:1;\n+\tuint32_t virtio_version_1_0:1;\n+\tuint32_t tso_ipv4:1;\n+\tuint32_t tso_ipv6:1;\n+\tuint32_t tx_csum:1;\n+\tuint32_t rx_csum:1;\n+\tuint32_t event_mode:3;\n+\tuint32_t log_doorbell_stride:5;\n+\tuint32_t log_doorbell_bar_size:5;\n+\tuint32_t max_num_virtio_queues;\n+\tuint32_t umem_1_buffer_param_a;\n+\tuint32_t umem_1_buffer_param_b;\n+\tuint32_t umem_2_buffer_param_a;\n+\tuint32_t umem_2_buffer_param_b;\n+\tuint32_t umem_3_buffer_param_a;\n+\tuint32_t umem_3_buffer_param_b;\n+\tuint64_t doorbell_bar_offset;\n+};\n+\n /* HCA supports this number of time periods for LRO. */\n #define MLX5_LRO_NUM_SUPP_PERIODS 4\n \n@@ -58,6 +81,7 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_hairpin_num_packets:5;\n \tuint32_t vhca_id:16;\n \tstruct mlx5_hca_qos_attr qos;\n+\tstruct mlx5_hca_vdpa_attr vdpa;\n };\n \n struct mlx5_devx_wq_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4b521b2..b0b8ab9 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -881,6 +881,11 @@ enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,\n \tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,\n+};\n+\n+enum {\n+\tMLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),\n };\n \n enum {\n@@ -1254,11 +1259,51 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 reserved_at_200[0x600];\n };\n \n+enum {\n+\tMLX5_VIRTQ_TYPE_SPLIT = 0,\n+\tMLX5_VIRTQ_TYPE_PACKED = 1,\n+};\n+\n+enum {\n+\tMLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,\n+\tMLX5_VIRTQ_EVENT_MODE_CQ = 1,\n+\tMLX5_VIRTQ_EVENT_MODE_MSIX = 2,\n+};\n+\n+struct mlx5_ifc_virtio_emulation_cap_bits {\n+\tu8 desc_tunnel_offload_type[0x1];\n+\tu8 eth_frame_offload_type[0x1];\n+\tu8 virtio_version_1_0[0x1];\n+\tu8 tso_ipv4[0x1];\n+\tu8 tso_ipv6[0x1];\n+\tu8 tx_csum[0x1];\n+\tu8 rx_csum[0x1];\n+\tu8 reserved_at_7[0x1][0x9];\n+\tu8 event_mode[0x8];\n+\tu8 virtio_queue_type[0x8];\n+\tu8 reserved_at_20[0x13];\n+\tu8 log_doorbell_stride[0x5];\n+\tu8 reserved_at_3b[0x3];\n+\tu8 log_doorbell_bar_size[0x5];\n+\tu8 doorbell_bar_offset[0x40];\n+\tu8 reserved_at_80[0x8];\n+\tu8 max_num_virtio_queues[0x18];\n+\tu8 reserved_at_a0[0x60];\n+\tu8 umem_1_buffer_param_a[0x20];\n+\tu8 umem_1_buffer_param_b[0x20];\n+\tu8 umem_2_buffer_param_a[0x20];\n+\tu8 umem_2_buffer_param_b[0x20];\n+\tu8 umem_3_buffer_param_a[0x20];\n+\tu8 umem_3_buffer_param_b[0x20];\n+\tu8 reserved_at_1c0[0x620];\n+};\n+\n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n \tstruct mlx5_ifc_per_protocol_networking_offload_caps_bits\n \t per_protocol_networking_offload_caps;\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n+\tstruct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;\n \tu8 reserved_at_0[0x8000];\n };\n \n", "prefixes": [ "v1", "07/38" ] }