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GET /api/patches/64941/?format=api
{ "id": 64941, "url": "http://patches.dpdk.org/api/patches/64941/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-2-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1579539790-3882-2-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1579539790-3882-2-git-send-email-matan@mellanox.com", "date": "2020-01-20T17:02:33", "name": "[v1,01/38] net/mlx5: separate DevX commands interface", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fdeb1b89efe3f7f6b9e0b1269cab29d2b2ae52b8", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-2-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8223, "url": "http://patches.dpdk.org/api/series/8223/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8223", "date": "2020-01-20T17:02:37", "name": "Introduce mlx5 vDPA driver", "version": 1, "mbox": "http://patches.dpdk.org/series/8223/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64941/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64941/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E6BA2A0526;\n\tMon, 20 Jan 2020 18:03:45 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 441091BFA6;\n\tMon, 20 Jan 2020 18:03:24 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id F34121BEB2\n for <dev@dpdk.org>; Mon, 20 Jan 2020 18:03:13 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 20 Jan 2020 19:03:12 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00KH3BGK024424;\n Mon, 20 Jan 2020 19:03:12 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n Thomas Monjalon <thomas@monjalon.net>", "Date": "Mon, 20 Jan 2020 17:02:33 +0000", "Message-Id": "<1579539790-3882-2-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v1 01/38] net/mlx5: separate DevX commands\n\tinterface", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The DevX commands interfaces is included in the mlx5.h file with a lot\nof other PMD interfaces.\n\nAs an arrangement to make the DevX commands shared with different PMDs,\nthis patch moves the DevX interface to a new file called mlx5_devx_cmds.h.\n\nAlso remove shared device structure dependency from DevX commands.\n\nReplace the DevX commands log mechanism from the mlx5 driver log\nmechanism to the EAL log mechanism.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 1 +\n drivers/net/mlx5/mlx5.h | 219 +-----------------------------------\n drivers/net/mlx5/mlx5_devx_cmds.c | 33 +++---\n drivers/net/mlx5/mlx5_devx_cmds.h | 227 ++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_ethdev.c | 1 +\n drivers/net/mlx5/mlx5_flow.c | 5 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 1 +\n drivers/net/mlx5/mlx5_rxq.c | 1 +\n drivers/net/mlx5/mlx5_rxtx.c | 1 +\n drivers/net/mlx5/mlx5_txq.c | 1 +\n drivers/net/mlx5/mlx5_vlan.c | 1 +\n 11 files changed, 259 insertions(+), 232 deletions(-)\n create mode 100644 drivers/net/mlx5/mlx5_devx_cmds.h", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex ffee39c..2f91e50 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -46,6 +46,7 @@\n #include \"mlx5_glue.h\"\n #include \"mlx5_mr.h\"\n #include \"mlx5_flow.h\"\n+#include \"mlx5_devx_cmds.h\"\n \n /* Device parameter to enable RX completion queue compression. */\n #define MLX5_RXQ_CQE_COMP_EN \"rxq_cqe_comp_en\"\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 01542e7..0b8b1b6 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -38,6 +38,7 @@\n #include \"mlx5_defs.h\"\n #include \"mlx5_glue.h\"\n #include \"mlx5_prm.h\"\n+#include \"mlx5_devx_cmds.h\"\n \n enum {\n \tPCI_VENDOR_ID_MELLANOX = 0x15b3,\n@@ -156,60 +157,6 @@ struct mlx5_stats_ctrl {\n \tuint64_t imissed_base;\n };\n \n-/* devX creation object */\n-struct mlx5_devx_obj {\n-\tstruct mlx5dv_devx_obj *obj; /* The DV object. */\n-\tint id; /* The object ID. */\n-};\n-\n-struct mlx5_devx_mkey_attr {\n-\tuint64_t addr;\n-\tuint64_t size;\n-\tuint32_t umem_id;\n-\tuint32_t pd;\n-};\n-\n-/* HCA qos attributes. */\n-struct mlx5_hca_qos_attr {\n-\tuint32_t sup:1;\t/* Whether QOS is supported. */\n-\tuint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */\n-\tuint8_t log_max_flow_meter;\n-\t/* Power of the maximum supported meters. */\n-\tuint8_t flow_meter_reg_c_ids;\n-\t/* Bitmap of the reg_Cs available for flow meter to use. */\n-\n-};\n-\n-/* HCA supports this number of time periods for LRO. */\n-#define MLX5_LRO_NUM_SUPP_PERIODS 4\n-\n-/* HCA attributes. */\n-struct mlx5_hca_attr {\n-\tuint32_t eswitch_manager:1;\n-\tuint32_t flow_counters_dump:1;\n-\tuint8_t flow_counter_bulk_alloc_bitmap;\n-\tuint32_t eth_net_offloads:1;\n-\tuint32_t eth_virt:1;\n-\tuint32_t wqe_vlan_insert:1;\n-\tuint32_t wqe_inline_mode:2;\n-\tuint32_t vport_inline_mode:3;\n-\tuint32_t tunnel_stateless_geneve_rx:1;\n-\tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n-\tuint32_t tunnel_stateless_gtp:1;\n-\tuint32_t lro_cap:1;\n-\tuint32_t tunnel_lro_gre:1;\n-\tuint32_t tunnel_lro_vxlan:1;\n-\tuint32_t lro_max_msg_sz_mode:2;\n-\tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n-\tuint32_t flex_parser_protocols;\n-\tuint32_t hairpin:1;\n-\tuint32_t log_max_hairpin_queues:5;\n-\tuint32_t log_max_hairpin_wq_data_sz:5;\n-\tuint32_t log_max_hairpin_num_packets:5;\n-\tuint32_t vhca_id:16;\n-\tstruct mlx5_hca_qos_attr qos;\n-};\n-\n /* Flow list . */\n TAILQ_HEAD(mlx5_flows, rte_flow);\n \n@@ -289,133 +236,6 @@ struct mlx5_dev_config {\n \tstruct mlx5_lro_config lro; /* LRO configuration. */\n };\n \n-struct mlx5_devx_wq_attr {\n-\tuint32_t wq_type:4;\n-\tuint32_t wq_signature:1;\n-\tuint32_t end_padding_mode:2;\n-\tuint32_t cd_slave:1;\n-\tuint32_t hds_skip_first_sge:1;\n-\tuint32_t log2_hds_buf_size:3;\n-\tuint32_t page_offset:5;\n-\tuint32_t lwm:16;\n-\tuint32_t pd:24;\n-\tuint32_t uar_page:24;\n-\tuint64_t dbr_addr;\n-\tuint32_t hw_counter;\n-\tuint32_t sw_counter;\n-\tuint32_t log_wq_stride:4;\n-\tuint32_t log_wq_pg_sz:5;\n-\tuint32_t log_wq_sz:5;\n-\tuint32_t dbr_umem_valid:1;\n-\tuint32_t wq_umem_valid:1;\n-\tuint32_t log_hairpin_num_packets:5;\n-\tuint32_t log_hairpin_data_sz:5;\n-\tuint32_t single_wqe_log_num_of_strides:4;\n-\tuint32_t two_byte_shift_en:1;\n-\tuint32_t single_stride_log_num_of_bytes:3;\n-\tuint32_t dbr_umem_id;\n-\tuint32_t wq_umem_id;\n-\tuint64_t wq_umem_offset;\n-};\n-\n-/* Create RQ attributes structure, used by create RQ operation. */\n-struct mlx5_devx_create_rq_attr {\n-\tuint32_t rlky:1;\n-\tuint32_t delay_drop_en:1;\n-\tuint32_t scatter_fcs:1;\n-\tuint32_t vsd:1;\n-\tuint32_t mem_rq_type:4;\n-\tuint32_t state:4;\n-\tuint32_t flush_in_error_en:1;\n-\tuint32_t hairpin:1;\n-\tuint32_t user_index:24;\n-\tuint32_t cqn:24;\n-\tuint32_t counter_set_id:8;\n-\tuint32_t rmpn:24;\n-\tstruct mlx5_devx_wq_attr wq_attr;\n-};\n-\n-/* Modify RQ attributes structure, used by modify RQ operation. */\n-struct mlx5_devx_modify_rq_attr {\n-\tuint32_t rqn:24;\n-\tuint32_t rq_state:4; /* Current RQ state. */\n-\tuint32_t state:4; /* Required RQ state. */\n-\tuint32_t scatter_fcs:1;\n-\tuint32_t vsd:1;\n-\tuint32_t counter_set_id:8;\n-\tuint32_t hairpin_peer_sq:24;\n-\tuint32_t hairpin_peer_vhca:16;\n-\tuint64_t modify_bitmask;\n-\tuint32_t lwm:16; /* Contained WQ lwm. */\n-};\n-\n-struct mlx5_rx_hash_field_select {\n-\tuint32_t l3_prot_type:1;\n-\tuint32_t l4_prot_type:1;\n-\tuint32_t selected_fields:30;\n-};\n-\n-/* TIR attributes structure, used by TIR operations. */\n-struct mlx5_devx_tir_attr {\n-\tuint32_t disp_type:4;\n-\tuint32_t lro_timeout_period_usecs:16;\n-\tuint32_t lro_enable_mask:4;\n-\tuint32_t lro_max_msg_sz:8;\n-\tuint32_t inline_rqn:24;\n-\tuint32_t rx_hash_symmetric:1;\n-\tuint32_t tunneled_offload_en:1;\n-\tuint32_t indirect_table:24;\n-\tuint32_t rx_hash_fn:4;\n-\tuint32_t self_lb_block:2;\n-\tuint32_t transport_domain:24;\n-\tuint32_t rx_hash_toeplitz_key[10];\n-\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_outer;\n-\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_inner;\n-};\n-\n-/* RQT attributes structure, used by RQT operations. */\n-struct mlx5_devx_rqt_attr {\n-\tuint32_t rqt_max_size:16;\n-\tuint32_t rqt_actual_size:16;\n-\tuint32_t rq_list[];\n-};\n-\n-/* TIS attributes structure. */\n-struct mlx5_devx_tis_attr {\n-\tuint32_t strict_lag_tx_port_affinity:1;\n-\tuint32_t tls_en:1;\n-\tuint32_t lag_tx_port_affinity:4;\n-\tuint32_t prio:4;\n-\tuint32_t transport_domain:24;\n-};\n-\n-/* SQ attributes structure, used by SQ create operation. */\n-struct mlx5_devx_create_sq_attr {\n-\tuint32_t rlky:1;\n-\tuint32_t cd_master:1;\n-\tuint32_t fre:1;\n-\tuint32_t flush_in_error_en:1;\n-\tuint32_t allow_multi_pkt_send_wqe:1;\n-\tuint32_t min_wqe_inline_mode:3;\n-\tuint32_t state:4;\n-\tuint32_t reg_umr:1;\n-\tuint32_t allow_swp:1;\n-\tuint32_t hairpin:1;\n-\tuint32_t user_index:24;\n-\tuint32_t cqn:24;\n-\tuint32_t packet_pacing_rate_limit_index:16;\n-\tuint32_t tis_lst_sz:16;\n-\tuint32_t tis_num:24;\n-\tstruct mlx5_devx_wq_attr wq_attr;\n-};\n-\n-/* SQ attributes structure, used by SQ modify operation. */\n-struct mlx5_devx_modify_sq_attr {\n-\tuint32_t sq_state:4;\n-\tuint32_t state:4;\n-\tuint32_t hairpin_peer_rq:24;\n-\tuint32_t hairpin_peer_vhca:16;\n-};\n \n /**\n * Type of object being allocated.\n@@ -1022,43 +842,6 @@ void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,\n void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_vf_vlan *vf_vlan);\n \n-/* mlx5_devx_cmds.c */\n-\n-struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n-\t\t\t\t\t\t uint32_t bulk_sz);\n-int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);\n-int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,\n-\t\t\t\t int clear, uint32_t n_counters,\n-\t\t\t\t uint64_t *pkts, uint64_t *bytes,\n-\t\t\t\t uint32_t mkey, void *addr,\n-\t\t\t\t struct mlx5dv_devx_cmd_comp *cmd_comp,\n-\t\t\t\t uint64_t async_id);\n-int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,\n-\t\t\t\t struct mlx5_hca_attr *attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,\n-\t\t\t\t\t struct mlx5_devx_mkey_attr *attr);\n-int mlx5_devx_get_out_command_status(void *out);\n-int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,\n-\t\t\t\t uint32_t *tis_td);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,\n-\t\t\t\tstruct mlx5_devx_create_rq_attr *rq_attr,\n-\t\t\t\tint socket);\n-int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,\n-\t\t\t struct mlx5_devx_modify_rq_attr *rq_attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,\n-\t\t\t\t\tstruct mlx5_devx_tir_attr *tir_attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,\n-\t\t\t\t\tstruct mlx5_devx_rqt_attr *rqt_attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_sq\n-\t(struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);\n-int mlx5_devx_cmd_modify_sq\n-\t(struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_tis\n-\t(struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);\n-struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);\n-\n-int mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh, FILE *file);\n-\n /* mlx5_flow_meter.c */\n \n int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex 9985d30..1302919 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -1,13 +1,15 @@\n // SPDX-License-Identifier: BSD-3-Clause\n /* Copyright 2018 Mellanox Technologies, Ltd */\n \n+#include <unistd.h>\n+\n #include <rte_flow_driver.h>\n #include <rte_malloc.h>\n-#include <unistd.h>\n \n-#include \"mlx5.h\"\n-#include \"mlx5_glue.h\"\n #include \"mlx5_prm.h\"\n+#include \"mlx5_devx_cmds.h\"\n+#include \"mlx5_utils.h\"\n+\n \n /**\n * Allocate flow counters via devx interface.\n@@ -934,8 +936,12 @@ struct mlx5_devx_obj *\n /**\n * Dump all flows to file.\n *\n- * @param[in] sh\n- * Pointer to context.\n+ * @param[in] fdb_domain\n+ * FDB domain.\n+ * @param[in] rx_domain\n+ * RX domain.\n+ * @param[in] tx_domain\n+ * TX domain.\n * @param[out] file\n * Pointer to file stream.\n *\n@@ -943,23 +949,24 @@ struct mlx5_devx_obj *\n * 0 on success, a nagative value otherwise.\n */\n int\n-mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh __rte_unused,\n-\t\t\tFILE *file __rte_unused)\n+mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,\n+\t\t\tvoid *rx_domain __rte_unused,\n+\t\t\tvoid *tx_domain __rte_unused, FILE *file __rte_unused)\n {\n \tint ret = 0;\n \n #ifdef HAVE_MLX5_DR_FLOW_DUMP\n-\tif (sh->fdb_domain) {\n-\t\tret = mlx5_glue->dr_dump_domain(file, sh->fdb_domain);\n+\tif (fdb_domain) {\n+\t\tret = mlx5_glue->dr_dump_domain(file, fdb_domain);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n-\tassert(sh->rx_domain);\n-\tret = mlx5_glue->dr_dump_domain(file, sh->rx_domain);\n+\tassert(rx_domain);\n+\tret = mlx5_glue->dr_dump_domain(file, rx_domain);\n \tif (ret)\n \t\treturn ret;\n-\tassert(sh->tx_domain);\n-\tret = mlx5_glue->dr_dump_domain(file, sh->tx_domain);\n+\tassert(tx_domain);\n+\tret = mlx5_glue->dr_dump_domain(file, tx_domain);\n #else\n \tret = ENOTSUP;\n #endif\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.h b/drivers/net/mlx5/mlx5_devx_cmds.h\nnew file mode 100644\nindex 0000000..0c5afde\n--- /dev/null\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.h\n@@ -0,0 +1,227 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef RTE_PMD_MLX5_DEVX_CMDS_H_\n+#define RTE_PMD_MLX5_DEVX_CMDS_H_\n+\n+#include \"mlx5_glue.h\"\n+\n+/* devX creation object */\n+struct mlx5_devx_obj {\n+\tstruct mlx5dv_devx_obj *obj; /* The DV object. */\n+\tint id; /* The object ID. */\n+};\n+\n+struct mlx5_devx_mkey_attr {\n+\tuint64_t addr;\n+\tuint64_t size;\n+\tuint32_t umem_id;\n+\tuint32_t pd;\n+};\n+\n+/* HCA qos attributes. */\n+struct mlx5_hca_qos_attr {\n+\tuint32_t sup:1;\t/* Whether QOS is supported. */\n+\tuint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */\n+\tuint8_t log_max_flow_meter;\n+\t/* Power of the maximum supported meters. */\n+\tuint8_t flow_meter_reg_c_ids;\n+\t/* Bitmap of the reg_Cs available for flow meter to use. */\n+\n+};\n+\n+/* HCA supports this number of time periods for LRO. */\n+#define MLX5_LRO_NUM_SUPP_PERIODS 4\n+\n+struct mlx5_hca_attr {\n+\tuint32_t eswitch_manager:1;\n+\tuint32_t flow_counters_dump:1;\n+\tuint8_t flow_counter_bulk_alloc_bitmap;\n+\tuint32_t eth_net_offloads:1;\n+\tuint32_t eth_virt:1;\n+\tuint32_t wqe_vlan_insert:1;\n+\tuint32_t wqe_inline_mode:2;\n+\tuint32_t vport_inline_mode:3;\n+\tuint32_t tunnel_stateless_geneve_rx:1;\n+\tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n+\tuint32_t tunnel_stateless_gtp:1;\n+\tuint32_t lro_cap:1;\n+\tuint32_t tunnel_lro_gre:1;\n+\tuint32_t tunnel_lro_vxlan:1;\n+\tuint32_t lro_max_msg_sz_mode:2;\n+\tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n+\tuint32_t flex_parser_protocols;\n+\tuint32_t hairpin:1;\n+\tuint32_t log_max_hairpin_queues:5;\n+\tuint32_t log_max_hairpin_wq_data_sz:5;\n+\tuint32_t log_max_hairpin_num_packets:5;\n+\tuint32_t vhca_id:16;\n+\tstruct mlx5_hca_qos_attr qos;\n+};\n+\n+struct mlx5_devx_wq_attr {\n+\tuint32_t wq_type:4;\n+\tuint32_t wq_signature:1;\n+\tuint32_t end_padding_mode:2;\n+\tuint32_t cd_slave:1;\n+\tuint32_t hds_skip_first_sge:1;\n+\tuint32_t log2_hds_buf_size:3;\n+\tuint32_t page_offset:5;\n+\tuint32_t lwm:16;\n+\tuint32_t pd:24;\n+\tuint32_t uar_page:24;\n+\tuint64_t dbr_addr;\n+\tuint32_t hw_counter;\n+\tuint32_t sw_counter;\n+\tuint32_t log_wq_stride:4;\n+\tuint32_t log_wq_pg_sz:5;\n+\tuint32_t log_wq_sz:5;\n+\tuint32_t dbr_umem_valid:1;\n+\tuint32_t wq_umem_valid:1;\n+\tuint32_t log_hairpin_num_packets:5;\n+\tuint32_t log_hairpin_data_sz:5;\n+\tuint32_t single_wqe_log_num_of_strides:4;\n+\tuint32_t two_byte_shift_en:1;\n+\tuint32_t single_stride_log_num_of_bytes:3;\n+\tuint32_t dbr_umem_id;\n+\tuint32_t wq_umem_id;\n+\tuint64_t wq_umem_offset;\n+};\n+\n+/* Create RQ attributes structure, used by create RQ operation. */\n+struct mlx5_devx_create_rq_attr {\n+\tuint32_t rlky:1;\n+\tuint32_t delay_drop_en:1;\n+\tuint32_t scatter_fcs:1;\n+\tuint32_t vsd:1;\n+\tuint32_t mem_rq_type:4;\n+\tuint32_t state:4;\n+\tuint32_t flush_in_error_en:1;\n+\tuint32_t hairpin:1;\n+\tuint32_t user_index:24;\n+\tuint32_t cqn:24;\n+\tuint32_t counter_set_id:8;\n+\tuint32_t rmpn:24;\n+\tstruct mlx5_devx_wq_attr wq_attr;\n+};\n+\n+/* Modify RQ attributes structure, used by modify RQ operation. */\n+struct mlx5_devx_modify_rq_attr {\n+\tuint32_t rqn:24;\n+\tuint32_t rq_state:4; /* Current RQ state. */\n+\tuint32_t state:4; /* Required RQ state. */\n+\tuint32_t scatter_fcs:1;\n+\tuint32_t vsd:1;\n+\tuint32_t counter_set_id:8;\n+\tuint32_t hairpin_peer_sq:24;\n+\tuint32_t hairpin_peer_vhca:16;\n+\tuint64_t modify_bitmask;\n+\tuint32_t lwm:16; /* Contained WQ lwm. */\n+};\n+\n+struct mlx5_rx_hash_field_select {\n+\tuint32_t l3_prot_type:1;\n+\tuint32_t l4_prot_type:1;\n+\tuint32_t selected_fields:30;\n+};\n+\n+/* TIR attributes structure, used by TIR operations. */\n+struct mlx5_devx_tir_attr {\n+\tuint32_t disp_type:4;\n+\tuint32_t lro_timeout_period_usecs:16;\n+\tuint32_t lro_enable_mask:4;\n+\tuint32_t lro_max_msg_sz:8;\n+\tuint32_t inline_rqn:24;\n+\tuint32_t rx_hash_symmetric:1;\n+\tuint32_t tunneled_offload_en:1;\n+\tuint32_t indirect_table:24;\n+\tuint32_t rx_hash_fn:4;\n+\tuint32_t self_lb_block:2;\n+\tuint32_t transport_domain:24;\n+\tuint32_t rx_hash_toeplitz_key[10];\n+\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_outer;\n+\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_inner;\n+};\n+\n+/* RQT attributes structure, used by RQT operations. */\n+struct mlx5_devx_rqt_attr {\n+\tuint32_t rqt_max_size:16;\n+\tuint32_t rqt_actual_size:16;\n+\tuint32_t rq_list[];\n+};\n+\n+/* TIS attributes structure. */\n+struct mlx5_devx_tis_attr {\n+\tuint32_t strict_lag_tx_port_affinity:1;\n+\tuint32_t tls_en:1;\n+\tuint32_t lag_tx_port_affinity:4;\n+\tuint32_t prio:4;\n+\tuint32_t transport_domain:24;\n+};\n+\n+/* SQ attributes structure, used by SQ create operation. */\n+struct mlx5_devx_create_sq_attr {\n+\tuint32_t rlky:1;\n+\tuint32_t cd_master:1;\n+\tuint32_t fre:1;\n+\tuint32_t flush_in_error_en:1;\n+\tuint32_t allow_multi_pkt_send_wqe:1;\n+\tuint32_t min_wqe_inline_mode:3;\n+\tuint32_t state:4;\n+\tuint32_t reg_umr:1;\n+\tuint32_t allow_swp:1;\n+\tuint32_t hairpin:1;\n+\tuint32_t user_index:24;\n+\tuint32_t cqn:24;\n+\tuint32_t packet_pacing_rate_limit_index:16;\n+\tuint32_t tis_lst_sz:16;\n+\tuint32_t tis_num:24;\n+\tstruct mlx5_devx_wq_attr wq_attr;\n+};\n+\n+/* SQ attributes structure, used by SQ modify operation. */\n+struct mlx5_devx_modify_sq_attr {\n+\tuint32_t sq_state:4;\n+\tuint32_t state:4;\n+\tuint32_t hairpin_peer_rq:24;\n+\tuint32_t hairpin_peer_vhca:16;\n+};\n+\n+/* mlx5_devx_cmds.c */\n+\n+struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n+\t\t\t\t\t\t uint32_t bulk_sz);\n+int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);\n+int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,\n+\t\t\t\t int clear, uint32_t n_counters,\n+\t\t\t\t uint64_t *pkts, uint64_t *bytes,\n+\t\t\t\t uint32_t mkey, void *addr,\n+\t\t\t\t struct mlx5dv_devx_cmd_comp *cmd_comp,\n+\t\t\t\t uint64_t async_id);\n+int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5_hca_attr *attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_mkey_attr *attr);\n+int mlx5_devx_get_out_command_status(void *out);\n+int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,\n+\t\t\t\t uint32_t *tis_td);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5_devx_create_rq_attr *rq_attr,\n+\t\t\t\t int socket);\n+int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,\n+\t\t\t struct mlx5_devx_modify_rq_attr *rq_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_tir_attr *tir_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_rqt_attr *rqt_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5_devx_create_sq_attr *sq_attr);\n+int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,\n+\t\t\t struct mlx5_devx_modify_sq_attr *sq_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_tis_attr *tis_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);\n+int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,\n+\t\t\t FILE *file);\n+#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 3b4c5db..ce0109c 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -38,6 +38,7 @@\n \n #include \"mlx5.h\"\n #include \"mlx5_glue.h\"\n+#include \"mlx5_devx_cmds.h\"\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_utils.h\"\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 970123b..34f3a53 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -31,6 +31,7 @@\n #include \"mlx5_defs.h\"\n #include \"mlx5_flow.h\"\n #include \"mlx5_glue.h\"\n+#include \"mlx5_devx_cmds.h\"\n #include \"mlx5_prm.h\"\n #include \"mlx5_rxtx.h\"\n \n@@ -5704,6 +5705,8 @@ struct mlx5_flow_counter *\n \t\t struct rte_flow_error *error __rte_unused)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_ibv_shared *sh = priv->sh;\n \n-\treturn mlx5_devx_cmd_flow_dump(priv->sh, file);\n+\treturn mlx5_devx_cmd_flow_dump(sh->fdb_domain, sh->rx_domain,\n+\t\t\t\t sh->tx_domain, file);\n }\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 5a1b426..d70dd4f 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -32,6 +32,7 @@\n #include \"mlx5.h\"\n #include \"mlx5_defs.h\"\n #include \"mlx5_glue.h\"\n+#include \"mlx5_devx_cmds.h\"\n #include \"mlx5_flow.h\"\n #include \"mlx5_prm.h\"\n #include \"mlx5_rxtx.h\"\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex c936a7f..89168cd 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -37,6 +37,7 @@\n #include \"mlx5_defs.h\"\n #include \"mlx5_glue.h\"\n #include \"mlx5_flow.h\"\n+#include \"mlx5_devx_cmds.h\"\n \n /* Default RSS hash key also used for ConnectX-3. */\n uint8_t rss_hash_default_key[] = {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 67cafd1..2eede1b 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -29,6 +29,7 @@\n #include <rte_flow.h>\n \n #include \"mlx5.h\"\n+#include \"mlx5_devx_cmds.h\"\n #include \"mlx5_utils.h\"\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_autoconf.h\"\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 1a76f6e..5adb4dc 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -34,6 +34,7 @@\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_autoconf.h\"\n #include \"mlx5_glue.h\"\n+#include \"mlx5_devx_cmds.h\"\n \n /**\n * Allocate TX queue elements.\ndiff --git a/drivers/net/mlx5/mlx5_vlan.c b/drivers/net/mlx5/mlx5_vlan.c\nindex 5f6554a..feac0f1 100644\n--- a/drivers/net/mlx5/mlx5_vlan.c\n+++ b/drivers/net/mlx5/mlx5_vlan.c\n@@ -30,6 +30,7 @@\n #include \"mlx5.h\"\n #include \"mlx5_autoconf.h\"\n #include \"mlx5_glue.h\"\n+#include \"mlx5_devx_cmds.h\"\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_utils.h\"\n \n", "prefixes": [ "v1", "01/38" ] }