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GET /api/patches/64711/?format=api
{ "id": 64711, "url": "http://patches.dpdk.org/api/patches/64711/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200115145923.29515-2-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200115145923.29515-2-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200115145923.29515-2-adamx.dybkowski@intel.com", "date": "2020-01-15T14:59:22", "name": "[v3,1/2] crypto/qat: handle mixed hash-cipher requests on GEN3 QAT", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b18ed57a6c8f2f3fbbb13ffc5dddd3e6de64cf13", "submitter": { "id": 1322, "url": "http://patches.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200115145923.29515-2-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 8138, "url": "http://patches.dpdk.org/api/series/8138/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8138", "date": "2020-01-15T14:59:21", "name": "Handle mixed algorithms on GEN3 QAT", "version": 3, "mbox": "http://patches.dpdk.org/series/8138/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64711/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64711/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 694E5A0513;\n\tWed, 15 Jan 2020 15:59:38 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C38891C191;\n\tWed, 15 Jan 2020 15:59:30 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 8D2091BFC3\n for <dev@dpdk.org>; Wed, 15 Jan 2020 15:59:27 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 15 Jan 2020 06:59:27 -0800", "from adamdybx-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n ([10.104.125.6])\n by fmsmga002.fm.intel.com with ESMTP; 15 Jan 2020 06:59:25 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,322,1574150400\"; d=\"scan'208\";a=\"256799453\"", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org,\n\tfiona.trahe@intel.com,\n\takhil.goyal@nxp.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Wed, 15 Jan 2020 15:59:22 +0100", "Message-Id": "<20200115145923.29515-2-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200115145923.29515-1-adamx.dybkowski@intel.com>", "References": "<20191211140935.9503-1-adamx.dybkowski@intel.com>\n <20200115145923.29515-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/2] crypto/qat: handle mixed hash-cipher\n\trequests on GEN3 QAT", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch implements handling mixed encrypted digest hash-cipher\nrequests (e.g. SNOW3G + ZUC or ZUC + AES CTR) possible when running\non GEN3 QAT. Such algorithm combinations are not supported on\nGEN1/GEN2 hardware.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\n---\n doc/guides/cryptodevs/qat.rst | 24 ++++++++\n doc/guides/rel_notes/release_20_02.rst | 7 +++\n drivers/common/qat/qat_adf/icp_qat_fw.h | 3 +\n drivers/common/qat/qat_adf/icp_qat_fw_la.h | 2 +\n drivers/crypto/qat/qat_sym_session.c | 72 ++++++++++++++++++++++\n 5 files changed, 108 insertions(+)", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex 6197875fe..9053ae9c0 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -72,6 +72,30 @@ Supported AEAD algorithms:\n * ``RTE_CRYPTO_AEAD_AES_CCM``\n \n \n+Supported Chains\n+~~~~~~~~~~~~~~~~\n+\n+All the usual chains are supported and also some mixed chains:\n+\n+.. table:: Supported hash-cipher chains for wireless digest-encrypted cases\n+\n+ +------------------+-----------+-------------+----------+----------+\n+ | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |\n+ +==================+===========+=============+==========+==========+\n+ | NULL CIPHER | Y | 3 | 3 | Y |\n+ +------------------+-----------+-------------+----------+----------+\n+ | SNOW3G UEA2 | 3 | Y | 3 | 3 |\n+ +------------------+-----------+-------------+----------+----------+\n+ | ZUC EEA3 | 3 | 3 | 2&3 | 3 |\n+ +------------------+-----------+-------------+----------+----------+\n+ | AES CTR | Y | 3 | 3 | Y |\n+ +------------------+-----------+-------------+----------+----------+\n+\n+* The combinations marked as \"Y\" are supported on all QAT hardware versions.\n+* The combinations marked as \"2&3\" are supported on GEN2/GEN3 QAT hardware only.\n+* The combinations marked as \"3\" are supported on GEN3 QAT hardware only.\n+\n+\n Limitations\n ~~~~~~~~~~~\n \ndiff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst\nindex 6b60f4737..b99abddfd 100644\n--- a/doc/guides/rel_notes/release_20_02.rst\n+++ b/doc/guides/rel_notes/release_20_02.rst\n@@ -60,6 +60,13 @@ New Features\n \n Chacha20-Poly1305 AEAD algorithm can now be supported in Cryptodev.\n \n+* **Added handling of mixed algorithms in encrypted digest requests in QAT PMD.**\n+\n+ Added handling of mixed algorithms in encrypted digest hash-cipher\n+ (generation) and cipher-hash (verification) requests (e.g. SNOW3G + ZUC or\n+ ZUC + AES CTR) in QAT PMD possible when running on GEN3 QAT hardware.\n+ Such algorithm combinations are not supported on GEN1/GEN2 hardware\n+ and executing the request returns RTE_CRYPTO_OP_STATUS_INVALID_SESSION.\n \n Removed Items\n -------------\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h\nindex 8f7cb37b4..1265c2a13 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h\n@@ -175,6 +175,9 @@ struct icp_qat_fw_comn_resp {\n #define QAT_COMN_PTR_TYPE_SGL 0x1\n #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0\n #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1\n+#define QAT_COMN_EXT_FLAGS_BITPOS 8\n+#define QAT_COMN_EXT_FLAGS_MASK 0x1\n+#define QAT_COMN_EXT_FLAGS_USED 0x1\n \n #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \\\n \t((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \\\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 38891eb1f..20eb145de 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -273,6 +273,8 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {\n \n #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1\n #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0\n+#define ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS 3\n+#define ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS 4\n #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX\t240\n #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24\n #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 72290ba48..4359f2f0b 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -416,6 +416,74 @@ qat_sym_session_configure(struct rte_cryptodev *dev,\n \treturn 0;\n }\n \n+static void\n+qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,\n+\t\tuint8_t hash_flag)\n+{\n+\tstruct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr;\n+\tstruct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl =\n+\t\t\t(struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *)\n+\t\t\tsession->fw_req.cd_ctrl.content_desc_ctrl_lw;\n+\n+\t/* Set the Use Extended Protocol Flags bit in LW 1 */\n+\tQAT_FIELD_SET(header->comn_req_flags,\n+\t\t\tQAT_COMN_EXT_FLAGS_USED,\n+\t\t\tQAT_COMN_EXT_FLAGS_BITPOS,\n+\t\t\tQAT_COMN_EXT_FLAGS_MASK);\n+\n+\t/* Set Hash Flags in LW 28 */\n+\tcd_ctrl->hash_flags |= hash_flag;\n+\n+\t/* Set proto flags in LW 1 */\n+\tswitch (session->qat_cipher_alg) {\n+\tcase ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_SNOW_3G_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags, 0);\n+\t\tbreak;\n+\tcase ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_ZUC_3G_PROTO);\n+\t\tbreak;\n+\tdefault:\n+\t\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\t\tICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(\n+\t\t\t\theader->serv_specif_flags, 0);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void\n+qat_sym_session_handle_mixed(struct qat_sym_session *session)\n+{\n+\tif (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&\n+\t\t\tsession->qat_cipher_alg !=\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {\n+\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tqat_sym_session_set_ext_hash_flags(session,\n+\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);\n+\t} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&\n+\t\t\tsession->qat_cipher_alg !=\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {\n+\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tqat_sym_session_set_ext_hash_flags(session,\n+\t\t\t1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);\n+\t} else if ((session->aes_cmac ||\n+\t\t\tsession->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n+\t\t\t(session->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||\n+\t\t\tsession->qat_cipher_alg ==\n+\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n+\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tqat_sym_session_set_ext_hash_flags(session, 0);\n+\t}\n+}\n+\n int\n qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\tstruct rte_crypto_sym_xform *xform, void *session_private)\n@@ -463,6 +531,8 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n+\t\t\t/* Special handling of mixed hash+cipher algorithms */\n+\t\t\tqat_sym_session_handle_mixed(session);\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_HASH_CIPHER:\n@@ -480,6 +550,8 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,\n \t\t\t\t\txform, session);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n+\t\t\t/* Special handling of mixed hash+cipher algorithms */\n+\t\t\tqat_sym_session_handle_mixed(session);\n \t\t}\n \t\tbreak;\n \tcase ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:\n", "prefixes": [ "v3", "1/2" ] }