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GET /api/patches/64295/?format=api
{ "id": 64295, "url": "http://patches.dpdk.org/api/patches/64295/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1578500161-20156-3-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1578500161-20156-3-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1578500161-20156-3-git-send-email-viacheslavo@mellanox.com", "date": "2020-01-08T16:15:59", "name": "[2/4] net/mlx5: update Tx error handling routine", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ef1d7b524919cbf7af886e2fd444a344265b43a9", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1578500161-20156-3-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 8020, "url": "http://patches.dpdk.org/api/series/8020/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8020", "date": "2020-01-08T16:15:57", "name": "net/mlx5: remove Tx descriptor reserved field usage", "version": 1, "mbox": "http://patches.dpdk.org/series/8020/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64295/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64295/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5E119A04F3;\n\tWed, 8 Jan 2020 17:16:31 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 281411DAB8;\n\tWed, 8 Jan 2020 17:16:25 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 9DD6F1DAC2\n for <dev@dpdk.org>; Wed, 8 Jan 2020 17:16:23 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 8 Jan 2020 18:16:21 +0200", "from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx\n [10.210.16.104])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 008GGL1Q000718;\n Wed, 8 Jan 2020 18:16:21 +0200", "from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 008GGLv2020234;\n Wed, 8 Jan 2020 16:16:21 GMT", "(from viacheslavo@localhost)\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 008GGLrE020233;\n Wed, 8 Jan 2020 16:16:21 GMT" ], "X-Authentication-Warning": "pegasus11.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, orika@mellanox.com", "Date": "Wed, 8 Jan 2020 16:15:59 +0000", "Message-Id": "<1578500161-20156-3-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1578500161-20156-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1578500161-20156-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 2/4] net/mlx5: update Tx error handling routine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is preparation step, we are going to store the index\nof elts to free on completion in the dedicated free on\ncompletion queue, this patch updates the elts freeing routine\nand updates Tx error handling routine to be synched with\ncoming new queue.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5_rxtx.c | 98 +++++++++++++++++++++++---------------------\n drivers/net/mlx5/mlx5_rxtx.h | 4 +-\n drivers/net/mlx5/mlx5_txq.c | 2 +-\n 3 files changed, 54 insertions(+), 50 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex ee6d5fc..b7b40ac 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -654,10 +654,10 @@ enum mlx5_txcmp_code {\n * Pointer to the error CQE.\n *\n * @return\n- * Negative value if queue recovery failed,\n- * the last Tx buffer element to free otherwise.\n+ * Negative value if queue recovery failed, otherwise\n+ * the error completion entry is handled successfully.\n */\n-int\n+static int\n mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,\n \t\t\t volatile struct mlx5_err_cqe *err_cqe)\n {\n@@ -701,18 +701,14 @@ enum mlx5_txcmp_code {\n \t\t\t */\n \t\t\ttxq->stats.oerrors += ((txq->wqe_ci & wqe_m) -\n \t\t\t\t\t\tnew_wqe_pi) & wqe_m;\n-\t\tif (tx_recover_qp(txq_ctrl) == 0) {\n-\t\t\ttxq->cq_ci++;\n-\t\t\t/* Release all the remaining buffers. */\n-\t\t\treturn txq->elts_head;\n+\t\tif (tx_recover_qp(txq_ctrl)) {\n+\t\t\t/* Recovering failed - retry later on the same WQE. */\n+\t\t\treturn -1;\n \t\t}\n-\t\t/* Recovering failed - try again later on the same WQE. */\n-\t\treturn -1;\n-\t} else {\n-\t\ttxq->cq_ci++;\n+\t\t/* Release all the remaining buffers. */\n+\t\ttxq_free_elts(txq_ctrl);\n \t}\n-\t/* Do not release buffers. */\n-\treturn txq->elts_tail;\n+\treturn 0;\n }\n \n /**\n@@ -2034,8 +2030,6 @@ enum mlx5_txcmp_code {\n * Pointer to TX queue structure.\n * @param valid CQE pointer\n * if not NULL update txq->wqe_pi and flush the buffers\n- * @param itail\n- * if not negative - flush the buffers till this index.\n * @param olx\n * Configured Tx offloads mask. It is fully defined at\n * compile time and may be used for optimization.\n@@ -2043,25 +2037,18 @@ enum mlx5_txcmp_code {\n static __rte_always_inline void\n mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,\n \t\t volatile struct mlx5_cqe *last_cqe,\n-\t\t int itail,\n \t\t unsigned int olx __rte_unused)\n {\n-\tuint16_t tail;\n-\n \tif (likely(last_cqe != NULL)) {\n+\t\tuint16_t tail;\n+\n \t\ttxq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);\n \t\ttail = ((volatile struct mlx5_wqe_cseg *)\n \t\t\t(txq->wqes + (txq->wqe_pi & txq->wqe_m)))->misc;\n-\t} else if (itail >= 0) {\n-\t\ttail = (uint16_t)itail;\n-\t} else {\n-\t\treturn;\n-\t}\n-\trte_compiler_barrier();\n-\t*txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);\n-\tif (likely(tail != txq->elts_tail)) {\n-\t\tmlx5_tx_free_elts(txq, tail, olx);\n-\t\tassert(tail == txq->elts_tail);\n+\t\tif (likely(tail != txq->elts_tail)) {\n+\t\t\tmlx5_tx_free_elts(txq, tail, olx);\n+\t\t\tassert(tail == txq->elts_tail);\n+\t\t}\n \t}\n }\n \n@@ -2085,6 +2072,7 @@ enum mlx5_txcmp_code {\n {\n \tunsigned int count = MLX5_TX_COMP_MAX_CQE;\n \tvolatile struct mlx5_cqe *last_cqe = NULL;\n+\tuint16_t ci = txq->cq_ci;\n \tint ret;\n \n \tstatic_assert(MLX5_CQE_STATUS_HW_OWN < 0, \"Must be negative value\");\n@@ -2092,8 +2080,8 @@ enum mlx5_txcmp_code {\n \tdo {\n \t\tvolatile struct mlx5_cqe *cqe;\n \n-\t\tcqe = &txq->cqes[txq->cq_ci & txq->cqe_m];\n-\t\tret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);\n+\t\tcqe = &txq->cqes[ci & txq->cqe_m];\n+\t\tret = check_cqe(cqe, txq->cqe_s, ci);\n \t\tif (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {\n \t\t\tif (likely(ret != MLX5_CQE_STATUS_ERR)) {\n \t\t\t\t/* No new CQEs in completion queue. */\n@@ -2109,31 +2097,49 @@ enum mlx5_txcmp_code {\n \t\t\trte_wmb();\n \t\t\tret = mlx5_tx_error_cqe_handle\n \t\t\t\t(txq, (volatile struct mlx5_err_cqe *)cqe);\n+\t\t\tif (unlikely(ret < 0)) {\n+\t\t\t\t/*\n+\t\t\t\t * Some error occurred on queue error\n+\t\t\t\t * handling, we do not advance the index\n+\t\t\t\t * here, allowing to retry on next call.\n+\t\t\t\t */\n+\t\t\t\treturn;\n+\t\t\t}\n \t\t\t/*\n-\t\t\t * Flush buffers, update consuming index\n-\t\t\t * if recovery succeeded. Otherwise\n-\t\t\t * just try to recover later.\n+\t\t\t * We are going to fetch all entries with\n+\t\t\t * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.\n \t\t\t */\n-\t\t\tlast_cqe = NULL;\n-\t\t\tbreak;\n+\t\t\t++ci;\n+\t\t\tcontinue;\n \t\t}\n \t\t/* Normal transmit completion. */\n-\t\t++txq->cq_ci;\n+\t\t++ci;\n \t\tlast_cqe = cqe;\n #ifndef NDEBUG\n \t\tif (txq->cq_pi)\n \t\t\t--txq->cq_pi;\n #endif\n-\t/*\n-\t * We have to restrict the amount of processed CQEs\n-\t * in one tx_burst routine call. The CQ may be large\n-\t * and many CQEs may be updated by the NIC in one\n-\t * transaction. Buffers freeing is time consuming,\n-\t * multiple iterations may introduce significant\n-\t * latency.\n-\t */\n-\t} while (--count);\n-\tmlx5_tx_comp_flush(txq, last_cqe, ret, olx);\n+\t\t/*\n+\t\t * We have to restrict the amount of processed CQEs\n+\t\t * in one tx_burst routine call. The CQ may be large\n+\t\t * and many CQEs may be updated by the NIC in one\n+\t\t * transaction. Buffers freeing is time consuming,\n+\t\t * multiple iterations may introduce significant\n+\t\t * latency.\n+\t\t */\n+\t\tif (--count == 0)\n+\t\t\tbreak;\n+\t} while (true);\n+\tif (likely(ci != txq->cq_ci)) {\n+\t\t/*\n+\t\t * Update completion queue consuming index\n+\t\t * and ring doorbell to notify hardware.\n+\t\t */\n+\t\trte_compiler_barrier();\n+\t\ttxq->cq_ci = ci;\n+\t\t*txq->cq_db = rte_cpu_to_be_32(ci);\n+\t\tmlx5_tx_comp_flush(txq, last_cqe, olx);\n+\t}\n }\n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex e927343..8a2185a 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -440,6 +440,7 @@ struct mlx5_txq_ctrl *mlx5_txq_hairpin_new\n int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_verify(struct rte_eth_dev *dev);\n void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);\n+void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);\n uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);\n \n /* mlx5_rxtx.c */\n@@ -451,9 +452,6 @@ struct mlx5_txq_ctrl *mlx5_txq_hairpin_new\n void mlx5_set_ptype_table(void);\n void mlx5_set_cksum_table(void);\n void mlx5_set_swp_types_table(void);\n-__rte_noinline int mlx5_tx_error_cqe_handle\n-\t\t\t\t(struct mlx5_txq_data *restrict txq,\n-\t\t\t\t volatile struct mlx5_err_cqe *err_cqe);\n uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);\n void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);\n __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 1c4f7e7..abe0947 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -62,7 +62,7 @@\n * @param txq_ctrl\n * Pointer to TX queue structure.\n */\n-static void\n+void\n txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl)\n {\n \tconst uint16_t elts_n = 1 << txq_ctrl->txq.elts_n;\n", "prefixes": [ "2/4" ] }