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GET /api/patches/64040/?format=api
{ "id": 64040, "url": "http://patches.dpdk.org/api/patches/64040/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1576811391-19131-4-git-send-email-gavin.hu@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1576811391-19131-4-git-send-email-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1576811391-19131-4-git-send-email-gavin.hu@arm.com", "date": "2019-12-20T03:09:51", "name": "[v2,3/3] crypto/virtio: virtual PCI requires smp barriers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5065e2cf28c7076667613ac574279de9aa37ee32", "submitter": { "id": 1018, "url": "http://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1576811391-19131-4-git-send-email-gavin.hu@arm.com/mbox/", "series": [ { "id": 7901, "url": "http://patches.dpdk.org/api/series/7901/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7901", "date": "2019-12-20T03:09:48", "name": "relax io barrier for aarch64 and use smp barriers for virtual pci memory", "version": 2, "mbox": "http://patches.dpdk.org/series/7901/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64040/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64040/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB6DEA04F3;\n\tFri, 20 Dec 2019 04:10:54 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BC3891BF76;\n\tFri, 20 Dec 2019 04:10:42 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id D4DC51BDFD\n for <dev@dpdk.org>; Fri, 20 Dec 2019 04:10:40 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52D3130E;\n Thu, 19 Dec 2019 19:10:40 -0800 (PST)", "from net-arm-thunderx2-01.test.ast.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 65DC63F719;\n Thu, 19 Dec 2019 19:10:36 -0800 (PST)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,\n rasland@mellanox.com, maxime.coquelin@redhat.com, tiwei.bie@intel.com,\n hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com,\n Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com,\n joyce.kong@arm.com, steve.capper@arm.com", "Date": "Fri, 20 Dec 2019 11:09:51 +0800", "Message-Id": "<1576811391-19131-4-git-send-email-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1576811391-19131-1-git-send-email-gavin.hu@arm.com>", "<1571758074-16445-1-git-send-email-gavin.hu@arm.com>" ], "References": [ "<1576811391-19131-1-git-send-email-gavin.hu@arm.com>", "<1571758074-16445-1-git-send-email-gavin.hu@arm.com>" ], "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 3/3] crypto/virtio: virtual PCI requires smp\n\tbarriers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Other than real PCI reads and writes to the device memory requiring\nthe io barriers, virtual pci memories are normal memory in the smp\nconfiguration, and requires the smp barriers.\n\nSince the smp barriers and io barriers are identical on x86 and PPC,\nthis change has only effect on aarch64.\n\nAs far as peripheral coherence order for ‘virtual’ devices, the arch\nintent is that the Hypervisor view of things takes precedence – since\ntranslations are made in holistic manner as the full stage1+stage2\nregime, there is no such thing as a transaction taking on “EL1”\nmapping as far as ordering. If the Hypervisor maps stage2 as Normal\nbut the OS at EL1 maps it as Device-nGnRE, then it’s Normal memory and\nfollows the ordering rules for Normal memory.\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\n---\n drivers/crypto/virtio/virtio_pci.c | 108 ++++++++++++++++++++++++++-----------\n 1 file changed, 78 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/crypto/virtio/virtio_pci.c b/drivers/crypto/virtio/virtio_pci.c\nindex 8137b3c..dd8eda8 100644\n--- a/drivers/crypto/virtio/virtio_pci.c\n+++ b/drivers/crypto/virtio/virtio_pci.c\n@@ -24,6 +24,54 @@\n #define PCI_CAP_ID_VNDR\t\t0x09\n #define PCI_CAP_ID_MSIX\t\t0x11\n \n+static __rte_always_inline uint8_t\n+virtio_pci_read8(const volatile void *addr)\n+{\n+\tuint8_t val;\n+\tval = rte_read8_relaxed(addr);\n+\trte_smp_rmb();\n+\treturn val;\n+}\n+\n+static __rte_always_inline uint16_t\n+virtio_pci_read16(const volatile void *addr)\n+{\n+\tuint16_t val;\n+\tval = rte_read16_relaxed(addr);\n+\trte_smp_rmb();\n+\treturn val;\n+}\n+\n+static __rte_always_inline uint32_t\n+virtio_pci_read32(const volatile void *addr)\n+{\n+\tuint32_t val;\n+\tval = rte_read32_relaxed(addr);\n+\trte_smp_rmb();\n+\treturn val;\n+}\n+\n+static __rte_always_inline void\n+virtio_pci_write8(uint8_t value, volatile void *addr)\n+{\n+\trte_smp_wmb();\n+\trte_write8_relaxed(value, addr);\n+}\n+\n+static __rte_always_inline void\n+virtio_pci_write16(uint16_t value, volatile void *addr)\n+{\n+\trte_smp_wmb();\n+\trte_write16_relaxed(value, addr);\n+}\n+\n+static __rte_always_inline void\n+virtio_pci_write32(uint32_t value, volatile void *addr)\n+{\n+\trte_smp_wmb();\n+\trte_write32_relaxed(value, addr);\n+}\n+\n /*\n * The remaining space is defined by each driver as the per-driver\n * configuration space.\n@@ -52,8 +100,8 @@ check_vq_phys_addr_ok(struct virtqueue *vq)\n static inline void\n io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)\n {\n-\trte_write32(val & ((1ULL << 32) - 1), lo);\n-\trte_write32(val >> 32,\t\t hi);\n+\tvirtio_pci_write32(val & ((1ULL << 32) - 1), lo);\n+\tvirtio_pci_write32(val >> 32,\t\t hi);\n }\n \n static void\n@@ -65,13 +113,13 @@ modern_read_dev_config(struct virtio_crypto_hw *hw, size_t offset,\n \tuint8_t old_gen, new_gen;\n \n \tdo {\n-\t\told_gen = rte_read8(&hw->common_cfg->config_generation);\n+\t\told_gen = virtio_pci_read8(&hw->common_cfg->config_generation);\n \n \t\tp = dst;\n \t\tfor (i = 0; i < length; i++)\n-\t\t\t*p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);\n+\t\t\t*p++ = virtio_pci_read8((uint8_t *)hw->dev_cfg + offset + i);\n \n-\t\tnew_gen = rte_read8(&hw->common_cfg->config_generation);\n+\t\tnew_gen = virtio_pci_read8(&hw->common_cfg->config_generation);\n \t} while (old_gen != new_gen);\n }\n \n@@ -83,7 +131,7 @@ modern_write_dev_config(struct virtio_crypto_hw *hw, size_t offset,\n \tconst uint8_t *p = src;\n \n \tfor (i = 0; i < length; i++)\n-\t\trte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));\n+\t\tvirtio_pci_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));\n }\n \n static uint64_t\n@@ -91,11 +139,11 @@ modern_get_features(struct virtio_crypto_hw *hw)\n {\n \tuint32_t features_lo, features_hi;\n \n-\trte_write32(0, &hw->common_cfg->device_feature_select);\n-\tfeatures_lo = rte_read32(&hw->common_cfg->device_feature);\n+\tvirtio_pci_write32(0, &hw->common_cfg->device_feature_select);\n+\tfeatures_lo = virtio_pci_read32(&hw->common_cfg->device_feature);\n \n-\trte_write32(1, &hw->common_cfg->device_feature_select);\n-\tfeatures_hi = rte_read32(&hw->common_cfg->device_feature);\n+\tvirtio_pci_write32(1, &hw->common_cfg->device_feature_select);\n+\tfeatures_hi = virtio_pci_read32(&hw->common_cfg->device_feature);\n \n \treturn ((uint64_t)features_hi << 32) | features_lo;\n }\n@@ -103,25 +151,25 @@ modern_get_features(struct virtio_crypto_hw *hw)\n static void\n modern_set_features(struct virtio_crypto_hw *hw, uint64_t features)\n {\n-\trte_write32(0, &hw->common_cfg->guest_feature_select);\n-\trte_write32(features & ((1ULL << 32) - 1),\n+\tvirtio_pci_write32(0, &hw->common_cfg->guest_feature_select);\n+\tvirtio_pci_write32(features & ((1ULL << 32) - 1),\n \t\t &hw->common_cfg->guest_feature);\n \n-\trte_write32(1, &hw->common_cfg->guest_feature_select);\n-\trte_write32(features >> 32,\n+\tvirtio_pci_write32(1, &hw->common_cfg->guest_feature_select);\n+\tvirtio_pci_write32(features >> 32,\n \t\t &hw->common_cfg->guest_feature);\n }\n \n static uint8_t\n modern_get_status(struct virtio_crypto_hw *hw)\n {\n-\treturn rte_read8(&hw->common_cfg->device_status);\n+\treturn virtio_pci_read8(&hw->common_cfg->device_status);\n }\n \n static void\n modern_set_status(struct virtio_crypto_hw *hw, uint8_t status)\n {\n-\trte_write8(status, &hw->common_cfg->device_status);\n+\tvirtio_pci_write8(status, &hw->common_cfg->device_status);\n }\n \n static void\n@@ -134,30 +182,30 @@ modern_reset(struct virtio_crypto_hw *hw)\n static uint8_t\n modern_get_isr(struct virtio_crypto_hw *hw)\n {\n-\treturn rte_read8(hw->isr);\n+\treturn virtio_pci_read8(hw->isr);\n }\n \n static uint16_t\n modern_set_config_irq(struct virtio_crypto_hw *hw, uint16_t vec)\n {\n-\trte_write16(vec, &hw->common_cfg->msix_config);\n-\treturn rte_read16(&hw->common_cfg->msix_config);\n+\tvirtio_pci_write16(vec, &hw->common_cfg->msix_config);\n+\treturn virtio_pci_read16(&hw->common_cfg->msix_config);\n }\n \n static uint16_t\n modern_set_queue_irq(struct virtio_crypto_hw *hw, struct virtqueue *vq,\n \t\tuint16_t vec)\n {\n-\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n-\trte_write16(vec, &hw->common_cfg->queue_msix_vector);\n-\treturn rte_read16(&hw->common_cfg->queue_msix_vector);\n+\tvirtio_pci_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\tvirtio_pci_write16(vec, &hw->common_cfg->queue_msix_vector);\n+\treturn virtio_pci_read16(&hw->common_cfg->queue_msix_vector);\n }\n \n static uint16_t\n modern_get_queue_num(struct virtio_crypto_hw *hw, uint16_t queue_id)\n {\n-\trte_write16(queue_id, &hw->common_cfg->queue_select);\n-\treturn rte_read16(&hw->common_cfg->queue_size);\n+\tvirtio_pci_write16(queue_id, &hw->common_cfg->queue_select);\n+\treturn virtio_pci_read16(&hw->common_cfg->queue_size);\n }\n \n static int\n@@ -175,7 +223,7 @@ modern_setup_queue(struct virtio_crypto_hw *hw, struct virtqueue *vq)\n \t\t\t\t\t\t\t ring[vq->vq_nentries]),\n \t\t\t\t VIRTIO_PCI_VRING_ALIGN);\n \n-\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\tvirtio_pci_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n \n \tio_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,\n \t\t\t\t &hw->common_cfg->queue_desc_hi);\n@@ -184,11 +232,11 @@ modern_setup_queue(struct virtio_crypto_hw *hw, struct virtqueue *vq)\n \tio_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,\n \t\t\t\t &hw->common_cfg->queue_used_hi);\n \n-\tnotify_off = rte_read16(&hw->common_cfg->queue_notify_off);\n+\tnotify_off = virtio_pci_read16(&hw->common_cfg->queue_notify_off);\n \tvq->notify_addr = (void *)((uint8_t *)hw->notify_base +\n \t\t\t\tnotify_off * hw->notify_off_multiplier);\n \n-\trte_write16(1, &hw->common_cfg->queue_enable);\n+\tvirtio_pci_write16(1, &hw->common_cfg->queue_enable);\n \n \tVIRTIO_CRYPTO_INIT_LOG_DBG(\"queue %u addresses:\", vq->vq_queue_index);\n \tVIRTIO_CRYPTO_INIT_LOG_DBG(\"\\t desc_addr: %\" PRIx64, desc_addr);\n@@ -203,7 +251,7 @@ modern_setup_queue(struct virtio_crypto_hw *hw, struct virtqueue *vq)\n static void\n modern_del_queue(struct virtio_crypto_hw *hw, struct virtqueue *vq)\n {\n-\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\tvirtio_pci_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n \n \tio_write64_twopart(0, &hw->common_cfg->queue_desc_lo,\n \t\t\t\t &hw->common_cfg->queue_desc_hi);\n@@ -212,14 +260,14 @@ modern_del_queue(struct virtio_crypto_hw *hw, struct virtqueue *vq)\n \tio_write64_twopart(0, &hw->common_cfg->queue_used_lo,\n \t\t\t\t &hw->common_cfg->queue_used_hi);\n \n-\trte_write16(0, &hw->common_cfg->queue_enable);\n+\tvirtio_pci_write16(0, &hw->common_cfg->queue_enable);\n }\n \n static void\n modern_notify_queue(struct virtio_crypto_hw *hw __rte_unused,\n \t\tstruct virtqueue *vq)\n {\n-\trte_write16(vq->vq_queue_index, vq->notify_addr);\n+\tvirtio_pci_write16(vq->vq_queue_index, vq->notify_addr);\n }\n \n const struct virtio_pci_ops virtio_crypto_modern_ops = {\n", "prefixes": [ "v2", "3/3" ] }