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GET /api/patches/64038/?format=api
{ "id": 64038, "url": "http://patches.dpdk.org/api/patches/64038/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1576811391-19131-2-git-send-email-gavin.hu@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1576811391-19131-2-git-send-email-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1576811391-19131-2-git-send-email-gavin.hu@arm.com", "date": "2019-12-20T03:09:49", "name": "[v2,1/3] eal/arm64: relax the io barrier for aarch64", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f86c09b83d0bb9461b2fbf65dd19bab94bec916f", "submitter": { "id": 1018, "url": "http://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1576811391-19131-2-git-send-email-gavin.hu@arm.com/mbox/", "series": [ { "id": 7901, "url": "http://patches.dpdk.org/api/series/7901/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7901", "date": "2019-12-20T03:09:48", "name": "relax io barrier for aarch64 and use smp barriers for virtual pci memory", "version": 2, "mbox": "http://patches.dpdk.org/series/7901/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64038/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64038/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4A450A04F3;\n\tFri, 20 Dec 2019 04:10:37 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5678B1BF78;\n\tFri, 20 Dec 2019 04:10:34 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 5CFC91BF76\n for <dev@dpdk.org>; Fri, 20 Dec 2019 04:10:32 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D473A31B;\n Thu, 19 Dec 2019 19:10:31 -0800 (PST)", "from net-arm-thunderx2-01.test.ast.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 262FF3F719;\n Thu, 19 Dec 2019 19:10:27 -0800 (PST)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net,\n rasland@mellanox.com, maxime.coquelin@redhat.com, tiwei.bie@intel.com,\n hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com,\n Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com,\n joyce.kong@arm.com, steve.capper@arm.com", "Date": "Fri, 20 Dec 2019 11:09:49 +0800", "Message-Id": "<1576811391-19131-2-git-send-email-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1576811391-19131-1-git-send-email-gavin.hu@arm.com>", "<1571758074-16445-1-git-send-email-gavin.hu@arm.com>" ], "References": [ "<1576811391-19131-1-git-send-email-gavin.hu@arm.com>", "<1571758074-16445-1-git-send-email-gavin.hu@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for\n\taarch64", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Armv8's peripheral coherence order is a total order on all reads and writes\nto that peripheral.[1]\n\nThe peripheral coherence order for a memory-mapped peripheral signifies the\norder in which accesses arrive at the endpoint. For a read or a write RW1\nand a read or a write RW2 to the same peripheral, then RW1 will appear in\nthe peripheral coherence order for the peripheral before RW2 if either of\nthe following cases apply:\n 1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and\n RW1 is Ordered-before RW2.\n 2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes\n and RW1 appears in program order before RW2.\n\nOn arm platforms, all the PCI resources are mapped to nGnRE device memory\n[2], the above case 2 holds true, that means the peripheral coherence order\napplies here and just a compiler barrier is sufficient for rte io barriers.\n\n[1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates\nt/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile\n[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/\ntree/drivers/pci/pci-sysfs.c#n1204\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Steve Capper <steve.capper@arm.com>\nReviewed-by: Phil Yang <phil.yang@arm.com>\n---\n lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h\nindex 859ae12..fd63956 100644\n--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h\n@@ -34,11 +34,11 @@ extern \"C\" {\n \n #define rte_smp_rmb() dmb(ishld)\n \n-#define rte_io_mb() rte_mb()\n+#define rte_io_mb() rte_compiler_barrier()\n \n-#define rte_io_wmb() rte_wmb()\n+#define rte_io_wmb() rte_compiler_barrier()\n \n-#define rte_io_rmb() rte_rmb()\n+#define rte_io_rmb() rte_compiler_barrier()\n \n #define rte_cio_wmb() dmb(oshst)\n \n", "prefixes": [ "v2", "1/3" ] }