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GET /api/patches/63985/?format=api
{ "id": 63985, "url": "http://patches.dpdk.org/api/patches/63985/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1576648808-24765-6-git-send-email-joyce.kong@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1576648808-24765-6-git-send-email-joyce.kong@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1576648808-24765-6-git-send-email-joyce.kong@arm.com", "date": "2019-12-18T06:00:07", "name": "[v6,5/6] net/qede: use common rte bit operation APIs instead", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e0143d48e02ea8cc5a5ccc30592d8638f9093df9", "submitter": { "id": 970, "url": "http://patches.dpdk.org/api/people/970/?format=api", "name": "Joyce Kong", "email": "joyce.kong@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1576648808-24765-6-git-send-email-joyce.kong@arm.com/mbox/", "series": [ { "id": 7882, "url": "http://patches.dpdk.org/api/series/7882/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7882", "date": "2019-12-18T06:00:02", "name": "implement common rte bit operation APIs in PMDs", "version": 6, "mbox": "http://patches.dpdk.org/series/7882/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63985/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A492A050F;\n\tWed, 18 Dec 2019 07:01:31 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 61F341BF7C;\n\tWed, 18 Dec 2019 07:01:05 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 1B06B1BF80\n for <dev@dpdk.org>; Wed, 18 Dec 2019 07:01:04 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9BB5631B;\n Tue, 17 Dec 2019 22:01:03 -0800 (PST)", "from net-arm-thunderx2-01.test.ast.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C12843F718;\n Tue, 17 Dec 2019 22:00:58 -0800 (PST)" ], "From": "Joyce Kong <joyce.kong@arm.com>", "To": "thomas@monjalon.net, stephen@networkplumber.org,\n david.marchand@redhat.com,\n mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com,\n ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com,\n xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com,\n zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com,\n gavin.hu@arm.com", "Cc": "nd@arm.com,\n\tdev@dpdk.org", "Date": "Wed, 18 Dec 2019 14:00:07 +0800", "Message-Id": "<1576648808-24765-6-git-send-email-joyce.kong@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1576648808-24765-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "References": [ "<1576648808-24765-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v6 5/6] net/qede: use common rte bit operation\n\tAPIs instead", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove its own bit operation APIs and use the common one,\nthis can reduce the code duplication largely.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\n---\n drivers/net/qede/base/bcm_osal.c | 22 +-----------------\n drivers/net/qede/base/bcm_osal.h | 14 +++++-------\n drivers/net/qede/base/ecore.h | 6 ++---\n drivers/net/qede/base/ecore_cxt.c | 6 ++---\n drivers/net/qede/base/ecore_dcbx.c | 8 +++----\n drivers/net/qede/base/ecore_dev.c | 38 +++++++++++++++----------------\n drivers/net/qede/base/ecore_dev_api.h | 2 +-\n drivers/net/qede/base/ecore_l2.c | 6 ++---\n drivers/net/qede/base/ecore_mcp.c | 4 ++--\n drivers/net/qede/base/ecore_sp_commands.c | 12 +++++-----\n drivers/net/qede/base/ecore_spq.c | 2 +-\n drivers/net/qede/base/ecore_spq.h | 10 ++++----\n drivers/net/qede/qede_main.c | 4 ++--\n 13 files changed, 56 insertions(+), 78 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\nindex 48d016e..54e5e4f 100644\n--- a/drivers/net/qede/base/bcm_osal.c\n+++ b/drivers/net/qede/base/bcm_osal.c\n@@ -46,26 +46,6 @@ u32 qede_osal_log2(u32 val)\n \treturn log;\n }\n \n-inline void qede_set_bit(u32 nr, unsigned long *addr)\n-{\n-\t__sync_fetch_and_or(addr, (1UL << nr));\n-}\n-\n-inline void qede_clr_bit(u32 nr, unsigned long *addr)\n-{\n-\t__sync_fetch_and_and(addr, ~(1UL << nr));\n-}\n-\n-inline bool qede_test_bit(u32 nr, unsigned long *addr)\n-{\n-\tbool res;\n-\n-\trte_mb();\n-\tres = ((*addr) & (1UL << nr)) != 0;\n-\trte_mb();\n-\treturn res;\n-}\n-\n static inline u32 qede_ffb(unsigned long word)\n {\n \tunsigned long first_bit;\n@@ -95,7 +75,7 @@ static inline u32 qede_ffz(unsigned long word)\n \treturn first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;\n }\n \n-inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)\n+inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit)\n {\n \tu32 i;\n \tu32 nwords = 0;\ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 0f09557..023ca06 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -8,6 +8,7 @@\n #define __BCM_OSAL_H\n \n #include <rte_byteorder.h>\n+#include <rte_bitops.h>\n #include <rte_spinlock.h>\n #include <rte_malloc.h>\n #include <rte_atomic.h>\n@@ -311,23 +312,20 @@ typedef struct osal_list_t {\n #define OSAL_BITS_PER_UL_MASK\t\t(OSAL_BITS_PER_UL - 1)\n \n /* Bitops */\n-void qede_set_bit(u32, unsigned long *);\n #define OSAL_SET_BIT(bit, bitmap) \\\n-\tqede_set_bit(bit, bitmap)\n+\trte_set_bit32(bit, bitmap)\n \n-void qede_clr_bit(u32, unsigned long *);\n #define OSAL_CLEAR_BIT(bit, bitmap) \\\n-\tqede_clr_bit(bit, bitmap)\n+\trte_clear_bit32(bit, bitmap)\n \n-bool qede_test_bit(u32, unsigned long *);\n-#define OSAL_TEST_BIT(bit, bitmap) \\\n-\tqede_test_bit(bit, bitmap)\n+#define OSAL_GET_BIT(bit, bitmap) \\\n+\trte_get_bit32(bit, bitmap)\n \n u32 qede_find_first_bit(unsigned long *, u32);\n #define OSAL_FIND_FIRST_BIT(bitmap, length) \\\n \tqede_find_first_bit(bitmap, length)\n \n-u32 qede_find_first_zero_bit(unsigned long *, u32);\n+u32 qede_find_first_zero_bit(u32 *addr, u32 limit);\n #define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \\\n \tqede_find_first_zero_bit(bitmap, length)\n \ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex b2077bc..498bb6f 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -422,8 +422,8 @@ struct ecore_hw_info {\n \tu8 max_chains_per_vf;\n \n \tu32 port_mode;\n-\tu32\thw_mode;\n-\tunsigned long device_capabilities;\n+\tu32 hw_mode;\n+\tu32 device_capabilities;\n \n \t/* Default DCBX mode */\n \tu8 dcbx_mode;\n@@ -807,7 +807,7 @@ struct ecore_dev {\n \n \tu8\t\t\t\tpath_id;\n \n-\tunsigned long\t\t\tmf_bits;\n+\tu32\t\t\t\tmf_bits;\n \tenum ecore_mf_mode\t\tmf_mode;\n #define IS_MF_DEFAULT(_p_hwfn)\t\\\n \t(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)\ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex 773b75e..dda47ea 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -154,7 +154,7 @@ struct ecore_ilt_client_cfg {\n struct ecore_cid_acquired_map {\n \tu32 start_cid;\n \tu32 max_count;\n-\tunsigned long *cid_map;\n+\tu32 *cid_map;\n };\n \n struct ecore_src_t2 {\n@@ -1991,7 +1991,7 @@ static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,\n \t}\n \n \trel_cid = cid - (*pp_map)->start_cid;\n-\tif (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {\n+\tif (!OSAL_GET_BIT(rel_cid, (*pp_map)->cid_map)) {\n \t\tDP_NOTICE(p_hwfn, true,\n \t\t\t \"CID %d [vifd %02x] not acquired\", cid, vfid);\n \t\tgoto fail;\n@@ -2102,7 +2102,7 @@ enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)\n \n \t\tcount = p_params->num_arfs_filters;\n \n-\t\tif (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,\n+\t\tif (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS,\n \t\t\t\t &p_hwfn->p_dev->mf_bits))\n \t\t\tp_hwfn->p_cxt_mngr->arfs_count = count;\n \ndiff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c\nindex ccd4383..31234f1 100644\n--- a/drivers/net/qede/base/ecore_dcbx.c\n+++ b/drivers/net/qede/base/ecore_dcbx.c\n@@ -148,7 +148,7 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,\n \tp_data->arr[type].update = UPDATE_DCB_DSCP;\n \n \t/* Do not add valn tag 0 when DCB is enabled and port is in UFP mode */\n-\tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n \t\tp_data->arr[type].dont_add_vlan0 = true;\n \n \t/* QM reconf data */\n@@ -156,8 +156,8 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,\n \t\tp_hwfn->hw_info.offload_tc = tc;\n \n \t/* Configure dcbx vlan priority in doorbell block for roce EDPM */\n-\tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) &&\n-\t (type == DCBX_PROTOCOL_ROCE)) {\n+\tif (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) &&\n+\t type == DCBX_PROTOCOL_ROCE) {\n \t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);\n \t\tecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP, prio << 1);\n \t}\n@@ -293,7 +293,7 @@ ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t}\n \n \t/* If Eth TLV is not detected, use UFP TC as default TC */\n-\tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC,\n+\tif (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC,\n \t\t\t &p_hwfn->p_dev->mf_bits) && !eth_tlv)\n \t\tp_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc;\n \ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 9d1db14..e292299 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -805,7 +805,7 @@ static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,\n \t\tecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n+\tif (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n \t !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {\n \t\trc = ecore_llh_add_mac_filter(p_dev, 0,\n \t\t\t\t\t p_hwfn->hw_info.hw_mac_addr);\n@@ -1044,7 +1044,7 @@ ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \tfilter_details.enable = 1;\n \tfilter_details.value = ((u64)high << 32) | low;\n \tfilter_details.hdr_sel =\n-\t\tOSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?\n+\t\tOSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?\n \t\t1 : /* inner/encapsulated header */\n \t\t0; /* outer/tunnel header */\n \tfilter_details.protocol_type = filter_prot_type;\n@@ -1083,7 +1083,7 @@ enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n \tif (p_ptt == OSAL_NULL)\n \t\treturn ECORE_AGAIN;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n \t\tgoto out;\n \n \tOSAL_MEM_ZERO(&filter, sizeof(filter));\n@@ -1220,7 +1220,7 @@ ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n \tif (p_ptt == OSAL_NULL)\n \t\treturn ECORE_AGAIN;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n \t\tgoto out;\n \n \trc = ecore_llh_protocol_filter_stringify(p_dev, type,\n@@ -1287,7 +1287,7 @@ void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n \tif (p_ptt == OSAL_NULL)\n \t\treturn;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n \t\tgoto out;\n \n \tOSAL_MEM_ZERO(&filter, sizeof(filter));\n@@ -1342,7 +1342,7 @@ void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n \tif (p_ptt == OSAL_NULL)\n \t\treturn;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n \t\tgoto out;\n \n \trc = ecore_llh_protocol_filter_stringify(p_dev, type,\n@@ -1396,8 +1396,8 @@ void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)\n \tif (p_ptt == OSAL_NULL)\n \t\treturn;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n-\t !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n+\t !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n \t\tgoto out;\n \n \trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n@@ -1423,8 +1423,8 @@ void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)\n {\n \tu8 ppfid;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n-\t !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n+\t !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n \t\treturn;\n \n \tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)\n@@ -2674,7 +2674,7 @@ static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)\n \t\treturn ECORE_INVAL;\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))\n \t\thw_mode |= 1 << MODE_MF_SD;\n \telse\n \t\thw_mode |= 1 << MODE_MF_SI;\n@@ -3382,7 +3382,7 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n \t\t * The ppfid should be set in the vector, except in BB which has\n \t\t * a bug in the LLH where the ppfid is actually engine based.\n \t\t */\n-\t\tif (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {\n+\t\tif (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {\n \t\t\tu8 pf_id = p_hwfn->rel_pf_id;\n \n \t\t\tif (!ECORE_IS_BB(p_dev))\n@@ -3715,11 +3715,11 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n \n-\t\tif (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,\n+\t\tif (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,\n \t\t\t\t\t\t &p_dev->mf_bits) ||\n-\t\t\t\t OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,\n+\t\t\t\t OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,\n \t\t\t\t\t\t &p_dev->mf_bits))) {\n-\t\t\tif (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,\n+\t\t\tif (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,\n \t\t\t\t\t &p_dev->mf_bits))\n \t\t\t\tether_type = ETHER_TYPE_VLAN;\n \t\t\telse\n@@ -4119,7 +4119,7 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)\n \t\tOSAL_MSLEEP(1);\n \n \t\tif (IS_LEAD_HWFN(p_hwfn) &&\n-\t\t OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n+\t\t OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n \t\t !ECORE_IS_FCOE_PERSONALITY(p_hwfn))\n \t\t\tecore_llh_remove_mac_filter(p_dev, 0,\n \t\t\t\t\t\t p_hwfn->hw_info.hw_mac_addr);\n@@ -5113,7 +5113,7 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,\n \t\t\tp_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;\n \t\tbreak;\n \t}\n-\tDP_INFO(p_hwfn, \"Multi function mode is 0x%lx\\n\",\n+\tDP_INFO(p_hwfn, \"Multi function mode is 0x%x\\n\",\n \t\tp_hwfn->p_dev->mf_bits);\n \n \tif (ECORE_IS_CMT(p_hwfn->p_dev))\n@@ -6202,7 +6202,7 @@ enum _ecore_status_t\n ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,\n \t\t\t\t struct ecore_ptt *p_ptt)\n {\n-\tif (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {\n+\tif (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {\n \t\tecore_wr(p_hwfn, p_ptt,\n \t\t\t NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,\n \t\t\t 1 << p_hwfn->abs_pf_id / 2);\n@@ -6779,5 +6779,5 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb,\n \n bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)\n {\n-\treturn !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);\n+\treturn !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);\n }\ndiff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h\nindex 4d5cc1a..83cfcf7 100644\n--- a/drivers/net/qede/base/ecore_dev_api.h\n+++ b/drivers/net/qede/base/ecore_dev_api.h\n@@ -212,7 +212,7 @@ enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,\n \n static OSAL_INLINE bool ecore_is_mf_ufp(struct ecore_hwfn *p_hwfn)\n {\n-\treturn !!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits);\n+\treturn !!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits);\n }\n \n #endif\ndiff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c\nindex b20d837..af234de 100644\n--- a/drivers/net/qede/base/ecore_l2.c\n+++ b/drivers/net/qede/base/ecore_l2.c\n@@ -29,7 +29,7 @@\n \n struct ecore_l2_info {\n \tu32 queues;\n-\tunsigned long **pp_qid_usage;\n+\tu32 **pp_qid_usage;\n \n \t/* The lock is meant to synchronize access to the qid usage */\n \tosal_mutex_t lock;\n@@ -38,7 +38,7 @@ struct ecore_l2_info {\n enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)\n {\n \tstruct ecore_l2_info *p_l2_info;\n-\tunsigned long **pp_qids;\n+\tu32 **pp_qids;\n \tu32 i;\n \n \tif (!ECORE_IS_L2_PERSONALITY(p_hwfn))\n@@ -2116,7 +2116,7 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,\n \t\t\t struct ecore_ptt *p_ptt,\n \t\t\t struct ecore_arfs_config_params *p_cfg_params)\n {\n-\tif (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))\n \t\treturn;\n \n \tif (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) {\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 7518765..a748596 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -1732,7 +1732,7 @@ static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,\n \tp_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &\n \t\t\t\t\t\t FUNC_MF_CFG_OV_STAG_MASK;\n \tp_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;\n-\tif (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {\n+\tif (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {\n \t\tif (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) {\n \t\t\tecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,\n \t\t\t\t p_hwfn->hw_info.ovlan);\n@@ -2026,7 +2026,7 @@ ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)\n \tstruct public_func shmem_info;\n \tu32 port_cfg, val;\n \n-\tif (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n+\tif (!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n \t\treturn;\n \n \tOSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));\ndiff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c\nindex 9860a62..44ced13 100644\n--- a/drivers/net/qede/base/ecore_sp_commands.c\n+++ b/drivers/net/qede/base/ecore_sp_commands.c\n@@ -335,16 +335,16 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n \tp_ramrod->dont_log_ramrods = 0;\n \tp_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))\n \t\tp_ramrod->mf_mode = MF_OVLAN;\n \telse\n \t\tp_ramrod->mf_mode = MF_NPAR;\n \n \tp_ramrod->outer_tag_config.outer_tag.tci =\n \t\tOSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);\n-\tif (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {\n+\tif (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {\n \t\tp_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;\n-\t} else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,\n+\t} else if (OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,\n \t\t &p_hwfn->p_dev->mf_bits)) {\n \t\tp_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;\n \t\tp_ramrod->outer_tag_config.enable_stag_pri_change = 1;\n@@ -357,7 +357,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n \t/* enable_stag_pri_change should be set if port is in BD mode or,\n \t * UFP with Host Control mode.\n \t */\n-\tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {\n+\tif (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {\n \t\tif (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)\n \t\t\tp_ramrod->outer_tag_config.enable_stag_pri_change = 1;\n \t\telse\n@@ -378,7 +378,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,\n \tecore_tunn_set_pf_start_params(p_hwfn, p_tunn,\n \t\t\t\t &p_ramrod->tunnel_config);\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,\n+\tif (OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH,\n \t\t\t &p_hwfn->p_dev->mf_bits))\n \t\tp_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;\n \n@@ -638,7 +638,7 @@ enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)\n \tif (rc != ECORE_SUCCESS)\n \t\treturn rc;\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))\n \t\tp_ent->ramrod.pf_update.mf_vlan |=\n \t\t\tOSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));\n \ndiff --git a/drivers/net/qede/base/ecore_spq.c b/drivers/net/qede/base/ecore_spq.c\nindex 6c38682..02f6136 100644\n--- a/drivers/net/qede/base/ecore_spq.c\n+++ b/drivers/net/qede/base/ecore_spq.c\n@@ -977,7 +977,7 @@ enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn,\n \t\t\t * for the first successive completed entries.\n \t\t\t */\n \t\t\tSPQ_COMP_BMAP_SET_BIT(p_spq, echo);\n-\t\t\twhile (SPQ_COMP_BMAP_TEST_BIT(p_spq,\n+\t\t\twhile (SPQ_COMP_BMAP_GET_BIT(p_spq,\n \t\t\t\t\t\t p_spq->comp_bitmap_idx)) {\n \t\t\t\tSPQ_COMP_BMAP_CLEAR_BIT(p_spq,\n \t\t\t\t\t\t\tp_spq->comp_bitmap_idx);\ndiff --git a/drivers/net/qede/base/ecore_spq.h b/drivers/net/qede/base/ecore_spq.h\nindex 6142c39..0958e5a 100644\n--- a/drivers/net/qede/base/ecore_spq.h\n+++ b/drivers/net/qede/base/ecore_spq.h\n@@ -121,17 +121,17 @@ struct ecore_spq {\n #define SPQ_RING_SIZE\t\t\\\n \t(CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element))\n /* BITS_PER_LONG */\n-#define SPQ_COMP_BMAP_SIZE\t(SPQ_RING_SIZE / (sizeof(unsigned long) * 8))\n-\tunsigned long\t\t\tp_comp_bitmap[SPQ_COMP_BMAP_SIZE];\n-\tu8\t\t\t\tcomp_bitmap_idx;\n+#define SPQ_COMP_BMAP_SIZE\t(SPQ_RING_SIZE / (sizeof(u32) * 8))\n+\tu32\t\t\tp_comp_bitmap[SPQ_COMP_BMAP_SIZE];\n+\tu8\t\t\tcomp_bitmap_idx;\n #define SPQ_COMP_BMAP_SET_BIT(p_spq, idx)\t\t\t\t\\\n \t(OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n #define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx)\t\t\t\t\\\n \t(OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n-#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx)\t\\\n-\t(OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n+#define SPQ_COMP_BMAP_GET_BIT(p_spq, idx)\t\\\n+\t(OSAL_GET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))\n \n \t/* Statistics */\n \tu32\t\t\t\tunlimited_pending_count;\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 4eb79d0..c5b909e 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -378,8 +378,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)\n \n \tif (IS_PF(edev)) {\n \t\tdev_info->b_inter_pf_switch =\n-\t\t\tOSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);\n-\t\tif (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))\n+\t\t\tOSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);\n+\t\tif (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))\n \t\t\tdev_info->b_arfs_capable = true;\n \t\tdev_info->tx_switching = false;\n \n", "prefixes": [ "v6", "5/6" ] }