Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/63763/?format=api
{ "id": 63763, "url": "http://patches.dpdk.org/api/patches/63763/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191211145004.11672-4-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191211145004.11672-4-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191211145004.11672-4-arkadiuszx.kusztal@intel.com", "date": "2019-12-11T14:50:03", "name": "[v3,3/4] common/qat: add dual thread support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "74be4d6a30c31fec6c2fa2be6f7cae7b592a5a7e", "submitter": { "id": 452, "url": "http://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191211145004.11672-4-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 7795, "url": "http://patches.dpdk.org/api/series/7795/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7795", "date": "2019-12-11T14:50:00", "name": "Add dual threading in QAT PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/7795/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63763/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EDF70A04F6;\n\tWed, 11 Dec 2019 15:51:41 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 256411BF6D;\n\tWed, 11 Dec 2019 15:51:28 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id B797B1BF30\n for <dev@dpdk.org>; Wed, 11 Dec 2019 15:51:26 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 11 Dec 2019 06:51:26 -0800", "from akusztax-mobl.ger.corp.intel.com ([10.104.12.173])\n by fmsmga001.fm.intel.com with ESMTP; 11 Dec 2019 06:51:23 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,301,1571727600\"; d=\"scan'208\";a=\"220478773\"", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "akhil.goyal@nxp.com, fiona.trahe@intel.com, declan.doherty@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Wed, 11 Dec 2019 15:50:03 +0100", "Message-Id": "<20191211145004.11672-4-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.19.1.windows.1", "In-Reply-To": "<20191211145004.11672-1-arkadiuszx.kusztal@intel.com>", "References": "<20191211145004.11672-1-arkadiuszx.kusztal@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 3/4] common/qat: add dual thread support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nRemove the limitation whereby enqueue and dequeue must be\ndone in same thread.\nThe inflight calculation is reworked to be thread-safe for 2\nthreads - note this is not general multi-thread support, i.e\nall enqueues to a qp must still be done in one thread and\nall dequeues must be done in one thread, but enqueues and\ndequeues may be in separate threads.\nDocumentation updated.\n\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n doc/guides/compressdevs/qat_comp.rst | 5 ++++-\n doc/guides/cryptodevs/qat.rst | 10 +++++++--\n drivers/common/qat/qat_qp.c | 40 +++++++++++++++++++++---------------\n drivers/common/qat/qat_qp.h | 3 ++-\n 4 files changed, 38 insertions(+), 20 deletions(-)", "diff": "diff --git a/doc/guides/compressdevs/qat_comp.rst b/doc/guides/compressdevs/qat_comp.rst\nindex 6421f76..757611a 100644\n--- a/doc/guides/compressdevs/qat_comp.rst\n+++ b/doc/guides/compressdevs/qat_comp.rst\n@@ -37,7 +37,10 @@ Limitations\n -----------\n \n * Compressdev level 0, no compression, is not supported.\n-* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).\n+* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single\n+ queue-pair all enqueues to the TX queue must be done from one thread and all dequeues\n+ from the RX queue must be done from one thread, but enqueues and dequeues may be done\n+ in different threads.)\n * No BSD support as BSD QAT kernel driver not available.\n * When using Deflate dynamic huffman encoding for compression, the input size (op.src.length)\n must be < CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE from the config file,\ndiff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex 6197875..3a4a189 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -81,7 +81,10 @@ Limitations\n * No BSD support as BSD QAT kernel driver not available.\n * ZUC EEA3/EIA3 is not supported by dh895xcc devices\n * Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros.\n-* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).\n+* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single\n+ queue-pair all enqueues to the TX queue must be done from one thread and all dequeues\n+ from the RX queue must be done from one thread, but enqueues and dequeues may be done\n+ in different threads.)\n * A GCM limitation exists, but only in the case where there are multiple\n generations of QAT devices on a single platform.\n To optimise performance, the GCM crypto session should be initialised for the\n@@ -133,7 +136,10 @@ Limitations\n ~~~~~~~~~~~\n \n * Big integers longer than 4096 bits are not supported.\n-* Queue pairs are not thread-safe (that is, within a single queue pair, RX and TX from different lcores is not supported).\n+* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single\n+ queue-pair all enqueues to the TX queue must be done from one thread and all dequeues\n+ from the RX queue must be done from one thread, but enqueues and dequeues may be done\n+ in different threads.)\n * RSA-2560, RSA-3584 are not supported\n \n .. _building_qat:\ndiff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 8e4c74a..30cdc61 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -230,7 +230,7 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \t}\n \n \tqp->mmap_bar_addr = pci_dev->mem_resource[0].addr;\n-\tqp->inflights16 = 0;\n+\tqp->enqueued = qp->dequeued = 0;\n \n \tif (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,\n \t\t\t\t\tADF_RING_DIR_TX) != 0) {\n@@ -321,7 +321,7 @@ int qat_qp_release(struct qat_qp **qp_addr)\n \t\t\t\tqp->qat_dev->qat_dev_id);\n \n \t/* Don't free memory if there are still responses to be processed */\n-\tif (qp->inflights16 == 0) {\n+\tif ((qp->enqueued - qp->dequeued) == 0) {\n \t\tqat_queue_delete(&(qp->tx_q));\n \t\tqat_queue_delete(&(qp->rx_q));\n \t} else {\n@@ -579,7 +579,6 @@ qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \tuint16_t nb_ops_possible = nb_ops;\n \tregister uint8_t *base_addr;\n \tregister uint32_t tail;\n-\tint overflow;\n \n \tif (unlikely(nb_ops == 0))\n \t\treturn 0;\n@@ -590,13 +589,25 @@ qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \ttail = queue->tail;\n \n \t/* Find how many can actually fit on the ring */\n-\ttmp_qp->inflights16 += nb_ops;\n-\toverflow = tmp_qp->inflights16 - tmp_qp->max_inflights;\n-\tif (overflow > 0) {\n-\t\ttmp_qp->inflights16 -= overflow;\n-\t\tnb_ops_possible = nb_ops - overflow;\n-\t\tif (nb_ops_possible == 0)\n-\t\t\treturn 0;\n+\t{\n+\t\t/* dequeued can only be written by one thread, but it may not\n+\t\t * be this thread. As it's 4-byte aligned it will be read\n+\t\t * atomically here by any Intel CPU.\n+\t\t * enqueued can wrap before dequeued, but cannot\n+\t\t * lap it as var size of enq/deq (uint32_t) > var size of\n+\t\t * max_inflights (uint16_t). In reality inflights is never\n+\t\t * even as big as max uint16_t, as it's <= ADF_MAX_DESC.\n+\t\t * On wrapping, the calculation still returns the correct\n+\t\t * positive value as all three vars are unsigned.\n+\t\t */\n+\t\tuint32_t inflights =\n+\t\t\ttmp_qp->enqueued - tmp_qp->dequeued;\n+\n+\t\tif ((inflights + nb_ops) > tmp_qp->max_inflights) {\n+\t\t\tnb_ops_possible = tmp_qp->max_inflights - inflights;\n+\t\t\tif (nb_ops_possible == 0)\n+\t\t\t\treturn 0;\n+\t\t}\n \t}\n \n \twhile (nb_ops_sent != nb_ops_possible) {\n@@ -605,11 +616,7 @@ qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \t\t\t\ttmp_qp->qat_dev_gen);\n \t\tif (ret != 0) {\n \t\t\ttmp_qp->stats.enqueue_err_count++;\n-\t\t\t/*\n-\t\t\t * This message cannot be enqueued,\n-\t\t\t * decrease number of ops that wasn't sent\n-\t\t\t */\n-\t\t\ttmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;\n+\t\t\t/* This message cannot be enqueued */\n \t\t\tif (nb_ops_sent == 0)\n \t\t\t\treturn 0;\n \t\t\tgoto kick_tail;\n@@ -621,6 +628,7 @@ qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \t}\n kick_tail:\n \tqueue->tail = tail;\n+\ttmp_qp->enqueued += nb_ops_sent;\n \ttmp_qp->stats.enqueued_count += nb_ops_sent;\n \ttxq_write_tail(tmp_qp, queue);\n \treturn nb_ops_sent;\n@@ -664,9 +672,9 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \t}\n \tif (resp_counter > 0) {\n \t\trx_queue->head = head;\n+\t\ttmp_qp->dequeued += resp_counter;\n \t\ttmp_qp->stats.dequeued_count += resp_counter;\n \t\trx_queue->nb_processed_responses += resp_counter;\n-\t\ttmp_qp->inflights16 -= resp_counter;\n \n \t\tif (rx_queue->nb_processed_responses >\n \t\t\t\t\t\tQAT_CSR_HEAD_WRITE_THRESH)\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex 5066f06..8b9ab79 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -63,7 +63,6 @@ struct qat_queue {\n \n struct qat_qp {\n \tvoid\t\t\t*mmap_bar_addr;\n-\tuint16_t\t\tinflights16;\n \tstruct qat_queue\ttx_q;\n \tstruct qat_queue\trx_q;\n \tstruct qat_common_stats stats;\n@@ -75,6 +74,8 @@ struct qat_qp {\n \tenum qat_service_type service_type;\n \tstruct qat_pci_device *qat_dev;\n \t/**< qat device this qp is on */\n+\tuint32_t enqueued;\n+\tuint32_t dequeued __rte_aligned(4);\n \tuint16_t max_inflights;\n } __rte_cache_aligned;\n \n", "prefixes": [ "v3", "3/4" ] }