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GET /api/patches/63748/?format=api
{ "id": 63748, "url": "http://patches.dpdk.org/api/patches/63748/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1576057875-7677-8-git-send-email-xiaojun.liu@silicom.co.il/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1576057875-7677-8-git-send-email-xiaojun.liu@silicom.co.il>", "list_archive_url": "https://inbox.dpdk.org/dev/1576057875-7677-8-git-send-email-xiaojun.liu@silicom.co.il", "date": "2019-12-11T09:52:17", "name": "[v2,7/7] net/fm10k: add dpdk port mapping", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "6b80eab67f78f26c52682531dc46cd70e404defe", "submitter": { "id": 1512, "url": "http://patches.dpdk.org/api/people/1512/?format=api", "name": "Xiaojun Liu", "email": "xiaojun.liu@silicom.co.il" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1576057875-7677-8-git-send-email-xiaojun.liu@silicom.co.il/mbox/", "series": [ { "id": 7788, "url": "http://patches.dpdk.org/api/series/7788/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7788", "date": "2019-12-11T09:51:58", "name": "support switch management", "version": 2, "mbox": "http://patches.dpdk.org/series/7788/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63748/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63748/checks/", "tags": {}, "related": [], "headers": { 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"Xiaojun Liu <xiaojun.liu@silicom.co.il>", "To": "\"xiao.w.wang@intel.com\" <xiao.w.wang@intel.com>, \"qi.z.zhang@intel.com\"\n <qi.z.zhang@intel.com>, \"ngai-mint.kwan@intel.com\"\n <ngai-mint.kwan@intel.com>, \"jakub.fornal@intel.co\" <jakub.fornal@intel.co>,\n \"jacob.e.keller@intel.com\" <jacob.e.keller@intel.com>", "CC": "\"dev@dpdk.org\" <dev@dpdk.org>, Xiaojun Liu <xiaojun.liu@silicom.co.il>", "Thread-Topic": "[PATCH v2 7/7] net/fm10k: add dpdk port mapping", "Thread-Index": "AQHVsAis7rZAir9v5kiDH0nbx/RvyA==", "Date": "Wed, 11 Dec 2019 09:52:17 +0000", "Message-ID": "<1576057875-7677-8-git-send-email-xiaojun.liu@silicom.co.il>", "References": "<xiaojun.liu@silicom.co.il>\n <1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il>", "In-Reply-To": "<1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": 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"c9e326d8-ce47-4930-8612-cc99d3c87ad1", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n KRsShHFot3kRJqOee9BH8ehF/p/yrVvlLo5jZ/KbVZ5hY5L6zycP1oadLjx+oML0xbyaqfxm/l68zA46FtpvMSm/i37LO6akgFiWQ6KQIYE=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB7PR04MB5050", "Subject": "[dpdk-dev] [PATCH v2 7/7] net/fm10k: add dpdk port mapping", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Modify fm10k/fm10k_ethdev.c.\nAdd dpdk port and pf mapping, so\nthe dpdk port can map to a specific pf\nand 1 dpdk port can map to 2 pf to get\ntotal 100G throughput.\n\nTo avoid configuration for both kernel driver\nand userspace SDK outside DPDK, we add switch\nmanagement in FM10K DPDK PMD driver.\nTo enable switch management, you need add\nCONFIG_RTE_FM10K_MANAGEMENT=y in\nconfig/common_linux when building.\n\nSigned-off-by: Xiaojun Liu <xiaojun.liu@silicom.co.il>\n---\n drivers/net/fm10k/fm10k_ethdev.c | 322 +++++++++++++++++++++++++++++++++++----\n 1 file changed, 294 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c\nindex 1c01684..8af97a7 100644\n--- a/drivers/net/fm10k/fm10k_ethdev.c\n+++ b/drivers/net/fm10k/fm10k_ethdev.c\n@@ -517,6 +517,15 @@ struct fm10k_xstats_name_off {\n \tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n \tuint32_t mrqc, *key, i, reta, j;\n \tuint64_t hf;\n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tuint16_t nb_rx_queues = dev->data->nb_rx_queues;\n+\tint mapped_num;\n+\tstruct fm10k_hw *mapped_hws[2];\n+\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(hw, mapped_hws);\n+\tif (mapped_num == 2)\n+\t\tnb_rx_queues /= 2;\n+#endif\n \n #define RSS_KEY_SIZE 40\n \tstatic uint8_t rss_intel_key[RSS_KEY_SIZE] = {\n@@ -646,27 +655,48 @@ struct fm10k_xstats_name_off {\n static int\n fm10k_dev_tx_init(struct rte_eth_dev *dev)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t data;\n+#endif\n \tint i, ret;\n+\tuint16_t hw_queue_id;\n \tstruct fm10k_tx_queue *txq;\n \tuint64_t base_addr;\n \tuint32_t size;\n \n+#ifndef ENABLE_FM10K_MANAGEMENT\n \t/* Disable TXINT to avoid possible interrupt */\n \tfor (i = 0; i < hw->mac.max_queues; i++)\n \t\tFM10K_WRITE_REG(hw, FM10K_TXINT(i),\n \t\t\t\t3 << FM10K_TXINT_TIMER_SHIFT);\n+#else\n+\tfm10k_switch_dpdk_tx_queue_num_set(unmap_hw,\n+\t\tdev->data->nb_tx_queues);\n+#endif\n \n \t/* Setup TX queue */\n \tfor (i = 0; i < dev->data->nb_tx_queues; ++i) {\n+\t\thw_queue_id = i;\n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\ti, dev->data->nb_tx_queues,\n+\t\t\t&hw, &hw_queue_id);\n+#endif\n \t\ttxq = dev->data->tx_queues[i];\n \t\tbase_addr = txq->hw_ring_phys_addr;\n \t\tsize = txq->nb_desc * sizeof(struct fm10k_tx_desc);\n \n \t\t/* disable queue to avoid issues while updating state */\n-\t\tret = tx_queue_disable(hw, i);\n+\t\tret = tx_queue_disable(hw, hw_queue_id);\n \t\tif (ret) {\n-\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\t\"failed to disable queue %d\",\n+\t\t\t\t\thw_queue_id);\n \t\t\treturn -1;\n \t\t}\n \t\t/* Enable use of FTAG bit in TX descriptor, PFVTCTL\n@@ -674,7 +704,7 @@ struct fm10k_xstats_name_off {\n \t\t */\n \t\tif (fm10k_check_ftag(dev->device->devargs)) {\n \t\t\tif (hw->mac.type == fm10k_mac_pf) {\n-\t\t\t\tFM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),\n+\t\t\t\tFM10K_WRITE_REG(hw, FM10K_PFVTCTL(hw_queue_id),\n \t\t\t\t\t\tFM10K_PFVTCTL_FTAG_DESC_ENABLE);\n \t\t\t\tPMD_INIT_LOG(DEBUG, \"FTAG mode is enabled\");\n \t\t\t} else {\n@@ -684,15 +714,25 @@ struct fm10k_xstats_name_off {\n \t\t}\n \n \t\t/* set location and size for descriptor ring */\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(hw_queue_id),\n \t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(hw_queue_id),\n \t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n-\t\tFM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);\n+\t\tFM10K_WRITE_REG(hw, FM10K_TDLEN(hw_queue_id), size);\n \n \t\t/* assign default SGLORT for each TX queue by PF */\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \t\tif (hw->mac.type == fm10k_mac_pf)\n-\t\t\tFM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);\n+\t\t\tFM10K_WRITE_REG(hw,\n+\t\t\t\t\tFM10K_TX_SGLORT(hw_queue_id),\n+\t\t\t\t\thw->mac.dglort_map);\n+#else\n+\t\tif (hw->mac.type == fm10k_mac_pf) {\n+\t\t\tdata = FM10K_SW_MAKE_REG_FIELD\n+\t\t\t\t\t(TX_SGLORT_SGLORT, hw->mac.dglort_map);\n+\t\t\tFM10K_WRITE_REG(hw, FM10K_TX_SGLORT(hw_queue_id), data);\n+\t\t}\n+#endif\n \t}\n \n \t/* set up vector or scalar TX function as appropriate */\n@@ -704,19 +744,27 @@ struct fm10k_xstats_name_off {\n static int\n fm10k_dev_rx_init(struct rte_eth_dev *dev)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct fm10k_macvlan_filter_info *macvlan;\n \tstruct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pdev->intr_handle;\n+\tuint32_t logic_port = hw->mac.dglort_map;\n+\tuint16_t queue_stride = 0;\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#endif\n \tint i, ret;\n+\tuint16_t hw_queue_id;\n \tstruct fm10k_rx_queue *rxq;\n \tuint64_t base_addr;\n \tuint32_t size;\n \tuint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;\n-\tuint32_t logic_port = hw->mac.dglort_map;\n \tuint16_t buf_size;\n-\tuint16_t queue_stride = 0;\n \n+#ifndef ENABLE_FM10K_MANAGEMENT\n \t/* enable RXINT for interrupt mode */\n \ti = 0;\n \tif (rte_intr_dp_is_en(intr_handle)) {\n@@ -736,26 +784,36 @@ struct fm10k_xstats_name_off {\n \tfor (; i < hw->mac.max_queues; i++)\n \t\tFM10K_WRITE_REG(hw, FM10K_RXINT(i),\n \t\t\t3 << FM10K_RXINT_TIMER_SHIFT);\n+#else\n+\tfm10k_switch_dpdk_rx_queue_num_set(unmap_hw, dev->data->nb_rx_queues);\n+#endif\n \n \t/* Setup RX queues */\n \tfor (i = 0; i < dev->data->nb_rx_queues; ++i) {\n+\t\thw_queue_id = i;\n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\ti, dev->data->nb_rx_queues, &hw, &hw_queue_id);\n+#endif\n \t\trxq = dev->data->rx_queues[i];\n \t\tbase_addr = rxq->hw_ring_phys_addr;\n \t\tsize = rxq->nb_desc * sizeof(union fm10k_rx_desc);\n \n \t\t/* disable queue to avoid issues while updating state */\n-\t\tret = rx_queue_disable(hw, i);\n+\t\tret = rx_queue_disable(hw, hw_queue_id);\n \t\tif (ret) {\n-\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\t\"failed to disable queue %d\",\n+\t\t\t\t\thw_queue_id);\n \t\t\treturn -1;\n \t\t}\n \n \t\t/* Setup the Base and Length of the Rx Descriptor Ring */\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(hw_queue_id),\n \t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(hw_queue_id),\n \t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n-\t\tFM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);\n+\t\tFM10K_WRITE_REG(hw, FM10K_RDLEN(hw_queue_id), size);\n \n \t\t/* Configure the Rx buffer size for one buff without split */\n \t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -\n@@ -769,7 +827,7 @@ struct fm10k_xstats_name_off {\n \t\t */\n \t\tbuf_size -= FM10K_RX_DATABUF_ALIGN;\n \n-\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i),\n+\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(hw_queue_id),\n \t\t\t\t(buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |\n \t\t\t\tFM10K_SRRCTL_LOOPBACK_SUPPRESS);\n \n@@ -779,9 +837,9 @@ struct fm10k_xstats_name_off {\n \t\t\trxq->offloads & DEV_RX_OFFLOAD_SCATTER) {\n \t\t\tuint32_t reg;\n \t\t\tdev->data->scattered_rx = 1;\n-\t\t\treg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));\n+\t\t\treg = FM10K_READ_REG(hw, FM10K_SRRCTL(hw_queue_id));\n \t\t\treg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;\n-\t\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);\n+\t\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(hw_queue_id), reg);\n \t\t}\n \n \t\t/* Enable drop on empty, it's RO for VF */\n@@ -801,6 +859,7 @@ struct fm10k_xstats_name_off {\n \t/* update RX_SGLORT for loopback suppress*/\n \tif (hw->mac.type != fm10k_mac_pf)\n \t\treturn 0;\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n \tif (macvlan->nb_queue_pools)\n \t\tqueue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;\n@@ -809,6 +868,7 @@ struct fm10k_xstats_name_off {\n \t\t\tlogic_port++;\n \t\tFM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);\n \t}\n+#endif\n \n \treturn 0;\n }\n@@ -816,13 +876,31 @@ struct fm10k_xstats_name_off {\n static int\n fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret;\n+#endif\n \tint err;\n \tuint32_t reg;\n \tstruct fm10k_rx_queue *rxq;\n+\tuint16_t hw_queue_id = rx_queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tret = fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\trx_queue_id, dev->data->nb_rx_queues,\n+\t\t\t&hw, &hw_queue_id);\n+\tif (ret < 0)\n+\t\treturn -EIO;\n+\telse if (ret != 1)\t/* reference port's queue don't need start */\n+\t\treturn 0;\n+#endif\n+\n \trxq = dev->data->rx_queues[rx_queue_id];\n \terr = rx_queue_reset(rxq);\n \tif (err == -ENOMEM) {\n@@ -841,23 +919,23 @@ struct fm10k_xstats_name_off {\n \t * this comment and the following two register writes when the\n \t * emulation platform is no longer being used.\n \t */\n-\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n+\tFM10K_WRITE_REG(hw, FM10K_RDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_RDT(hw_queue_id), rxq->nb_desc - 1);\n \n \t/* Set PF ownership flag for PF devices */\n-\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));\n+\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(hw_queue_id));\n \tif (hw->mac.type == fm10k_mac_pf)\n \t\treg |= FM10K_RXQCTL_PF;\n \treg |= FM10K_RXQCTL_ENABLE;\n \t/* enable RX queue */\n-\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);\n+\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(hw_queue_id), reg);\n \tFM10K_WRITE_FLUSH(hw);\n \n \t/* Setup the HW Rx Head and Tail Descriptor Pointers\n \t * Note: this must be done AFTER the queue is enabled\n \t */\n-\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n+\tFM10K_WRITE_REG(hw, FM10K_RDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_RDT(hw_queue_id), rxq->nb_desc - 1);\n \tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n \treturn 0;\n@@ -883,22 +961,39 @@ struct fm10k_xstats_name_off {\n static int\n fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint ret;\n+#endif\n \t/** @todo - this should be defined in the shared code */\n #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY\t0x00010000\n \tuint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;\n \tstruct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];\n+\tuint16_t hw_queue_id = tx_queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tret = fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\ttx_queue_id, dev->data->nb_tx_queues, &hw, &hw_queue_id);\n+\tif (ret < 0)\n+\t\treturn -EIO;\n+\telse if (ret != 1)\n+\t\treturn 0;\n+#endif\n+\n \tq->ops->reset(q);\n \n \t/* reset head and tail pointers */\n-\tFM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);\n-\tFM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_TDH(hw_queue_id), 0);\n+\tFM10K_WRITE_REG(hw, FM10K_TDT(hw_queue_id), 0);\n \n \t/* enable TX queue */\n-\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),\n+\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(hw_queue_id),\n \t\t\t\tFM10K_TXDCTL_ENABLE | txdctl);\n \tFM10K_WRITE_FLUSH(hw);\n \tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n@@ -1089,9 +1184,22 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n {\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tint i, diag;\n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tstruct fm10k_hw *mapped_hws[2];\n+\tint j, mapped_num;\n+\tuint32_t data;\n+#endif\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(hw, mapped_hws);\n+\tif (mapped_num < 0 || mapped_num > 2)\n+\t\treturn -EIO;\n+#endif\n+\n+\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \t/* stop, init, then start the hw */\n \tdiag = fm10k_stop_hw(hw);\n \tif (diag != FM10K_SUCCESS) {\n@@ -1110,6 +1218,62 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n \t\tPMD_INIT_LOG(ERR, \"Hardware start failed: %d\", diag);\n \t\treturn -EIO;\n \t}\n+#else\n+\tfor (j = 0; j < mapped_num; j++) {\n+\t\tstruct rte_pci_device *pdev =\n+\t\t\tRTE_ETH_DEV_TO_PCI((struct rte_eth_dev *)\n+\t\t\t(fm10k_switch_dpdk_port_rte_dev_get(mapped_hws[j])));\n+\t\tstruct rte_intr_handle *intr_handle = &pdev->intr_handle;\n+\n+\t\t/* stop, init, then start the hw */\n+\t\tdiag = fm10k_stop_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware stop failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tdiag = fm10k_init_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware init failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tdiag = fm10k_start_hw(mapped_hws[j]);\n+\t\tif (diag != FM10K_SUCCESS) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Hardware start failed: %d\", diag);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\t/* Disable TXINT to avoid possible interrupt */\n+\t\tfor (i = 0; i < hw->mac.max_queues; i++)\n+\t\t\tFM10K_WRITE_REG(mapped_hws[j], FM10K_TXINT(i),\n+\t\t\t\t\t3 << FM10K_TXINT_TIMER_SHIFT);\n+\n+\t\t/* enable RXINT for interrupt mode */\n+\t\ti = 0;\n+\t\tif (rte_intr_dp_is_en(intr_handle)) {\n+\t\t\tfor (; i < dev->data->nb_rx_queues; i++) {\n+\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_RXINT(i), Q2V(pdev, i));\n+\t\t\t\tif (mapped_hws[j]->mac.type == fm10k_mac_pf)\n+\t\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_ITR(Q2V(pdev, i)),\n+\t\t\t\t\t\tFM10K_ITR_AUTOMASK |\n+\t\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n+\t\t\t\telse\n+\t\t\t\t\tFM10K_WRITE_REG(mapped_hws[j],\n+\t\t\t\t\t\tFM10K_VFITR(Q2V(pdev, i)),\n+\t\t\t\t\t\tFM10K_ITR_AUTOMASK |\n+\t\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Disable other RXINT to avoid possible interrupt */\n+\t\tfor (; i < hw->mac.max_queues; i++)\n+\t\t\tFM10K_WRITE_REG(mapped_hws[j], FM10K_RXINT(i),\n+\t\t\t\t3 << FM10K_RXINT_TIMER_SHIFT);\n+\t}\n+#endif\n \n \tdiag = fm10k_dev_tx_init(dev);\n \tif (diag) {\n@@ -1161,12 +1325,32 @@ static inline int fm10k_glort_valid(struct fm10k_hw *hw)\n \t\t}\n \t}\n \n+#ifndef ENABLE_FM10K_MANAGEMENT\n \t/* Update default vlan when not in VMDQ mode */\n \tif (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))\n \t\tfm10k_vlan_filter_set(dev, hw->mac.default_vid, true);\n+#endif\n \n \tfm10k_link_update(dev, 0);\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\t/* Admit all VLANs */\n+\tfor (j = 0; j <= 64; j++) {\n+\t\tfor (i = 0; i < FM10K_SW_VLAN_TABLE_ENTRIES; i++)\n+\t\t\tFM10K_WRITE_REG(hw,\n+\t\t\t\t\tFM10K_SW_VLAN_TABLE_ENTRY(j, i),\n+\t\t\t\t\t0xffffffff);\n+\t}\n+\n+\t/* Disable PEP 1loopback */\n+\t/* XXX Does this need to be done by the master\n+\t * PEP while the switch is in reset?\n+\t */\n+\tdata = FM10K_READ_REG(hw, FM10K_CTRL_EXT);\n+\tdata &= ~FM10K_SW_CTRL_EXT_SWITCH_LOOPBACK;\n+\tFM10K_WRITE_REG(hw, FM10K_CTRL_EXT, data);\n+#endif\n+\n \treturn 0;\n }\n \n@@ -1327,17 +1511,41 @@ static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n {\n \tuint64_t ipackets, opackets, ibytes, obytes, imissed;\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw =\n \t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct fm10k_hw *mapped_hws[2];\n+\tint mapped_num;\n+\tuint16_t hw_queue_id;\n+#endif\n \tstruct fm10k_hw_stats *hw_stats =\n \t\tFM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n \tint i;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tfm10k_update_hw_stats(hw, hw_stats);\n+#else\n+\tmapped_num = fm10k_switch_dpdk_mapped_hw_get(unmap_hw, mapped_hws);\n+\tif (mapped_num < 0 || mapped_num > 2)\n+\t\treturn -EIO;\n+\n+\tfor (i = 0; i < mapped_num; i++) {\n+\t\tstruct rte_eth_dev *mydev =\n+\t\t\tfm10k_switch_dpdk_port_rte_dev_get(mapped_hws[i]);\n+\t\thw_stats = FM10K_DEV_PRIVATE_TO_STATS(mydev->data->dev_private);\n+\t\tfm10k_update_hw_stats(mapped_hws[i], hw_stats);\n+\t}\n+#endif\n \n \tipackets = opackets = ibytes = obytes = imissed = 0;\n+\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tfor (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&\n \t\t(i < hw->mac.max_queues); ++i) {\n \t\tstats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;\n@@ -1351,6 +1559,36 @@ static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\n \t\tobytes += stats->q_obytes[i];\n \t\timissed += stats->q_errors[i];\n \t}\n+#else\n+\tif (mapped_num)\t{\n+\t\tfor (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&\n+\t\t\t(i < unmap_hw->mac.max_queues); ++i) {\n+\t\t\thw_queue_id = i;\n+\t\t\tfm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\t\t\ti, unmap_hw->mac.max_queues,\n+\t\t\t\t\t&hw, &hw_queue_id);\n+\t\t\tif (mapped_hws[1]) {\n+\t\t\t\tstruct rte_eth_dev *mydev;\n+\t\t\t\tmydev = fm10k_switch_dpdk_port_rte_dev_get(hw);\n+\t\t\t\thw_stats =\n+\t\t\t\t\t\tFM10K_DEV_PRIVATE_TO_STATS\n+\t\t\t\t\t\t(mydev->data->dev_private);\n+\t\t\t}\n+\t\t\tstats->q_ipackets[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].rx_packets.count;\n+\t\t\tstats->q_opackets[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].tx_packets.count;\n+\t\t\tstats->q_ibytes[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].rx_bytes.count;\n+\t\t\tstats->q_obytes[i] =\n+\t\t\t\thw_stats->q[hw_queue_id].tx_bytes.count;\n+\t\t\tipackets += stats->q_ipackets[i];\n+\t\t\topackets += stats->q_opackets[i];\n+\t\t\tibytes += stats->q_ibytes[i];\n+\t\t\tobytes += stats->q_obytes[i];\n+\t\t}\n+\t}\n+#endif\n \tstats->ipackets = ipackets;\n \tstats->opackets = opackets;\n \tstats->ibytes = ibytes;\n@@ -1821,15 +2059,29 @@ static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)\n \tuint16_t nb_desc, unsigned int socket_id,\n \tconst struct rte_eth_rxconf *conf, struct rte_mempool *mp)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#endif\n \tstruct fm10k_dev_info *dev_info =\n \t\tFM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);\n \tstruct fm10k_rx_queue *q;\n \tconst struct rte_memzone *mz;\n \tuint64_t offloads;\n+\tuint16_t hw_queue_id = queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tif (fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\tqueue_id, dev->data->nb_rx_queues,\n+\t\t\t&hw, &hw_queue_id) < 0)\n+\t\treturn -EIO;\n+#endif\n+\n \toffloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;\n \n \t/* make sure the mempool element size can account for alignment. */\n@@ -1875,7 +2127,7 @@ static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)\n \tq->port_id = dev->data->port_id;\n \tq->queue_id = queue_id;\n \tq->tail_ptr = (volatile uint32_t *)\n-\t\t&((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];\n+\t\t&((uint32_t *)hw->hw_addr)[FM10K_RDT(hw_queue_id)];\n \tq->offloads = offloads;\n \tif (handle_rxconf(q, conf))\n \t\treturn -EINVAL;\n@@ -2010,13 +2262,27 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \tuint16_t nb_desc, unsigned int socket_id,\n \tconst struct rte_eth_txconf *conf)\n {\n+#ifndef ENABLE_FM10K_MANAGEMENT\n \tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#else\n+\tstruct fm10k_hw *hw;\n+\tstruct fm10k_hw *unmap_hw =\n+\t\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+#endif\n \tstruct fm10k_tx_queue *q;\n \tconst struct rte_memzone *mz;\n \tuint64_t offloads;\n+\tuint16_t hw_queue_id = queue_id;\n \n \tPMD_INIT_FUNC_TRACE();\n \n+#ifdef ENABLE_FM10K_MANAGEMENT\n+\tif (fm10k_switch_dpdk_hw_queue_map(unmap_hw,\n+\t\t\tqueue_id, dev->data->nb_tx_queues,\n+\t\t\t&hw, &hw_queue_id) < 0)\n+\t\treturn -EIO;\n+#endif\n+\n \toffloads = conf->offloads | dev->data->dev_conf.txmode.offloads;\n \n \t/* make sure a valid number of descriptors have been requested */\n@@ -2058,7 +2324,7 @@ static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \tq->offloads = offloads;\n \tq->ops = &def_txq_ops;\n \tq->tail_ptr = (volatile uint32_t *)\n-\t\t&((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];\n+\t\t&((uint32_t *)hw->hw_addr)[FM10K_TDT(hw_queue_id)];\n \tif (handle_txconf(q, conf))\n \t\treturn -EINVAL;\n \n", "prefixes": [ "v2", "7/7" ] }