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GET /api/patches/63679/?format=api
{ "id": 63679, "url": "http://patches.dpdk.org/api/patches/63679/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191209214656.27347-3-cardigliano@ntop.org/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191209214656.27347-3-cardigliano@ntop.org>", "list_archive_url": "https://inbox.dpdk.org/dev/20191209214656.27347-3-cardigliano@ntop.org", "date": "2019-12-09T21:46:41", "name": "[v3,02/17] net/ionic: add hardware structures definitions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8b3ea45ba05e6d9cb1b313120a4b55c95478342e", "submitter": { "id": 1465, "url": "http://patches.dpdk.org/api/people/1465/?format=api", "name": "Alfredo Cardigliano", "email": "cardigliano@ntop.org" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191209214656.27347-3-cardigliano@ntop.org/mbox/", "series": [ { "id": 7760, "url": "http://patches.dpdk.org/api/series/7760/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7760", "date": "2019-12-09T21:46:39", "name": "Introduces net/ionic PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/7760/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63679/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63679/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3267EA04B3;\n\tMon, 9 Dec 2019 22:48:51 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0892D1BE84;\n\tMon, 9 Dec 2019 22:48:36 +0100 (CET)", "from mail.ntop.org (mail-digitalocean.ntop.org [167.99.215.164])\n by dpdk.org (Postfix) with ESMTP id 0073E1F5\n for <dev@dpdk.org>; Mon, 9 Dec 2019 22:48:29 +0100 (CET)", "from devele.ntop.org (net-93-145-196-230.cust.vodafonedsl.it\n [93.145.196.230])\n by mail.ntop.org (Postfix) with ESMTPSA id 848954090E;\n Mon, 9 Dec 2019 22:48:29 +0100 (CET)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=ntop.org; s=mail;\n t=1575928109; bh=7KWrYkDd2/d9cbOxhkEf0J4oio63Xc/Yq9+woc73LQo=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=mbXetdpuCnVHfucQ2NKAzWs6iLmLcUNMmuLbUh+n8tyU/ml5/VRifnWp1s8rtpaHZ\n YWNN6/Ac6KbQL48kirVvto1tuukc8SjGkC/Hl20Ko0uhyuny9BqjmQMBrhWVBMiXYc\n zm6LfmjtJmhbt48AqklAJzhkVUJjKxd094/JfwiA=", "From": "Alfredo Cardigliano <cardigliano@ntop.org>", "To": "Alfredo Cardigliano <cardigliano@ntop.org>", "Cc": "dev@dpdk.org", "Date": "Mon, 9 Dec 2019 22:46:41 +0100", "Message-Id": "<20191209214656.27347-3-cardigliano@ntop.org>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20191209214656.27347-1-cardigliano@ntop.org>", "References": "<20191209214656.27347-1-cardigliano@ntop.org>", "Subject": "[dpdk-dev] [PATCH v3 02/17] net/ionic: add hardware structures\n\tdefinitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add hardware structures and message commands definitions for\nPensando network adapters.\n\nSigned-off-by: Alfredo Cardigliano <cardigliano@ntop.org>\nReviewed-by: Shannon Nelson <snelson@pensando.io>\n---\n drivers/net/ionic/ionic_if.h | 2491 ++++++++++++++++++++++++++++++++++\n 1 file changed, 2491 insertions(+)\n create mode 100644 drivers/net/ionic/ionic_if.h", "diff": "diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h\nnew file mode 100644\nindex 000000000..5f31ec034\n--- /dev/null\n+++ b/drivers/net/ionic/ionic_if.h\n@@ -0,0 +1,2491 @@\n+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */\n+/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */\n+\n+#ifndef _IONIC_IF_H_\n+#define _IONIC_IF_H_\n+\n+#pragma pack(push, 1)\n+\n+#define IONIC_DEV_INFO_SIGNATURE\t\t0x44455649 /* 'DEVI' */\n+#define IONIC_DEV_INFO_VERSION\t\t\t1\n+#define IONIC_IFNAMSIZ\t\t\t\t16\n+\n+/**\n+ * Commands\n+ */\n+enum ionic_cmd_opcode {\n+\tIONIC_CMD_NOP\t\t\t\t= 0,\n+\n+\t/* Device commands */\n+\tIONIC_CMD_IDENTIFY\t\t\t= 1,\n+\tIONIC_CMD_INIT\t\t\t\t= 2,\n+\tIONIC_CMD_RESET\t\t\t\t= 3,\n+\tIONIC_CMD_GETATTR\t\t\t= 4,\n+\tIONIC_CMD_SETATTR\t\t\t= 5,\n+\n+\t/* Port commands */\n+\tIONIC_CMD_PORT_IDENTIFY\t\t\t= 10,\n+\tIONIC_CMD_PORT_INIT\t\t\t= 11,\n+\tIONIC_CMD_PORT_RESET\t\t\t= 12,\n+\tIONIC_CMD_PORT_GETATTR\t\t\t= 13,\n+\tIONIC_CMD_PORT_SETATTR\t\t\t= 14,\n+\n+\t/* LIF commands */\n+\tIONIC_CMD_LIF_IDENTIFY\t\t\t= 20,\n+\tIONIC_CMD_LIF_INIT\t\t\t= 21,\n+\tIONIC_CMD_LIF_RESET\t\t\t= 22,\n+\tIONIC_CMD_LIF_GETATTR\t\t\t= 23,\n+\tIONIC_CMD_LIF_SETATTR\t\t\t= 24,\n+\n+\tIONIC_CMD_RX_MODE_SET\t\t\t= 30,\n+\tIONIC_CMD_RX_FILTER_ADD\t\t\t= 31,\n+\tIONIC_CMD_RX_FILTER_DEL\t\t\t= 32,\n+\n+\t/* Queue commands */\n+\tIONIC_CMD_Q_INIT\t\t\t= 40,\n+\tIONIC_CMD_Q_CONTROL\t\t\t= 41,\n+\n+\t/* RDMA commands */\n+\tIONIC_CMD_RDMA_RESET_LIF\t\t= 50,\n+\tIONIC_CMD_RDMA_CREATE_EQ\t\t= 51,\n+\tIONIC_CMD_RDMA_CREATE_CQ\t\t= 52,\n+\tIONIC_CMD_RDMA_CREATE_ADMINQ\t\t= 53,\n+\n+\t/* QoS commands */\n+\tIONIC_CMD_QOS_CLASS_IDENTIFY\t\t= 240,\n+\tIONIC_CMD_QOS_CLASS_INIT\t\t= 241,\n+\tIONIC_CMD_QOS_CLASS_RESET\t\t= 242,\n+\n+\t/* Firmware commands */\n+\tIONIC_CMD_FW_DOWNLOAD\t\t\t= 254,\n+\tIONIC_CMD_FW_CONTROL\t\t\t= 255,\n+};\n+\n+/**\n+ * Command Return codes\n+ */\n+enum ionic_status_code {\n+\tIONIC_RC_SUCCESS\t= 0,\t/* Success */\n+\tIONIC_RC_EVERSION\t= 1,\t/* Incorrect version for request */\n+\tIONIC_RC_EOPCODE\t= 2,\t/* Invalid cmd opcode */\n+\tIONIC_RC_EIO\t\t= 3,\t/* I/O error */\n+\tIONIC_RC_EPERM\t\t= 4,\t/* Permission denied */\n+\tIONIC_RC_EQID\t\t= 5,\t/* Bad qid */\n+\tIONIC_RC_EQTYPE\t\t= 6,\t/* Bad qtype */\n+\tIONIC_RC_ENOENT\t\t= 7,\t/* No such element */\n+\tIONIC_RC_EINTR\t\t= 8,\t/* operation interrupted */\n+\tIONIC_RC_EAGAIN\t\t= 9,\t/* Try again */\n+\tIONIC_RC_ENOMEM\t\t= 10,\t/* Out of memory */\n+\tIONIC_RC_EFAULT\t\t= 11,\t/* Bad address */\n+\tIONIC_RC_EBUSY\t\t= 12,\t/* Device or resource busy */\n+\tIONIC_RC_EEXIST\t\t= 13,\t/* object already exists */\n+\tIONIC_RC_EINVAL\t\t= 14,\t/* Invalid argument */\n+\tIONIC_RC_ENOSPC\t\t= 15,\t/* No space left or alloc failure */\n+\tIONIC_RC_ERANGE\t\t= 16,\t/* Parameter out of range */\n+\tIONIC_RC_BAD_ADDR\t= 17,\t/* Descriptor contains a bad ptr */\n+\tIONIC_RC_DEV_CMD\t= 18,\t/* Device cmd attempted on AdminQ */\n+\tIONIC_RC_ENOSUPP\t= 19,\t/* Operation not supported */\n+\tIONIC_RC_ERROR\t\t= 29,\t/* Generic error */\n+\n+\tIONIC_RC_ERDMA\t\t= 30,\t/* Generic RDMA error */\n+};\n+\n+enum ionic_notifyq_opcode {\n+\tIONIC_EVENT_LINK_CHANGE\t\t= 1,\n+\tIONIC_EVENT_RESET\t\t= 2,\n+\tIONIC_EVENT_HEARTBEAT\t\t= 3,\n+\tIONIC_EVENT_LOG\t\t\t= 4,\n+};\n+\n+/**\n+ * struct cmd - General admin command format\n+ * @opcode: Opcode for the command\n+ * @lif_index: LIF index\n+ * @cmd_data: Opcode-specific command bytes\n+ */\n+struct ionic_admin_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\tu8 cmd_data[60];\n+};\n+\n+/**\n+ * struct ionic_admin_comp - General admin command completion format\n+ * @status: The status of the command (enum status_code)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @cmd_data: Command-specific bytes.\n+ * @color: Color bit. (Always 0 for commands issued to the\n+ * Device Cmd Registers.)\n+ */\n+struct ionic_admin_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 cmd_data[11];\n+\tu8 color;\n+#define IONIC_COMP_COLOR_MASK 0x80\n+};\n+\n+static inline u8 color_match(u8 color, u8 done_color)\n+{\n+\treturn (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;\n+}\n+\n+/**\n+ * struct ionic_nop_cmd - NOP command\n+ * @opcode: opcode\n+ */\n+struct ionic_nop_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[63];\n+};\n+\n+/**\n+ * struct ionic_nop_comp - NOP command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_nop_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+/**\n+ * struct ionic_dev_init_cmd - Device init command\n+ * @opcode: opcode\n+ * @type: device type\n+ */\n+struct ionic_dev_init_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct init_comp - Device init command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_dev_init_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+/**\n+ * struct ionic_dev_reset_cmd - Device reset command\n+ * @opcode: opcode\n+ */\n+struct ionic_dev_reset_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[63];\n+};\n+\n+/**\n+ * struct reset_comp - Reset command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_dev_reset_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+#define IONIC_IDENTITY_VERSION_1\t1\n+\n+/**\n+ * struct ionic_dev_identify_cmd - Driver/device identify command\n+ * @opcode: opcode\n+ * @ver: Highest version of identify supported by driver\n+ */\n+struct ionic_dev_identify_cmd {\n+\tu8 opcode;\n+\tu8 ver;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct dev_identify_comp - Driver/device identify command completion\n+ * @status: The status of the command (enum status_code)\n+ * @ver: Version of identify returned by device\n+ */\n+struct ionic_dev_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd[14];\n+};\n+\n+enum ionic_os_type {\n+\tIONIC_OS_TYPE_LINUX = 1,\n+\tIONIC_OS_TYPE_WIN = 2,\n+\tIONIC_OS_TYPE_DPDK = 3,\n+\tIONIC_OS_TYPE_FREEBSD = 4,\n+\tIONIC_OS_TYPE_IPXE = 5,\n+\tIONIC_OS_TYPE_ESXI = 6,\n+};\n+\n+/**\n+ * union drv_identity - driver identity information\n+ * @os_type: OS type (see enum os_type)\n+ * @os_dist: OS distribution, numeric format\n+ * @os_dist_str: OS distribution, string format\n+ * @kernel_ver: Kernel version, numeric format\n+ * @kernel_ver_str: Kernel version, string format\n+ * @driver_ver_str: Driver version, string format\n+ */\n+union ionic_drv_identity {\n+\tstruct {\n+\t\t__le32 os_type;\n+\t\t__le32 os_dist;\n+\t\tchar os_dist_str[128];\n+\t\t__le32 kernel_ver;\n+\t\tchar kernel_ver_str[32];\n+\t\tchar driver_ver_str[32];\n+\t};\n+\t__le32 words[512];\n+};\n+\n+/**\n+ * union dev_identity - device identity information\n+ * @version: Version of device identify\n+ * @type: Identify type (0 for now)\n+ * @nports: Number of ports provisioned\n+ * @nlifs: Number of LIFs provisioned\n+ * @nintrs: Number of interrupts provisioned\n+ * @ndbpgs_per_lif: Number of doorbell pages per LIF\n+ * @intr_coal_mult: Interrupt coalescing multiplication factor.\n+ * Scale user-supplied interrupt coalescing\n+ * value in usecs to device units using:\n+ * device units = usecs * mult / div\n+ * @intr_coal_div: Interrupt coalescing division factor.\n+ * Scale user-supplied interrupt coalescing\n+ * value in usecs to device units using:\n+ * device units = usecs * mult / div\n+ *\n+ */\n+union ionic_dev_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 type;\n+\t\tu8 rsvd[2];\n+\t\tu8 nports;\n+\t\tu8 rsvd2[3];\n+\t\t__le32 nlifs;\n+\t\t__le32 nintrs;\n+\t\t__le32 ndbpgs_per_lif;\n+\t\t__le32 intr_coal_mult;\n+\t\t__le32 intr_coal_div;\n+\t};\n+\t__le32 words[512];\n+};\n+\n+enum ionic_lif_type {\n+\tIONIC_LIF_TYPE_CLASSIC = 0,\n+\tIONIC_LIF_TYPE_MACVLAN = 1,\n+\tIONIC_LIF_TYPE_NETQUEUE = 2,\n+};\n+\n+/**\n+ * struct ionic_lif_identify_cmd - lif identify command\n+ * @opcode: opcode\n+ * @type: lif type (enum lif_type)\n+ * @ver: version of identify returned by device\n+ */\n+struct ionic_lif_identify_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\tu8 ver;\n+\tu8 rsvd[61];\n+};\n+\n+/**\n+ * struct ionic_lif_identify_comp - lif identify command completion\n+ * @status: status of the command (enum status_code)\n+ * @ver: version of identify returned by device\n+ */\n+struct ionic_lif_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd2[14];\n+};\n+\n+enum ionic_lif_capability {\n+\tIONIC_LIF_CAP_ETH = BIT(0),\n+\tIONIC_LIF_CAP_RDMA = BIT(1),\n+};\n+\n+/**\n+ * Logical Queue Types\n+ */\n+enum ionic_logical_qtype {\n+\tIONIC_QTYPE_ADMINQ = 0,\n+\tIONIC_QTYPE_NOTIFYQ = 1,\n+\tIONIC_QTYPE_RXQ = 2,\n+\tIONIC_QTYPE_TXQ = 3,\n+\tIONIC_QTYPE_EQ = 4,\n+\tIONIC_QTYPE_MAX = 16,\n+};\n+\n+/**\n+ * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue\n+ * type.\n+ * @qtype: Hardware Queue Type.\n+ * @qid_count: Number of Queue IDs of the logical type.\n+ * @qid_base: Minimum Queue ID of the logical type.\n+ */\n+struct ionic_lif_logical_qtype {\n+\tu8 qtype;\n+\tu8 rsvd[3];\n+\t__le32 qid_count;\n+\t__le32 qid_base;\n+};\n+\n+enum ionic_lif_state {\n+\tIONIC_LIF_DISABLE\t= 0,\n+\tIONIC_LIF_ENABLE\t= 1,\n+\tIONIC_LIF_HANG_RESET\t= 2,\n+};\n+\n+/**\n+ * LIF configuration\n+ * @state: lif state (enum lif_state)\n+ * @name: lif name\n+ * @mtu: mtu\n+ * @mac: station mac address\n+ * @features: features (enum ionic_eth_hw_features)\n+ * @queue_count: queue counts per queue-type\n+ */\n+union ionic_lif_config {\n+\tstruct {\n+\t\tu8 state;\n+\t\tu8 rsvd[3];\n+\t\tchar name[IONIC_IFNAMSIZ];\n+\t\t__le32 mtu;\n+\t\tu8 mac[6];\n+\t\tu8 rsvd2[2];\n+\t\t__le64 features;\n+\t\t__le32 queue_count[IONIC_QTYPE_MAX];\n+\t};\n+\t__le32 words[64];\n+};\n+\n+/**\n+ * struct ionic_lif_identity - lif identity information (type-specific)\n+ *\n+ * @capabilities LIF capabilities\n+ *\n+ * Ethernet:\n+ * @version: Ethernet identify structure version.\n+ * @features: Ethernet features supported on this lif type.\n+ * @max_ucast_filters: Number of perfect unicast addresses supported.\n+ * @max_mcast_filters: Number of perfect multicast addresses supported.\n+ * @min_frame_size: Minimum size of frames to be sent\n+ * @max_frame_size: Maximim size of frames to be sent\n+ * @config: LIF config struct with features, mtu, mac, q counts\n+ *\n+ * RDMA:\n+ * @version: RDMA version of opcodes and queue descriptors.\n+ * @qp_opcodes: Number of rdma queue pair opcodes supported.\n+ * @admin_opcodes: Number of rdma admin opcodes supported.\n+ * @npts_per_lif: Page table size per lif\n+ * @nmrs_per_lif: Number of memory regions per lif\n+ * @nahs_per_lif: Number of address handles per lif\n+ * @max_stride: Max work request stride.\n+ * @cl_stride: Cache line stride.\n+ * @pte_stride: Page table entry stride.\n+ * @rrq_stride: Remote RQ work request stride.\n+ * @rsq_stride: Remote SQ work request stride.\n+ * @dcqcn_profiles: Number of DCQCN profiles\n+ * @aq_qtype: RDMA Admin Qtype.\n+ * @sq_qtype: RDMA Send Qtype.\n+ * @rq_qtype: RDMA Receive Qtype.\n+ * @cq_qtype: RDMA Completion Qtype.\n+ * @eq_qtype: RDMA Event Qtype.\n+ */\n+union ionic_lif_identity {\n+\tstruct {\n+\t\t__le64 capabilities;\n+\n+\t\tstruct {\n+\t\t\tu8 version;\n+\t\t\tu8 rsvd[3];\n+\t\t\t__le32 max_ucast_filters;\n+\t\t\t__le32 max_mcast_filters;\n+\t\t\t__le16 rss_ind_tbl_sz;\n+\t\t\t__le32 min_frame_size;\n+\t\t\t__le32 max_frame_size;\n+\t\t\tu8 rsvd2[106];\n+\t\t\tunion ionic_lif_config config;\n+\t\t} eth;\n+\n+\t\tstruct {\n+\t\t\tu8 version;\n+\t\t\tu8 qp_opcodes;\n+\t\t\tu8 admin_opcodes;\n+\t\t\tu8 rsvd;\n+\t\t\t__le32 npts_per_lif;\n+\t\t\t__le32 nmrs_per_lif;\n+\t\t\t__le32 nahs_per_lif;\n+\t\t\tu8 max_stride;\n+\t\t\tu8 cl_stride;\n+\t\t\tu8 pte_stride;\n+\t\t\tu8 rrq_stride;\n+\t\t\tu8 rsq_stride;\n+\t\t\tu8 dcqcn_profiles;\n+\t\t\tu8 rsvd_dimensions[10];\n+\t\t\tstruct ionic_lif_logical_qtype aq_qtype;\n+\t\t\tstruct ionic_lif_logical_qtype sq_qtype;\n+\t\t\tstruct ionic_lif_logical_qtype rq_qtype;\n+\t\t\tstruct ionic_lif_logical_qtype cq_qtype;\n+\t\t\tstruct ionic_lif_logical_qtype eq_qtype;\n+\t\t} rdma;\n+\t};\n+\t__le32 words[512];\n+};\n+\n+/**\n+ * struct ionic_lif_init_cmd - LIF init command\n+ * @opcode: opcode\n+ * @type: LIF type (enum lif_type)\n+ * @index: LIF index\n+ * @info_pa: destination address for lif info (struct ionic_lif_info)\n+ */\n+struct ionic_lif_init_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 index;\n+\t__le32 rsvd;\n+\t__le64 info_pa;\n+\tu8 rsvd2[48];\n+};\n+\n+/**\n+ * struct ionic_lif_init_comp - LIF init command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_lif_init_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 hw_index;\n+\tu8 rsvd2[12];\n+};\n+\n+/**\n+ * struct ionic_q_init_cmd - Queue init command\n+ * @opcode: opcode\n+ * @type: Logical queue type\n+ * @ver: Queue version (defines opcode/descriptor scope)\n+ * @lif_index: LIF index\n+ * @index: (lif, qtype) relative admin queue index\n+ * @intr_index: Interrupt control register index\n+ * @pid: Process ID\n+ * @flags:\n+ * IRQ: Interrupt requested on completion\n+ * ENA: Enable the queue. If ENA=0 the queue is initialized\n+ * but remains disabled, to be later enabled with the\n+ * Queue Enable command. If ENA=1, then queue is\n+ * initialized and then enabled.\n+ * SG: Enable Scatter-Gather on the queue.\n+ * in number of descs. The actual ring size is\n+ * (1 << ring_size). For example, to\n+ * select a ring size of 64 descriptors write\n+ * ring_size = 6. The minimum ring_size value is 2\n+ * for a ring size of 4 descriptors. The maximum\n+ * ring_size value is 16 for a ring size of 64k\n+ * descriptors. Values of ring_size <2 and >16 are\n+ * reserved.\n+ * EQ: Enable the Event Queue\n+ * @cos: Class of service for this queue.\n+ * @ring_size: Queue ring size, encoded as a log2(size)\n+ * @ring_base: Queue ring base address\n+ * @cq_ring_base: Completion queue ring base address\n+ * @sg_ring_base: Scatter/Gather ring base address\n+ * @eq_index:\t Event queue index\n+ */\n+struct ionic_q_init_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\tu8 type;\n+\tu8 ver;\n+\tu8 rsvd1[2];\n+\t__le32 index;\n+\t__le16 pid;\n+\t__le16 intr_index;\n+\t__le16 flags;\n+#define IONIC_QINIT_F_IRQ\t0x01\t/* Request interrupt on completion */\n+#define IONIC_QINIT_F_ENA\t0x02\t/* Enable the queue */\n+#define IONIC_QINIT_F_SG\t0x04\t/* Enable scatter/gather on the queue */\n+#define IONIC_QINIT_F_EQ\t0x08\t/* Enable event queue */\n+#define IONIC_QINIT_F_DEBUG 0x80\t/* Enable queue debugging */\n+\tu8 cos;\n+\tu8 ring_size;\n+\t__le64 ring_base;\n+\t__le64 cq_ring_base;\n+\t__le64 sg_ring_base;\n+\t__le32 eq_index;\n+\tu8 rsvd2[16];\n+};\n+\n+/**\n+ * struct ionic_q_init_comp - Queue init command completion\n+ * @status: The status of the command (enum status_code)\n+ * @ver: Queue version (defines opcode/descriptor scope)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @hw_index: Hardware Queue ID\n+ * @hw_type: Hardware Queue type\n+ * @color: Color\n+ */\n+struct ionic_q_init_comp {\n+\tu8 status;\n+\tu8 ver;\n+\t__le16 comp_index;\n+\t__le32 hw_index;\n+\tu8 hw_type;\n+\tu8 rsvd2[6];\n+\tu8 color;\n+};\n+\n+/* the device's internal addressing uses up to 52 bits */\n+#define IONIC_ADDR_LEN\t\t52\n+#define IONIC_ADDR_MASK\t\t(BIT_ULL(IONIC_ADDR_LEN) - 1)\n+\n+enum ionic_txq_desc_opcode {\n+\tIONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,\n+\tIONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,\n+\tIONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,\n+\tIONIC_TXQ_DESC_OPCODE_TSO = 3,\n+};\n+\n+/**\n+ * struct ionic_txq_desc - Ethernet Tx queue descriptor format\n+ * @opcode: Tx operation, see TXQ_DESC_OPCODE_*:\n+ *\n+ * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:\n+ *\n+ * Non-offload send. No segmentation,\n+ * fragmentation or checksum calc/insertion is\n+ * performed by device; packet is prepared\n+ * to send by software stack and requires\n+ * no further manipulation from device.\n+ *\n+ * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:\n+ *\n+ * Offload 16-bit L4 checksum\n+ * calculation/insertion. The device will\n+ * calculate the L4 checksum value and\n+ * insert the result in the packet's L4\n+ * header checksum field. The L4 checksum\n+ * is calculated starting at @csum_start bytes\n+ * into the packet to the end of the packet.\n+ * The checksum insertion position is given\n+ * in @csum_offset. This feature is only\n+ * applicable to protocols such as TCP, UDP\n+ * and ICMP where a standard (i.e. the\n+ * 'IP-style' checksum) one's complement\n+ * 16-bit checksum is used, using an IP\n+ * pseudo-header to seed the calculation.\n+ * Software will preload the L4 checksum\n+ * field with the IP pseudo-header checksum.\n+ *\n+ * For tunnel encapsulation, @csum_start and\n+ * @csum_offset refer to the inner L4\n+ * header. Supported tunnels encapsulations\n+ * are: IPIP, GRE, and UDP. If the @encap\n+ * is clear, no further processing by the\n+ * device is required; software will\n+ * calculate the outer header checksums. If\n+ * the @encap is set, the device will\n+ * offload the outer header checksums using\n+ * LCO (local checksum offload) (see\n+ * Documentation/networking/checksum-\n+ * offloads.txt for more info).\n+ *\n+ * IONIC_TXQ_DESC_OPCODE_CSUM_HW:\n+ *\n+ * Offload 16-bit checksum computation to hardware.\n+ * If @csum_l3 is set then the packet's L3 checksum is\n+ * updated. Similarly, if @csum_l4 is set the the L4\n+ * checksum is updated. If @encap is set then encap header\n+ * checksums are also updated.\n+ *\n+ * IONIC_TXQ_DESC_OPCODE_TSO:\n+ *\n+ * Device preforms TCP segmentation offload\n+ * (TSO). @hdr_len is the number of bytes\n+ * to the end of TCP header (the offset to\n+ * the TCP payload). @mss is the desired\n+ * MSS, the TCP payload length for each\n+ * segment. The device will calculate/\n+ * insert IP (IPv4 only) and TCP checksums\n+ * for each segment. In the first data\n+ * buffer containing the header template,\n+ * the driver will set IPv4 checksum to 0\n+ * and preload TCP checksum with the IP\n+ * pseudo header calculated with IP length = 0.\n+ *\n+ * Supported tunnel encapsulations are IPIP,\n+ * layer-3 GRE, and UDP. @hdr_len includes\n+ * both outer and inner headers. The driver\n+ * will set IPv4 checksum to zero and\n+ * preload TCP checksum with IP pseudo\n+ * header on the inner header.\n+ *\n+ * TCP ECN offload is supported. The device\n+ * will set CWR flag in the first segment if\n+ * CWR is set in the template header, and\n+ * clear CWR in remaining segments.\n+ * @flags:\n+ * vlan:\n+ * Insert an L2 VLAN header using @vlan_tci.\n+ * encap:\n+ * Calculate encap header checksum.\n+ * csum_l3:\n+ * Compute L3 header checksum.\n+ * csum_l4:\n+ * Compute L4 header checksum.\n+ * tso_sot:\n+ * TSO start\n+ * tso_eot:\n+ * TSO end\n+ * @num_sg_elems: Number of scatter-gather elements in SG\n+ * descriptor\n+ * @addr: First data buffer's DMA address.\n+ * (Subsequent data buffers are on txq_sg_desc).\n+ * @len: First data buffer's length, in bytes\n+ * @vlan_tci: VLAN tag to insert in the packet (if requested\n+ * by @V-bit). Includes .1p and .1q tags\n+ * @hdr_len: Length of packet headers, including\n+ * encapsulating outer header, if applicable.\n+ * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and\n+ * TXQ_DESC_OPCODE_TSO. Should be set to zero for\n+ * all other modes. For\n+ * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length\n+ * of headers up to inner-most L4 header. For\n+ * TXQ_DESC_OPCODE_TSO, @hdr_len is up to\n+ * inner-most L4 payload, so inclusive of\n+ * inner-most L4 header.\n+ * @mss: Desired MSS value for TSO. Only applicable for\n+ * TXQ_DESC_OPCODE_TSO.\n+ * @csum_start: Offset into inner-most L3 header of checksum\n+ * @csum_offset: Offset into inner-most L4 header of checksum\n+ */\n+\n+#define IONIC_TXQ_DESC_OPCODE_MASK\t\t0xf\n+#define IONIC_TXQ_DESC_OPCODE_SHIFT\t\t4\n+#define IONIC_TXQ_DESC_FLAGS_MASK\t\t0xf\n+#define IONIC_TXQ_DESC_FLAGS_SHIFT\t\t0\n+#define IONIC_TXQ_DESC_NSGE_MASK\t\t0xf\n+#define IONIC_TXQ_DESC_NSGE_SHIFT\t\t8\n+#define IONIC_TXQ_DESC_ADDR_MASK\t\t(BIT_ULL(IONIC_ADDR_LEN) - 1)\n+#define IONIC_TXQ_DESC_ADDR_SHIFT\t\t12\n+\n+/* common flags */\n+#define IONIC_TXQ_DESC_FLAG_VLAN\t\t0x1\n+#define IONIC_TXQ_DESC_FLAG_ENCAP\t\t0x2\n+\n+/* flags for csum_hw opcode */\n+#define IONIC_TXQ_DESC_FLAG_CSUM_L3\t\t0x4\n+#define IONIC_TXQ_DESC_FLAG_CSUM_L4\t\t0x8\n+\n+/* flags for tso opcode */\n+#define IONIC_TXQ_DESC_FLAG_TSO_SOT\t\t0x4\n+#define IONIC_TXQ_DESC_FLAG_TSO_EOT\t\t0x8\n+\n+struct ionic_txq_desc {\n+\t__le64 cmd;\n+\t__le16 len;\n+\tunion {\n+\t\t__le16 vlan_tci;\n+\t\t__le16 hword0;\n+\t};\n+\tunion {\n+\t\t__le16 csum_start;\n+\t\t__le16 hdr_len;\n+\t\t__le16 hword1;\n+\t};\n+\tunion {\n+\t\t__le16 csum_offset;\n+\t\t__le16 mss;\n+\t\t__le16 hword2;\n+\t};\n+};\n+\n+static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,\n+\t\t\t\t u8 nsge, u64 addr)\n+{\n+\tu64 cmd;\n+\n+\tcmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) <<\n+\t\tIONIC_TXQ_DESC_OPCODE_SHIFT;\n+\tcmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) <<\n+\t\tIONIC_TXQ_DESC_FLAGS_SHIFT;\n+\tcmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;\n+\tcmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;\n+\n+\treturn cmd;\n+};\n+\n+static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,\n+\t\t\t\t u8 *nsge, u64 *addr)\n+{\n+\t*opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) &\n+\t\tIONIC_TXQ_DESC_OPCODE_MASK;\n+\t*flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) &\n+\t\tIONIC_TXQ_DESC_FLAGS_MASK;\n+\t*nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;\n+\t*addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;\n+};\n+\n+#define IONIC_TX_MAX_SG_ELEMS\t8\n+#define IONIC_RX_MAX_SG_ELEMS\t8\n+\n+/**\n+ * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list\n+ * @addr: DMA address of SG element data buffer\n+ * @len: Length of SG element data buffer, in bytes\n+ */\n+struct ionic_txq_sg_desc {\n+\tstruct ionic_txq_sg_elem {\n+\t\t__le64 addr;\n+\t\t__le16 len;\n+\t\t__le16 rsvd[3];\n+\t} elems[IONIC_TX_MAX_SG_ELEMS];\n+};\n+\n+/**\n+ * struct ionic_txq_comp - Ethernet transmit queue completion descriptor\n+ * @status: The status of the command (enum status_code)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @color: Color bit.\n+ */\n+struct ionic_txq_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 rsvd2[11];\n+\tu8 color;\n+};\n+\n+enum ionic_rxq_desc_opcode {\n+\tIONIC_RXQ_DESC_OPCODE_SIMPLE = 0,\n+\tIONIC_RXQ_DESC_OPCODE_SG = 1,\n+};\n+\n+/**\n+ * struct ionic_rxq_desc - Ethernet Rx queue descriptor format\n+ * @opcode: Rx operation, see RXQ_DESC_OPCODE_*:\n+ *\n+ * RXQ_DESC_OPCODE_SIMPLE:\n+ *\n+ * Receive full packet into data buffer\n+ * starting at @addr. Results of\n+ * receive, including actual bytes received,\n+ * are recorded in Rx completion descriptor.\n+ *\n+ * @len: Data buffer's length, in bytes.\n+ * @addr: Data buffer's DMA address\n+ */\n+struct ionic_rxq_desc {\n+\tu8 opcode;\n+\tu8 rsvd[5];\n+\t__le16 len;\n+\t__le64 addr;\n+};\n+\n+/**\n+ * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list\n+ * @addr: DMA address of SG element data buffer\n+ * @len: Length of SG element data buffer, in bytes\n+ */\n+struct ionic_rxq_sg_desc {\n+\tstruct ionic_rxq_sg_elem {\n+\t\t__le64 addr;\n+\t\t__le16 len;\n+\t\t__le16 rsvd[3];\n+\t} elems[IONIC_RX_MAX_SG_ELEMS];\n+};\n+\n+/**\n+ * struct ionic_rxq_comp - Ethernet receive queue completion descriptor\n+ * @status: The status of the command (enum status_code)\n+ * @num_sg_elems: Number of SG elements used by this descriptor\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @rss_hash: 32-bit RSS hash\n+ * @csum: 16-bit sum of the packet's L2 payload.\n+ * If the packet's L2 payload is odd length, an extra\n+ * zero-value byte is included in the @csum calculation but\n+ * not included in @len.\n+ * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is\n+ * set. Includes .1p and .1q tags.\n+ * @len: Received packet length, in bytes. Excludes FCS.\n+ * @csum_calc L2 payload checksum is computed or not\n+ * @csum_tcp_ok: The TCP checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * TCP header\n+ * @csum_tcp_bad: The TCP checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * TCP header.\n+ * @csum_udp_ok: The UDP checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * UDP header\n+ * @csum_udp_bad: The UDP checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * UDP header.\n+ * @csum_ip_ok: The IPv4 checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * first IPv4 header. If the receive packet\n+ * contains both a tunnel IPv4 header and a\n+ * transport IPv4 header, the device validates the\n+ * checksum for the both IPv4 headers.\n+ * @csum_ip_bad: The IPv4 checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * first IPv4 header. If the receive packet\n+ * contains both a tunnel IPv4 header and a\n+ * transport IPv4 header, the device validates the\n+ * checksum for both IP headers.\n+ * @VLAN: VLAN header was stripped and placed in @vlan_tci.\n+ * @pkt_type: Packet type\n+ * @color: Color bit.\n+ */\n+struct ionic_rxq_comp {\n+\tu8 status;\n+\tu8 num_sg_elems;\n+\t__le16 comp_index;\n+\t__le32 rss_hash;\n+\t__le16 csum;\n+\t__le16 vlan_tci;\n+\t__le16 len;\n+\tu8 csum_flags;\n+#define IONIC_RXQ_COMP_CSUM_F_TCP_OK\t0x01\n+#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD\t0x02\n+#define IONIC_RXQ_COMP_CSUM_F_UDP_OK\t0x04\n+#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD\t0x08\n+#define IONIC_RXQ_COMP_CSUM_F_IP_OK\t0x10\n+#define IONIC_RXQ_COMP_CSUM_F_IP_BAD\t0x20\n+#define IONIC_RXQ_COMP_CSUM_F_VLAN\t0x40\n+#define IONIC_RXQ_COMP_CSUM_F_CALC\t0x80\n+\tu8 pkt_type_color;\n+#define IONIC_RXQ_COMP_PKT_TYPE_MASK\t0x0f\n+};\n+\n+enum ionic_pkt_type {\n+\tIONIC_PKT_TYPE_NON_IP = 0x000,\n+\tIONIC_PKT_TYPE_IPV4 = 0x001,\n+\tIONIC_PKT_TYPE_IPV4_TCP = 0x003,\n+\tIONIC_PKT_TYPE_IPV4_UDP = 0x005,\n+\tIONIC_PKT_TYPE_IPV6 = 0x008,\n+\tIONIC_PKT_TYPE_IPV6_TCP = 0x018,\n+\tIONIC_PKT_TYPE_IPV6_UDP = 0x028,\n+};\n+\n+enum ionic_eth_hw_features {\n+\tIONIC_ETH_HW_VLAN_TX_TAG\t= BIT(0),\n+\tIONIC_ETH_HW_VLAN_RX_STRIP\t= BIT(1),\n+\tIONIC_ETH_HW_VLAN_RX_FILTER\t= BIT(2),\n+\tIONIC_ETH_HW_RX_HASH\t\t= BIT(3),\n+\tIONIC_ETH_HW_RX_CSUM\t\t= BIT(4),\n+\tIONIC_ETH_HW_TX_SG\t\t= BIT(5),\n+\tIONIC_ETH_HW_RX_SG\t\t= BIT(6),\n+\tIONIC_ETH_HW_TX_CSUM\t\t= BIT(7),\n+\tIONIC_ETH_HW_TSO\t\t= BIT(8),\n+\tIONIC_ETH_HW_TSO_IPV6\t\t= BIT(9),\n+\tIONIC_ETH_HW_TSO_ECN\t\t= BIT(10),\n+\tIONIC_ETH_HW_TSO_GRE\t\t= BIT(11),\n+\tIONIC_ETH_HW_TSO_GRE_CSUM\t= BIT(12),\n+\tIONIC_ETH_HW_TSO_IPXIP4\t= BIT(13),\n+\tIONIC_ETH_HW_TSO_IPXIP6\t= BIT(14),\n+\tIONIC_ETH_HW_TSO_UDP\t\t= BIT(15),\n+\tIONIC_ETH_HW_TSO_UDP_CSUM\t= BIT(16),\n+};\n+\n+/**\n+ * struct ionic_q_control_cmd - Queue control command\n+ * @opcode: opcode\n+ * @type: Queue type\n+ * @lif_index: LIF index\n+ * @index: Queue index\n+ * @oper: Operation (enum q_control_oper)\n+ */\n+struct ionic_q_control_cmd {\n+\tu8 opcode;\n+\tu8 type;\n+\t__le16 lif_index;\n+\t__le32 index;\n+\tu8 oper;\n+\tu8 rsvd[55];\n+};\n+\n+typedef struct ionic_admin_comp ionic_q_control_comp;\n+\n+enum q_control_oper {\n+\tIONIC_Q_DISABLE\t\t= 0,\n+\tIONIC_Q_ENABLE\t\t= 1,\n+\tIONIC_Q_HANG_RESET\t= 2,\n+};\n+\n+/**\n+ * Physical connection type\n+ */\n+enum ionic_phy_type {\n+\tIONIC_PHY_TYPE_NONE\t= 0,\n+\tIONIC_PHY_TYPE_COPPER\t= 1,\n+\tIONIC_PHY_TYPE_FIBER\t= 2,\n+};\n+\n+/**\n+ * Transceiver status\n+ */\n+enum ionic_xcvr_state {\n+\tIONIC_XCVR_STATE_REMOVED\t = 0,\n+\tIONIC_XCVR_STATE_INSERTED\t = 1,\n+\tIONIC_XCVR_STATE_PENDING\t = 2,\n+\tIONIC_XCVR_STATE_SPROM_READ\t = 3,\n+\tIONIC_XCVR_STATE_SPROM_READ_ERR = 4,\n+};\n+\n+/**\n+ * Supported link modes\n+ */\n+enum ionic_xcvr_pid {\n+\tIONIC_XCVR_PID_UNKNOWN = 0,\n+\n+\t/* CU */\n+\tIONIC_XCVR_PID_QSFP_100G_CR4 = 1,\n+\tIONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,\n+\tIONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,\n+\tIONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,\n+\tIONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,\n+\n+\t/* Fiber */\n+\tIONIC_XCVR_PID_QSFP_100G_AOC = 50,\n+\tIONIC_XCVR_PID_QSFP_100G_ACC = 51,\n+\tIONIC_XCVR_PID_QSFP_100G_SR4 = 52,\n+\tIONIC_XCVR_PID_QSFP_100G_LR4 = 53,\n+\tIONIC_XCVR_PID_QSFP_100G_ER4 = 54,\n+\tIONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,\n+\tIONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,\n+\tIONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,\n+\tIONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,\n+\tIONIC_XCVR_PID_SFP_25GBASE_SR = 59,\n+\tIONIC_XCVR_PID_SFP_25GBASE_LR = 60,\n+\tIONIC_XCVR_PID_SFP_25GBASE_ER = 61,\n+\tIONIC_XCVR_PID_SFP_25GBASE_AOC = 62,\n+\tIONIC_XCVR_PID_SFP_10GBASE_SR = 63,\n+\tIONIC_XCVR_PID_SFP_10GBASE_LR = 64,\n+\tIONIC_XCVR_PID_SFP_10GBASE_LRM = 65,\n+\tIONIC_XCVR_PID_SFP_10GBASE_ER = 66,\n+\tIONIC_XCVR_PID_SFP_10GBASE_AOC = 67,\n+\tIONIC_XCVR_PID_SFP_10GBASE_CU = 68,\n+\tIONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,\n+\tIONIC_XCVR_PID_QSFP_100G_PSM4 = 70,\n+};\n+\n+/**\n+ * Port types\n+ */\n+enum ionic_port_type {\n+\tIONIC_PORT_TYPE_NONE = 0, /* port type not configured */\n+\tIONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */\n+\tIONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */\n+};\n+\n+/**\n+ * Port config state\n+ */\n+enum ionic_port_admin_state {\n+\tIONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */\n+\tIONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */\n+\tIONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */\n+};\n+\n+/**\n+ * Port operational status\n+ */\n+enum ionic_port_oper_status {\n+\tIONIC_PORT_OPER_STATUS_NONE = 0,\t/* port is disabled */\n+\tIONIC_PORT_OPER_STATUS_UP = 1,\t/* port is linked up */\n+\tIONIC_PORT_OPER_STATUS_DOWN = 2,\t/* port link status is down */\n+};\n+\n+/**\n+ * Ethernet Forward error correction (fec) modes\n+ */\n+enum ionic_port_fec_type {\n+\tIONIC_PORT_FEC_TYPE_NONE = 0,\t\t/* Disabled */\n+\tIONIC_PORT_FEC_TYPE_FC = 1,\t\t/* FireCode */\n+\tIONIC_PORT_FEC_TYPE_RS = 2,\t\t/* ReedSolomon */\n+};\n+\n+/**\n+ * Ethernet pause (flow control) modes\n+ */\n+enum ionic_port_pause_type {\n+\tIONIC_PORT_PAUSE_TYPE_NONE = 0,\t/* Disable Pause */\n+\tIONIC_PORT_PAUSE_TYPE_LINK = 1,\t/* Link level pause */\n+\tIONIC_PORT_PAUSE_TYPE_PFC = 2,\t/* Priority-Flow control */\n+};\n+\n+/**\n+ * Loopback modes\n+ */\n+enum ionic_port_loopback_mode {\n+\tIONIC_PORT_LOOPBACK_MODE_NONE = 0,\t/* Disable loopback */\n+\tIONIC_PORT_LOOPBACK_MODE_MAC = 1,\t/* MAC loopback */\n+\tIONIC_PORT_LOOPBACK_MODE_PHY = 2,\t/* PHY/Serdes loopback */\n+};\n+\n+/**\n+ * Transceiver Status information\n+ * @state: Transceiver status (enum ionic_xcvr_state)\n+ * @phy: Physical connection type (enum ionic_phy_type)\n+ * @pid: Transceiver link mode (enum pid)\n+ * @sprom: Transceiver sprom contents\n+ */\n+struct ionic_xcvr_status {\n+\tu8 state;\n+\tu8 phy;\n+\t__le16 pid;\n+\tu8 sprom[256];\n+};\n+\n+/**\n+ * Port configuration\n+ * @speed: port speed (in Mbps)\n+ * @mtu: mtu\n+ * @state: port admin state (enum port_admin_state)\n+ * @an_enable: autoneg enable\n+ * @fec_type: fec type (enum ionic_port_fec_type)\n+ * @pause_type: pause type (enum ionic_port_pause_type)\n+ * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)\n+ */\n+union ionic_port_config {\n+\tstruct {\n+#define IONIC_SPEED_100G\t100000\t/* 100G in Mbps */\n+#define IONIC_SPEED_50G\t\t50000\t/* 50G in Mbps */\n+#define IONIC_SPEED_40G\t\t40000\t/* 40G in Mbps */\n+#define IONIC_SPEED_25G\t\t25000\t/* 25G in Mbps */\n+#define IONIC_SPEED_10G\t\t10000\t/* 10G in Mbps */\n+#define IONIC_SPEED_1G\t\t1000\t/* 1G in Mbps */\n+\t\t__le32 speed;\n+\t\t__le32 mtu;\n+\t\tu8 state;\n+\t\tu8 an_enable;\n+\t\tu8 fec_type;\n+#define IONIC_PAUSE_TYPE_MASK\t\t0x0f\n+#define IONIC_PAUSE_FLAGS_MASK\t\t0xf0\n+#define IONIC_PAUSE_F_TX\t\t0x10\n+#define IONIC_PAUSE_F_RX\t\t0x20\n+\t\tu8 pause_type;\n+\t\tu8 loopback_mode;\n+\t};\n+\t__le32 words[64];\n+};\n+\n+/**\n+ * Port Status information\n+ * @status: link status (enum ionic_port_oper_status)\n+ * @id: port id\n+ * @speed: link speed (in Mbps)\n+ * @xcvr: tranceiver status\n+ */\n+struct ionic_port_status {\n+\t__le32 id;\n+\t__le32 speed;\n+\tu8 status;\n+\tu8 rsvd[51];\n+\tstruct ionic_xcvr_status xcvr;\n+};\n+\n+/**\n+ * struct ionic_port_identify_cmd - Port identify command\n+ * @opcode: opcode\n+ * @index: port index\n+ * @ver: Highest version of identify supported by driver\n+ */\n+struct ionic_port_identify_cmd {\n+\tu8 opcode;\n+\tu8 index;\n+\tu8 ver;\n+\tu8 rsvd[61];\n+};\n+\n+/**\n+ * struct ionic_port_identify_comp - Port identify command completion\n+ * @status: The status of the command (enum status_code)\n+ * @ver: Version of identify returned by device\n+ */\n+struct ionic_port_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd[14];\n+};\n+\n+/**\n+ * struct ionic_port_init_cmd - Port initialization command\n+ * @opcode: opcode\n+ * @index: port index\n+ * @info_pa: destination address for port info (struct ionic_port_info)\n+ */\n+struct ionic_port_init_cmd {\n+\tu8 opcode;\n+\tu8 index;\n+\tu8 rsvd[6];\n+\t__le64 info_pa;\n+\tu8 rsvd2[48];\n+};\n+\n+/**\n+ * struct ionic_port_init_comp - Port initialization command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_port_init_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+/**\n+ * struct ionic_port_reset_cmd - Port reset command\n+ * @opcode: opcode\n+ * @index: port index\n+ */\n+struct ionic_port_reset_cmd {\n+\tu8 opcode;\n+\tu8 index;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct ionic_port_reset_comp - Port reset command completion\n+ * @status: The status of the command (enum status_code)\n+ */\n+struct ionic_port_reset_comp {\n+\tu8 status;\n+\tu8 rsvd[15];\n+};\n+\n+/**\n+ * enum stats_ctl_cmd - List of commands for stats control\n+ */\n+enum ionic_stats_ctl_cmd {\n+\tIONIC_STATS_CTL_RESET\t\t= 0,\n+};\n+\n+\n+/**\n+ * enum ionic_port_attr - List of device attributes\n+ */\n+enum ionic_port_attr {\n+\tIONIC_PORT_ATTR_STATE\t\t= 0,\n+\tIONIC_PORT_ATTR_SPEED\t\t= 1,\n+\tIONIC_PORT_ATTR_MTU\t\t= 2,\n+\tIONIC_PORT_ATTR_AUTONEG\t\t= 3,\n+\tIONIC_PORT_ATTR_FEC\t\t= 4,\n+\tIONIC_PORT_ATTR_PAUSE\t\t= 5,\n+\tIONIC_PORT_ATTR_LOOPBACK\t= 6,\n+\tIONIC_PORT_ATTR_STATS_CTRL\t= 7,\n+};\n+\n+/**\n+ * struct ionic_port_setattr_cmd - Set port attributes on the NIC\n+ * @opcode: Opcode\n+ * @index: port index\n+ * @attr: Attribute type (enum ionic_port_attr)\n+ */\n+struct ionic_port_setattr_cmd {\n+\tu8 opcode;\n+\tu8 index;\n+\tu8 attr;\n+\tu8 rsvd;\n+\tunion {\n+\t\tu8 state;\n+\t\t__le32 speed;\n+\t\t__le32 mtu;\n+\t\tu8 an_enable;\n+\t\tu8 fec_type;\n+\t\tu8 pause_type;\n+\t\tu8 loopback_mode;\n+\t\tu8\tstats_ctl;\n+\t\tu8 rsvd2[60];\n+\t};\n+};\n+\n+/**\n+ * struct ionic_port_setattr_comp - Port set attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @color: Color bit\n+ */\n+struct ionic_port_setattr_comp {\n+\tu8 status;\n+\tu8 rsvd[14];\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_port_getattr_cmd - Get port attributes from the NIC\n+ * @opcode: Opcode\n+ * @index: port index\n+ * @attr: Attribute type (enum ionic_port_attr)\n+ */\n+struct ionic_port_getattr_cmd {\n+\tu8 opcode;\n+\tu8 index;\n+\tu8 attr;\n+\tu8 rsvd[61];\n+};\n+\n+/**\n+ * struct ionic_port_getattr_comp - Port get attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @color: Color bit\n+ */\n+struct ionic_port_getattr_comp {\n+\tu8 status;\n+\tu8 rsvd[3];\n+\tunion {\n+\t\tu8 state;\n+\t\t__le32 speed;\n+\t\t__le32 mtu;\n+\t\tu8 an_enable;\n+\t\tu8 fec_type;\n+\t\tu8 pause_type;\n+\t\tu8 loopback_mode;\n+\t\tu8 rsvd2[11];\n+\t};\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_lif_status - Lif status register\n+ * @eid: most recent NotifyQ event id\n+ * @port_num: port the lif is connected to\n+ * @link_status: port status (enum ionic_port_oper_status)\n+ * @link_speed: speed of link in Mbps\n+ * @link_down_count: number of times link status changes\n+ */\n+struct ionic_lif_status {\n+\t__le64 eid;\n+\tu8 port_num;\n+\tu8 rsvd;\n+\t__le16 link_status;\n+\t__le32 link_speed;\t\t/* units of 1Mbps: eg 10000 = 10Gbps */\n+\t__le16 link_down_count;\n+\tu8 rsvd2[46];\n+};\n+\n+/**\n+ * struct ionic_lif_reset_cmd - LIF reset command\n+ * @opcode: opcode\n+ * @index: LIF index\n+ */\n+struct ionic_lif_reset_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 index;\n+\t__le32 rsvd2[15];\n+};\n+\n+typedef struct ionic_admin_comp ionic_lif_reset_comp;\n+\n+enum ionic_dev_state {\n+\tIONIC_DEV_DISABLE\t= 0,\n+\tIONIC_DEV_ENABLE\t= 1,\n+\tIONIC_DEV_HANG_RESET\t= 2,\n+};\n+\n+/**\n+ * enum ionic_dev_attr - List of device attributes\n+ */\n+enum ionic_dev_attr {\n+\tIONIC_DEV_ATTR_STATE = 0,\n+\tIONIC_DEV_ATTR_NAME = 1,\n+\tIONIC_DEV_ATTR_FEATURES = 2,\n+};\n+\n+/**\n+ * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC\n+ * @opcode: Opcode\n+ * @attr: Attribute type (enum ionic_dev_attr)\n+ * @state: Device state (enum ionic_dev_state)\n+ * @name: The bus info, e.g. PCI slot-device-function, 0 terminated\n+ * @features: Device features\n+ */\n+struct ionic_dev_setattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 rsvd;\n+\tunion {\n+\t\tu8 state;\n+\t\tchar name[IONIC_IFNAMSIZ];\n+\t\t__le64 features;\n+\t\tu8 rsvd2[60];\n+\t};\n+};\n+\n+/**\n+ * struct ionic_dev_setattr_comp - Device set attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @features: Device features\n+ * @color: Color bit\n+ */\n+struct ionic_dev_setattr_comp {\n+\tu8 status;\n+\tu8 rsvd[3];\n+\tunion {\n+\t\t__le64 features;\n+\t\tu8 rsvd2[11];\n+\t};\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC\n+ * @opcode: opcode\n+ * @attr: Attribute type (enum ionic_dev_attr)\n+ */\n+struct ionic_dev_getattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct ionic_dev_setattr_comp - Device set attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @features: Device features\n+ * @color: Color bit\n+ */\n+struct ionic_dev_getattr_comp {\n+\tu8 status;\n+\tu8 rsvd[3];\n+\tunion {\n+\t\t__le64 features;\n+\t\tu8 rsvd2[11];\n+\t};\n+\tu8 color;\n+};\n+\n+/**\n+ * RSS parameters\n+ */\n+#define IONIC_RSS_HASH_KEY_SIZE\t\t40\n+\n+enum ionic_rss_hash_types {\n+\tIONIC_RSS_TYPE_IPV4\t= BIT(0),\n+\tIONIC_RSS_TYPE_IPV4_TCP\t= BIT(1),\n+\tIONIC_RSS_TYPE_IPV4_UDP\t= BIT(2),\n+\tIONIC_RSS_TYPE_IPV6\t= BIT(3),\n+\tIONIC_RSS_TYPE_IPV6_TCP\t= BIT(4),\n+\tIONIC_RSS_TYPE_IPV6_UDP\t= BIT(5),\n+};\n+\n+/**\n+ * enum ionic_lif_attr - List of LIF attributes\n+ */\n+enum ionic_lif_attr {\n+\tIONIC_LIF_ATTR_STATE = 0,\n+\tIONIC_LIF_ATTR_NAME = 1,\n+\tIONIC_LIF_ATTR_MTU = 2,\n+\tIONIC_LIF_ATTR_MAC = 3,\n+\tIONIC_LIF_ATTR_FEATURES = 4,\n+\tIONIC_LIF_ATTR_RSS = 5,\n+\tIONIC_LIF_ATTR_STATS_CTRL = 6,\n+};\n+\n+/**\n+ * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC\n+ * @opcode: Opcode\n+ * @type: Attribute type (enum ionic_lif_attr)\n+ * @index: LIF index\n+ * @state: lif state (enum lif_state)\n+ * @name: The netdev name string, 0 terminated\n+ * @mtu: Mtu\n+ * @mac: Station mac\n+ * @features: Features (enum ionic_eth_hw_features)\n+ * @rss: RSS properties\n+ * @types: The hash types to enable (see rss_hash_types).\n+ * @key: The hash secret key.\n+ * @addr: Address for the indirection table shared memory.\n+ * @stats_ctl: stats control commands (enum stats_ctl_cmd)\n+ */\n+struct ionic_lif_setattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 index;\n+\tunion {\n+\t\tu8 state;\n+\t\tchar name[IONIC_IFNAMSIZ];\n+\t\t__le32 mtu;\n+\t\tu8 mac[6];\n+\t\t__le64 features;\n+\t\tstruct {\n+\t\t\t__le16 types;\n+\t\t\tu8 key[IONIC_RSS_HASH_KEY_SIZE];\n+\t\t\tu8 rsvd[6];\n+\t\t\t__le64 addr;\n+\t\t} rss;\n+\t\tu8\tstats_ctl;\n+\t\tu8 rsvd[60];\n+\t};\n+};\n+\n+/**\n+ * struct ionic_lif_setattr_comp - LIF set attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @features: features (enum ionic_eth_hw_features)\n+ * @color: Color bit\n+ */\n+struct ionic_lif_setattr_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tunion {\n+\t\t__le64 features;\n+\t\tu8 rsvd2[11];\n+\t};\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC\n+ * @opcode: Opcode\n+ * @attr: Attribute type (enum ionic_lif_attr)\n+ * @index: LIF index\n+ */\n+struct ionic_lif_getattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 index;\n+\tu8 rsvd[60];\n+};\n+\n+/**\n+ * struct ionic_lif_getattr_comp - LIF get attr command completion\n+ * @status: The status of the command (enum status_code)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @state: lif state (enum lif_state)\n+ * @name: The netdev name string, 0 terminated\n+ * @mtu: Mtu\n+ * @mac: Station mac\n+ * @features: Features (enum ionic_eth_hw_features)\n+ * @color: Color bit\n+ */\n+struct ionic_lif_getattr_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tunion {\n+\t\tu8 state;\n+\t\t__le32 mtu;\n+\t\tu8 mac[6];\n+\t\t__le64 features;\n+\t\tu8 rsvd2[11];\n+\t};\n+\tu8 color;\n+};\n+\n+enum ionic_rx_mode {\n+\tIONIC_RX_MODE_F_UNICAST = BIT(0),\n+\tIONIC_RX_MODE_F_MULTICAST = BIT(1),\n+\tIONIC_RX_MODE_F_BROADCAST = BIT(2),\n+\tIONIC_RX_MODE_F_PROMISC = BIT(3),\n+\tIONIC_RX_MODE_F_ALLMULTI = BIT(4),\n+};\n+\n+/**\n+ * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command\n+ * @opcode: opcode\n+ * @lif_index: LIF index\n+ * @rx_mode: Rx mode flags:\n+ * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets.\n+ * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets.\n+ * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets.\n+ * IONIC_RX_MODE_F_PROMISC: Accept any packets.\n+ * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets.\n+ */\n+struct ionic_rx_mode_set_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\t__le16 rx_mode;\n+\t__le16 rsvd2[29];\n+};\n+\n+typedef struct ionic_admin_comp ionic_rx_mode_set_comp;\n+\n+enum ionic_rx_filter_match_type {\n+\tIONIC_RX_FILTER_MATCH_VLAN = 0,\n+\tIONIC_RX_FILTER_MATCH_MAC,\n+\tIONIC_RX_FILTER_MATCH_MAC_VLAN,\n+};\n+\n+/**\n+ * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command\n+ * @opcode: opcode\n+ * @qtype: Queue type\n+ * @lif_index: LIF index\n+ * @qid: Queue ID\n+ * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx)\n+ * @vlan: VLAN ID\n+ * @addr: MAC address (network-byte order)\n+ */\n+struct ionic_rx_filter_add_cmd {\n+\tu8 opcode;\n+\tu8 qtype;\n+\t__le16 lif_index;\n+\t__le32 qid;\n+\t__le16 match;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 vlan;\n+\t\t} vlan;\n+\t\tstruct {\n+\t\t\tu8 addr[6];\n+\t\t} mac;\n+\t\tstruct {\n+\t\t\t__le16 vlan;\n+\t\t\tu8 addr[6];\n+\t\t} mac_vlan;\n+\t\tu8 rsvd[54];\n+\t};\n+};\n+\n+/**\n+ * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion\n+ * @status: The status of the command (enum status_code)\n+ * @comp_index: The index in the descriptor ring for which this\n+ * is the completion.\n+ * @filter_id: Filter ID\n+ * @color: Color bit.\n+ */\n+struct ionic_rx_filter_add_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\t__le32 filter_id;\n+\tu8 rsvd2[7];\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command\n+ * @opcode: opcode\n+ * @lif_index: LIF index\n+ * @filter_id: Filter ID\n+ */\n+struct ionic_rx_filter_del_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\t__le32 filter_id;\n+\tu8 rsvd2[56];\n+};\n+\n+typedef struct ionic_admin_comp ionic_rx_filter_del_comp;\n+\n+/**\n+ * struct ionic_qos_identify_cmd - QoS identify command\n+ * @opcode: opcode\n+ * @ver: Highest version of identify supported by driver\n+ *\n+ */\n+struct ionic_qos_identify_cmd {\n+\tu8 opcode;\n+\tu8 ver;\n+\tu8 rsvd[62];\n+};\n+\n+/**\n+ * struct ionic_qos_identify_comp - QoS identify command completion\n+ * @status: The status of the command (enum status_code)\n+ * @ver: Version of identify returned by device\n+ */\n+struct ionic_qos_identify_comp {\n+\tu8 status;\n+\tu8 ver;\n+\tu8 rsvd[14];\n+};\n+\n+#define IONIC_QOS_CLASS_MAX\t\t7\n+#define IONIC_QOS_CLASS_NAME_SZ\t\t32\n+#define IONIC_QOS_DSCP_MAX_VALUES\t64\n+\n+/**\n+ * enum ionic_qos_class\n+ */\n+enum ionic_qos_class {\n+\tIONIC_QOS_CLASS_DEFAULT\t\t= 0,\n+\tIONIC_QOS_CLASS_USER_DEFINED_1\t= 1,\n+\tIONIC_QOS_CLASS_USER_DEFINED_2\t= 2,\n+\tIONIC_QOS_CLASS_USER_DEFINED_3\t= 3,\n+\tIONIC_QOS_CLASS_USER_DEFINED_4\t= 4,\n+\tIONIC_QOS_CLASS_USER_DEFINED_5\t= 5,\n+\tIONIC_QOS_CLASS_USER_DEFINED_6\t= 6,\n+};\n+\n+/**\n+ * enum ionic_qos_class_type - Traffic classification criteria\n+ */\n+enum ionic_qos_class_type {\n+\tIONIC_QOS_CLASS_TYPE_NONE\t= 0,\n+\tIONIC_QOS_CLASS_TYPE_PCP\t= 1,\t/* Dot1Q pcp */\n+\tIONIC_QOS_CLASS_TYPE_DSCP\t= 2,\t/* IP dscp */\n+};\n+\n+/**\n+ * enum ionic_qos_sched_type - Qos class scheduling type\n+ */\n+enum ionic_qos_sched_type {\n+\t/* Strict priority */\n+\tIONIC_QOS_SCHED_TYPE_STRICT\t= 0,\n+\t/* Deficit weighted round-robin */\n+\tIONIC_QOS_SCHED_TYPE_DWRR\t= 1,\n+};\n+\n+/**\n+ * union ionic_qos_config - Qos configuration structure\n+ * @flags:\t\tConfiguration flags\n+ *\tIONIC_QOS_CONFIG_F_ENABLE\t\tenable\n+ *\tIONIC_QOS_CONFIG_F_DROP\t\t\tdrop/nodrop\n+ *\tIONIC_QOS_CONFIG_F_RW_DOT1Q_PCP\t\tenable dot1q pcp rewrite\n+ *\tIONIC_QOS_CONFIG_F_RW_IP_DSCP\t\tenable ip dscp rewrite\n+ * @sched_type:\t\tQos class scheduling type (enum ionic_qos_sched_type)\n+ * @class_type:\t\tQos class type (enum ionic_qos_class_type)\n+ * @pause_type:\t\tQos pause type (enum qos_pause_type)\n+ * @name:\t\tQos class name\n+ * @mtu:\t\tMTU of the class\n+ * @pfc_dot1q_pcp:\tPcp value for pause frames (valid iff F_NODROP)\n+ * @dwrr_weight:\tQos class scheduling weight\n+ * @strict_rlmt:\tRate limit for strict priority scheduling\n+ * @rw_dot1q_pcp:\tRewrite dot1q pcp to this value\n+ *\t\t\t(valid iff F_RW_DOT1Q_PCP)\n+ * @rw_ip_dscp:\t\tRewrite ip dscp to this value\n+ *\t\t\t(valid iff F_RW_IP_DSCP)\n+ * @dot1q_pcp:\t\tDot1q pcp value\n+ * @ndscp:\t\tNumber of valid dscp values in the ip_dscp field\n+ * @ip_dscp:\t\tIP dscp values\n+ */\n+union ionic_qos_config {\n+\tstruct {\n+#define IONIC_QOS_CONFIG_F_ENABLE\t\tBIT(0)\n+#define IONIC_QOS_CONFIG_F_DROP\t\t\tBIT(1)\n+#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP\t\tBIT(2)\n+#define IONIC_QOS_CONFIG_F_RW_IP_DSCP\t\tBIT(3)\n+\t\tu8 flags;\n+\t\tu8 sched_type;\n+\t\tu8 class_type;\n+\t\tu8 pause_type;\n+\t\tchar name[IONIC_QOS_CLASS_NAME_SZ];\n+\t\t__le32 mtu;\n+\t\t/* flow control */\n+\t\tu8 pfc_cos;\n+\t\t/* scheduler */\n+\t\tunion {\n+\t\t\tu8 dwrr_weight;\n+\t\t\t__le64 strict_rlmt;\n+\t\t};\n+\t\t/* marking */\n+\t\tunion {\n+\t\t\tu8 rw_dot1q_pcp;\n+\t\t\tu8 rw_ip_dscp;\n+\t\t};\n+\t\t/* classification */\n+\t\tunion {\n+\t\t\tu8 dot1q_pcp;\n+\t\t\tstruct {\n+\t\t\t\tu8 ndscp;\n+\t\t\t\tu8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__le32 words[64];\n+};\n+\n+/**\n+ * union ionic_qos_identity - QoS identity structure\n+ * @version:\tVersion of the identify structure\n+ * @type:\tQoS system type\n+ * @nclasses:\tNumber of usable QoS classes\n+ * @config:\tCurrent configuration of classes\n+ */\n+union ionic_qos_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 type;\n+\t\tu8 rsvd[62];\n+\t\tunion ionic_qos_config config[IONIC_QOS_CLASS_MAX];\n+\t};\n+\t__le32 words[512];\n+};\n+\n+/**\n+ * struct qos_init_cmd - QoS config init command\n+ * @opcode:\tOpcode\n+ * @group:\tQos class id\n+ * @info_pa:\tdestination address for qos info\n+ */\n+struct ionic_qos_init_cmd {\n+\tu8 opcode;\n+\tu8 group;\n+\tu8 rsvd[6];\n+\t__le64 info_pa;\n+\tu8 rsvd1[48];\n+};\n+\n+typedef struct ionic_admin_comp ionic_qos_init_comp;\n+\n+/**\n+ * struct ionic_qos_reset_cmd - Qos config reset command\n+ * @opcode:\tOpcode\n+ */\n+struct ionic_qos_reset_cmd {\n+\tu8 opcode;\n+\tu8 group;\n+\tu8 rsvd[62];\n+};\n+\n+typedef struct ionic_admin_comp ionic_qos_reset_comp;\n+\n+/**\n+ * struct ionic_fw_download_cmd - Firmware download command\n+ * @opcode:\topcode\n+ * @addr:\tdma address of the firmware buffer\n+ * @offset:\toffset of the firmware buffer within the full image\n+ * @length:\tnumber of valid bytes in the firmware buffer\n+ */\n+struct ionic_fw_download_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[3];\n+\t__le32 offset;\n+\t__le64 addr;\n+\t__le32 length;\n+};\n+\n+typedef struct ionic_admin_comp ionic_fw_download_comp;\n+\n+enum ionic_fw_control_oper {\n+\tIONIC_FW_RESET\t\t= 0,\t/* Reset firmware */\n+\tIONIC_FW_INSTALL\t= 1,\t/* Install firmware */\n+\tIONIC_FW_ACTIVATE\t= 2,\t/* Activate firmware */\n+};\n+\n+/**\n+ * struct ionic_fw_control_cmd - Firmware control command\n+ * @opcode: opcode\n+ * @oper: firmware control operation (enum ionic_fw_control_oper)\n+ * @slot: slot to activate\n+ */\n+struct ionic_fw_control_cmd {\n+\tu8 opcode;\n+\tu8 rsvd[3];\n+\tu8 oper;\n+\tu8 slot;\n+\tu8 rsvd1[58];\n+};\n+\n+/**\n+ * struct ionic_fw_control_comp - Firmware control copletion\n+ * @opcode: opcode\n+ * @slot: slot where the firmware was installed\n+ */\n+struct ionic_fw_control_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 slot;\n+\tu8 rsvd1[10];\n+\tu8 color;\n+};\n+\n+/******************************************************************\n+ ******************* RDMA Commands ********************************\n+ ******************************************************************/\n+\n+/**\n+ * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd\n+ * @opcode: opcode\n+ * @lif_index: lif index\n+ *\n+ * There is no rdma specific dev command completion struct. Completion uses\n+ * the common struct ionic_admin_comp. Only the status is indicated.\n+ * Nonzero status means the LIF does not support rdma.\n+ **/\n+struct ionic_rdma_reset_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\tu8 rsvd2[60];\n+};\n+\n+/**\n+ * struct ionic_rdma_queue_cmd - Create RDMA Queue command\n+ * @opcode: opcode, 52, 53\n+ * @lif_index lif index\n+ * @qid_ver: (qid | (rdma version << 24))\n+ * @cid: intr, eq_id, or cq_id\n+ * @dbid: doorbell page id\n+ * @depth_log2: log base two of queue depth\n+ * @stride_log2: log base two of queue stride\n+ * @dma_addr: address of the queue memory\n+ * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.\n+ *\n+ * The same command struct is used to create an rdma event queue, completion\n+ * queue, or rdma admin queue. The cid is an interrupt number for an event\n+ * queue, an event queue id for a completion queue, or a completion queue id\n+ * for an rdma admin queue.\n+ *\n+ * The queue created via a dev command must be contiguous in dma space.\n+ *\n+ * The dev commands are intended only to be used during driver initialization,\n+ * to create queues supporting the rdma admin queue. Other queues, and other\n+ * types of rdma resources like memory regions, will be created and registered\n+ * via the rdma admin queue, and will support a more complete interface\n+ * providing scatter gather lists for larger, scattered queue buffers and\n+ * memory registration.\n+ *\n+ * There is no rdma specific dev command completion struct. Completion uses\n+ * the common struct ionic_admin_comp. Only the status is indicated.\n+ **/\n+struct ionic_rdma_queue_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_index;\n+\t__le32 qid_ver;\n+\t__le32 cid;\n+\t__le16 dbid;\n+\tu8 depth_log2;\n+\tu8 stride_log2;\n+\t__le64 dma_addr;\n+\tu8 rsvd2[36];\n+\t__le32 xxx_table_index;\n+};\n+\n+/******************************************************************\n+ ******************* Notify Events ********************************\n+ ******************************************************************/\n+\n+/**\n+ * struct ionic_notifyq_event\n+ * @eid: event number\n+ * @ecode: event code\n+ * @data: unspecified data about the event\n+ *\n+ * This is the generic event report struct from which the other\n+ * actual events will be formed.\n+ */\n+struct ionic_notifyq_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 data[54];\n+};\n+\n+/**\n+ * struct ionic_link_change_event\n+ * @eid:\t\tevent number\n+ * @ecode:\t\tevent code = EVENT_OPCODE_LINK_CHANGE\n+ * @link_status:\tlink up or down, with error bits (enum port_status)\n+ * @link_speed:\t\tspeed of the network link\n+ *\n+ * Sent when the network link state changes between UP and DOWN\n+ */\n+struct ionic_link_change_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\t__le16 link_status;\n+\t__le32 link_speed;\t/* units of 1Mbps: e.g. 10000 = 10Gbps */\n+\tu8 rsvd[48];\n+};\n+\n+/**\n+ * struct ionic_reset_event\n+ * @eid:\t\tevent number\n+ * @ecode:\t\tevent code = EVENT_OPCODE_RESET\n+ * @reset_code:\t\treset type\n+ * @state:\t\t0=pending, 1=complete, 2=error\n+ *\n+ * Sent when the NIC or some subsystem is going to be or\n+ * has been reset.\n+ */\n+struct ionic_reset_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 reset_code;\n+\tu8 state;\n+\tu8 rsvd[52];\n+};\n+\n+/**\n+ * struct ionic_heartbeat_event\n+ * @eid:\tevent number\n+ * @ecode:\tevent code = EVENT_OPCODE_HEARTBEAT\n+ *\n+ * Sent periodically by the NIC to indicate continued health\n+ */\n+struct ionic_heartbeat_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 rsvd[54];\n+};\n+\n+/**\n+ * struct ionic_log_event\n+ * @eid:\tevent number\n+ * @ecode:\tevent code = EVENT_OPCODE_LOG\n+ * @data:\tlog data\n+ *\n+ * Sent to notify the driver of an internal error.\n+ */\n+struct ionic_log_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 data[54];\n+};\n+\n+/**\n+ * struct ionic_port_stats\n+ */\n+struct ionic_port_stats {\n+\t__le64 frames_rx_ok;\n+\t__le64 frames_rx_all;\n+\t__le64 frames_rx_bad_fcs;\n+\t__le64 frames_rx_bad_all;\n+\t__le64 octets_rx_ok;\n+\t__le64 octets_rx_all;\n+\t__le64 frames_rx_unicast;\n+\t__le64 frames_rx_multicast;\n+\t__le64 frames_rx_broadcast;\n+\t__le64 frames_rx_pause;\n+\t__le64 frames_rx_bad_length;\n+\t__le64 frames_rx_undersized;\n+\t__le64 frames_rx_oversized;\n+\t__le64 frames_rx_fragments;\n+\t__le64 frames_rx_jabber;\n+\t__le64 frames_rx_pripause;\n+\t__le64 frames_rx_stomped_crc;\n+\t__le64 frames_rx_too_long;\n+\t__le64 frames_rx_vlan_good;\n+\t__le64 frames_rx_dropped;\n+\t__le64 frames_rx_less_than_64b;\n+\t__le64 frames_rx_64b;\n+\t__le64 frames_rx_65b_127b;\n+\t__le64 frames_rx_128b_255b;\n+\t__le64 frames_rx_256b_511b;\n+\t__le64 frames_rx_512b_1023b;\n+\t__le64 frames_rx_1024b_1518b;\n+\t__le64 frames_rx_1519b_2047b;\n+\t__le64 frames_rx_2048b_4095b;\n+\t__le64 frames_rx_4096b_8191b;\n+\t__le64 frames_rx_8192b_9215b;\n+\t__le64 frames_rx_other;\n+\t__le64 frames_tx_ok;\n+\t__le64 frames_tx_all;\n+\t__le64 frames_tx_bad;\n+\t__le64 octets_tx_ok;\n+\t__le64 octets_tx_total;\n+\t__le64 frames_tx_unicast;\n+\t__le64 frames_tx_multicast;\n+\t__le64 frames_tx_broadcast;\n+\t__le64 frames_tx_pause;\n+\t__le64 frames_tx_pripause;\n+\t__le64 frames_tx_vlan;\n+\t__le64 frames_tx_less_than_64b;\n+\t__le64 frames_tx_64b;\n+\t__le64 frames_tx_65b_127b;\n+\t__le64 frames_tx_128b_255b;\n+\t__le64 frames_tx_256b_511b;\n+\t__le64 frames_tx_512b_1023b;\n+\t__le64 frames_tx_1024b_1518b;\n+\t__le64 frames_tx_1519b_2047b;\n+\t__le64 frames_tx_2048b_4095b;\n+\t__le64 frames_tx_4096b_8191b;\n+\t__le64 frames_tx_8192b_9215b;\n+\t__le64 frames_tx_other;\n+\t__le64 frames_tx_pri_0;\n+\t__le64 frames_tx_pri_1;\n+\t__le64 frames_tx_pri_2;\n+\t__le64 frames_tx_pri_3;\n+\t__le64 frames_tx_pri_4;\n+\t__le64 frames_tx_pri_5;\n+\t__le64 frames_tx_pri_6;\n+\t__le64 frames_tx_pri_7;\n+\t__le64 frames_rx_pri_0;\n+\t__le64 frames_rx_pri_1;\n+\t__le64 frames_rx_pri_2;\n+\t__le64 frames_rx_pri_3;\n+\t__le64 frames_rx_pri_4;\n+\t__le64 frames_rx_pri_5;\n+\t__le64 frames_rx_pri_6;\n+\t__le64 frames_rx_pri_7;\n+\t__le64 tx_pripause_0_1us_count;\n+\t__le64 tx_pripause_1_1us_count;\n+\t__le64 tx_pripause_2_1us_count;\n+\t__le64 tx_pripause_3_1us_count;\n+\t__le64 tx_pripause_4_1us_count;\n+\t__le64 tx_pripause_5_1us_count;\n+\t__le64 tx_pripause_6_1us_count;\n+\t__le64 tx_pripause_7_1us_count;\n+\t__le64 rx_pripause_0_1us_count;\n+\t__le64 rx_pripause_1_1us_count;\n+\t__le64 rx_pripause_2_1us_count;\n+\t__le64 rx_pripause_3_1us_count;\n+\t__le64 rx_pripause_4_1us_count;\n+\t__le64 rx_pripause_5_1us_count;\n+\t__le64 rx_pripause_6_1us_count;\n+\t__le64 rx_pripause_7_1us_count;\n+\t__le64 rx_pause_1us_count;\n+\t__le64 frames_tx_truncated;\n+};\n+\n+struct ionic_mgmt_port_stats {\n+\t__le64 frames_rx_ok;\n+\t__le64 frames_rx_all;\n+\t__le64 frames_rx_bad_fcs;\n+\t__le64 frames_rx_bad_all;\n+\t__le64 octets_rx_ok;\n+\t__le64 octets_rx_all;\n+\t__le64 frames_rx_unicast;\n+\t__le64 frames_rx_multicast;\n+\t__le64 frames_rx_broadcast;\n+\t__le64 frames_rx_pause;\n+\t__le64 frames_rx_bad_length0;\n+\t__le64 frames_rx_undersized1;\n+\t__le64 frames_rx_oversized2;\n+\t__le64 frames_rx_fragments3;\n+\t__le64 frames_rx_jabber4;\n+\t__le64 frames_rx_64b5;\n+\t__le64 frames_rx_65b_127b6;\n+\t__le64 frames_rx_128b_255b7;\n+\t__le64 frames_rx_256b_511b8;\n+\t__le64 frames_rx_512b_1023b9;\n+\t__le64 frames_rx_1024b_1518b0;\n+\t__le64 frames_rx_gt_1518b1;\n+\t__le64 frames_rx_fifo_full2;\n+\t__le64 frames_tx_ok3;\n+\t__le64 frames_tx_all4;\n+\t__le64 frames_tx_bad5;\n+\t__le64 octets_tx_ok6;\n+\t__le64 octets_tx_total7;\n+\t__le64 frames_tx_unicast8;\n+\t__le64 frames_tx_multicast9;\n+\t__le64 frames_tx_broadcast0;\n+\t__le64 frames_tx_pause1;\n+};\n+\n+/**\n+ * struct ionic_port_identity - port identity structure\n+ * @version: identity structure version\n+ * @type: type of port (enum port_type)\n+ * @num_lanes: number of lanes for the port\n+ * @autoneg: autoneg supported\n+ * @min_frame_size: minimum frame size supported\n+ * @max_frame_size: maximum frame size supported\n+ * @fec_type: supported fec types\n+ * @pause_type: supported pause types\n+ * @loopback_mode: supported loopback mode\n+ * @speeds: supported speeds\n+ * @config: current port configuration\n+ */\n+union ionic_port_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 type;\n+\t\tu8 num_lanes;\n+\t\tu8 autoneg;\n+\t\t__le32 min_frame_size;\n+\t\t__le32 max_frame_size;\n+\t\tu8 fec_type[4];\n+\t\tu8 pause_type[2];\n+\t\tu8 loopback_mode[2];\n+\t\t__le32 speeds[16];\n+\t\tu8 rsvd2[44];\n+\t\tunion ionic_port_config config;\n+\t};\n+\t__le32 words[512];\n+};\n+\n+/**\n+ * struct ionic_port_info - port info structure\n+ * @port_status: port status\n+ * @port_stats: port stats\n+ */\n+struct ionic_port_info {\n+\tunion ionic_port_config config;\n+\tstruct ionic_port_status status;\n+\tstruct ionic_port_stats stats;\n+};\n+\n+/**\n+ * struct ionic_lif_stats\n+ */\n+struct ionic_lif_stats {\n+\t/* RX */\n+\t__le64 rx_ucast_bytes;\n+\t__le64 rx_ucast_packets;\n+\t__le64 rx_mcast_bytes;\n+\t__le64 rx_mcast_packets;\n+\t__le64 rx_bcast_bytes;\n+\t__le64 rx_bcast_packets;\n+\t__le64 rsvd0;\n+\t__le64 rsvd1;\n+\t/* RX drops */\n+\t__le64 rx_ucast_drop_bytes;\n+\t__le64 rx_ucast_drop_packets;\n+\t__le64 rx_mcast_drop_bytes;\n+\t__le64 rx_mcast_drop_packets;\n+\t__le64 rx_bcast_drop_bytes;\n+\t__le64 rx_bcast_drop_packets;\n+\t__le64 rx_dma_error;\n+\t__le64 rsvd2;\n+\t/* TX */\n+\t__le64 tx_ucast_bytes;\n+\t__le64 tx_ucast_packets;\n+\t__le64 tx_mcast_bytes;\n+\t__le64 tx_mcast_packets;\n+\t__le64 tx_bcast_bytes;\n+\t__le64 tx_bcast_packets;\n+\t__le64 rsvd3;\n+\t__le64 rsvd4;\n+\t/* TX drops */\n+\t__le64 tx_ucast_drop_bytes;\n+\t__le64 tx_ucast_drop_packets;\n+\t__le64 tx_mcast_drop_bytes;\n+\t__le64 tx_mcast_drop_packets;\n+\t__le64 tx_bcast_drop_bytes;\n+\t__le64 tx_bcast_drop_packets;\n+\t__le64 tx_dma_error;\n+\t__le64 rsvd5;\n+\t/* Rx Queue/Ring drops */\n+\t__le64 rx_queue_disabled;\n+\t__le64 rx_queue_empty;\n+\t__le64 rx_queue_error;\n+\t__le64 rx_desc_fetch_error;\n+\t__le64 rx_desc_data_error;\n+\t__le64 rsvd6;\n+\t__le64 rsvd7;\n+\t__le64 rsvd8;\n+\t/* Tx Queue/Ring drops */\n+\t__le64 tx_queue_disabled;\n+\t__le64 tx_queue_error;\n+\t__le64 tx_desc_fetch_error;\n+\t__le64 tx_desc_data_error;\n+\t__le64 rsvd9;\n+\t__le64 rsvd10;\n+\t__le64 rsvd11;\n+\t__le64 rsvd12;\n+\n+\t/* RDMA/ROCE TX */\n+\t__le64 tx_rdma_ucast_bytes;\n+\t__le64 tx_rdma_ucast_packets;\n+\t__le64 tx_rdma_mcast_bytes;\n+\t__le64 tx_rdma_mcast_packets;\n+\t__le64 tx_rdma_cnp_packets;\n+\t__le64 rsvd13;\n+\t__le64 rsvd14;\n+\t__le64 rsvd15;\n+\n+\t/* RDMA/ROCE RX */\n+\t__le64 rx_rdma_ucast_bytes;\n+\t__le64 rx_rdma_ucast_packets;\n+\t__le64 rx_rdma_mcast_bytes;\n+\t__le64 rx_rdma_mcast_packets;\n+\t__le64 rx_rdma_cnp_packets;\n+\t__le64 rx_rdma_ecn_packets;\n+\t__le64 rsvd16;\n+\t__le64 rsvd17;\n+\n+\t__le64 rsvd18;\n+\t__le64 rsvd19;\n+\t__le64 rsvd20;\n+\t__le64 rsvd21;\n+\t__le64 rsvd22;\n+\t__le64 rsvd23;\n+\t__le64 rsvd24;\n+\t__le64 rsvd25;\n+\n+\t__le64 rsvd26;\n+\t__le64 rsvd27;\n+\t__le64 rsvd28;\n+\t__le64 rsvd29;\n+\t__le64 rsvd30;\n+\t__le64 rsvd31;\n+\t__le64 rsvd32;\n+\t__le64 rsvd33;\n+\n+\t__le64 rsvd34;\n+\t__le64 rsvd35;\n+\t__le64 rsvd36;\n+\t__le64 rsvd37;\n+\t__le64 rsvd38;\n+\t__le64 rsvd39;\n+\t__le64 rsvd40;\n+\t__le64 rsvd41;\n+\n+\t__le64 rsvd42;\n+\t__le64 rsvd43;\n+\t__le64 rsvd44;\n+\t__le64 rsvd45;\n+\t__le64 rsvd46;\n+\t__le64 rsvd47;\n+\t__le64 rsvd48;\n+\t__le64 rsvd49;\n+\n+\t/* RDMA/ROCE REQ Error/Debugs (768 - 895) */\n+\t__le64 rdma_req_rx_pkt_seq_err;\n+\t__le64 rdma_req_rx_rnr_retry_err;\n+\t__le64 rdma_req_rx_remote_access_err;\n+\t__le64 rdma_req_rx_remote_inv_req_err;\n+\t__le64 rdma_req_rx_remote_oper_err;\n+\t__le64 rdma_req_rx_implied_nak_seq_err;\n+\t__le64 rdma_req_rx_cqe_err;\n+\t__le64 rdma_req_rx_cqe_flush_err;\n+\n+\t__le64 rdma_req_rx_dup_responses;\n+\t__le64 rdma_req_rx_invalid_packets;\n+\t__le64 rdma_req_tx_local_access_err;\n+\t__le64 rdma_req_tx_local_oper_err;\n+\t__le64 rdma_req_tx_memory_mgmt_err;\n+\t__le64 rsvd52;\n+\t__le64 rsvd53;\n+\t__le64 rsvd54;\n+\n+\t/* RDMA/ROCE RESP Error/Debugs (896 - 1023) */\n+\t__le64 rdma_resp_rx_dup_requests;\n+\t__le64 rdma_resp_rx_out_of_buffer;\n+\t__le64 rdma_resp_rx_out_of_seq_pkts;\n+\t__le64 rdma_resp_rx_cqe_err;\n+\t__le64 rdma_resp_rx_cqe_flush_err;\n+\t__le64 rdma_resp_rx_local_len_err;\n+\t__le64 rdma_resp_rx_inv_request_err;\n+\t__le64 rdma_resp_rx_local_qp_oper_err;\n+\n+\t__le64 rdma_resp_rx_out_of_atomic_resource;\n+\t__le64 rdma_resp_tx_pkt_seq_err;\n+\t__le64 rdma_resp_tx_remote_inv_req_err;\n+\t__le64 rdma_resp_tx_remote_access_err;\n+\t__le64 rdma_resp_tx_remote_oper_err;\n+\t__le64 rdma_resp_tx_rnr_retry_err;\n+\t__le64 rsvd57;\n+\t__le64 rsvd58;\n+};\n+\n+/**\n+ * struct ionic_lif_info - lif info structure\n+ */\n+struct ionic_lif_info {\n+\tunion ionic_lif_config config;\n+\tstruct ionic_lif_status status;\n+\tstruct ionic_lif_stats stats;\n+};\n+\n+union ionic_dev_cmd {\n+\tu32 words[16];\n+\tstruct ionic_admin_cmd cmd;\n+\tstruct ionic_nop_cmd nop;\n+\n+\tstruct ionic_dev_identify_cmd identify;\n+\tstruct ionic_dev_init_cmd init;\n+\tstruct ionic_dev_reset_cmd reset;\n+\tstruct ionic_dev_getattr_cmd getattr;\n+\tstruct ionic_dev_setattr_cmd setattr;\n+\n+\tstruct ionic_port_identify_cmd port_identify;\n+\tstruct ionic_port_init_cmd port_init;\n+\tstruct ionic_port_reset_cmd port_reset;\n+\tstruct ionic_port_getattr_cmd port_getattr;\n+\tstruct ionic_port_setattr_cmd port_setattr;\n+\n+\tstruct ionic_lif_identify_cmd lif_identify;\n+\tstruct ionic_lif_init_cmd lif_init;\n+\tstruct ionic_lif_reset_cmd lif_reset;\n+\n+\tstruct ionic_qos_identify_cmd qos_identify;\n+\tstruct ionic_qos_init_cmd qos_init;\n+\tstruct ionic_qos_reset_cmd qos_reset;\n+\n+\tstruct ionic_q_init_cmd q_init;\n+};\n+\n+union ionic_dev_cmd_comp {\n+\tu32 words[4];\n+\tu8 status;\n+\tstruct ionic_admin_comp comp;\n+\tstruct ionic_nop_comp nop;\n+\n+\tstruct ionic_dev_identify_comp identify;\n+\tstruct ionic_dev_init_comp init;\n+\tstruct ionic_dev_reset_comp reset;\n+\tstruct ionic_dev_getattr_comp getattr;\n+\tstruct ionic_dev_setattr_comp setattr;\n+\n+\tstruct ionic_port_identify_comp port_identify;\n+\tstruct ionic_port_init_comp port_init;\n+\tstruct ionic_port_reset_comp port_reset;\n+\tstruct ionic_port_getattr_comp port_getattr;\n+\tstruct ionic_port_setattr_comp port_setattr;\n+\n+\tstruct ionic_lif_identify_comp lif_identify;\n+\tstruct ionic_lif_init_comp lif_init;\n+\tionic_lif_reset_comp lif_reset;\n+\n+\tstruct ionic_qos_identify_comp qos_identify;\n+\tionic_qos_init_comp qos_init;\n+\tionic_qos_reset_comp qos_reset;\n+\n+\tstruct ionic_q_init_comp q_init;\n+};\n+\n+/**\n+ * union dev_info - Device info register format (read-only)\n+ * @signature: Signature value of 0x44455649 ('DEVI').\n+ * @version: Current version of info.\n+ * @asic_type: Asic type.\n+ * @asic_rev: Asic revision.\n+ * @fw_status: Firmware status.\n+ * @fw_heartbeat: Firmware heartbeat counter.\n+ * @serial_num: Serial number.\n+ * @fw_version: Firmware version.\n+ */\n+union ionic_dev_info_regs {\n+#define IONIC_DEVINFO_FWVERS_BUFLEN 32\n+#define IONIC_DEVINFO_SERIAL_BUFLEN 32\n+\tstruct {\n+\t\tu32 signature;\n+\t\tu8 version;\n+\t\tu8 asic_type;\n+\t\tu8 asic_rev;\n+\t\tu8 fw_status;\n+\t\tu32 fw_heartbeat;\n+\t\tchar fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];\n+\t\tchar serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];\n+\t};\n+\tu32 words[512];\n+};\n+\n+/**\n+ * union ionic_dev_cmd_regs - Device command register format (read-write)\n+ * @doorbell: Device Cmd Doorbell, write-only.\n+ * Write a 1 to signal device to process cmd,\n+ * poll done for completion.\n+ * @done: Done indicator, bit 0 == 1 when command is complete.\n+ * @cmd: Opcode-specific command bytes\n+ * @comp: Opcode-specific response bytes\n+ * @data: Opcode-specific side-data\n+ */\n+union ionic_dev_cmd_regs {\n+\tstruct {\n+\t\tu32 doorbell;\n+\t\tu32 done;\n+\t\tunion ionic_dev_cmd cmd;\n+\t\tunion ionic_dev_cmd_comp comp;\n+\t\tu8 rsvd[48];\n+\t\tu32 data[478];\n+\t};\n+\tu32 words[512];\n+};\n+\n+/**\n+ * union ionic_dev_regs - Device register format in for bar 0 page 0\n+ * @info: Device info registers\n+ * @devcmd: Device command registers\n+ */\n+union ionic_dev_regs {\n+\tstruct {\n+\t\tunion ionic_dev_info_regs info;\n+\t\tunion ionic_dev_cmd_regs devcmd;\n+\t};\n+\t__le32 words[1024];\n+};\n+\n+union ionic_adminq_cmd {\n+\tstruct ionic_admin_cmd cmd;\n+\tstruct ionic_nop_cmd nop;\n+\tstruct ionic_q_init_cmd q_init;\n+\tstruct ionic_q_control_cmd q_control;\n+\tstruct ionic_lif_setattr_cmd lif_setattr;\n+\tstruct ionic_lif_getattr_cmd lif_getattr;\n+\tstruct ionic_rx_mode_set_cmd rx_mode_set;\n+\tstruct ionic_rx_filter_add_cmd rx_filter_add;\n+\tstruct ionic_rx_filter_del_cmd rx_filter_del;\n+\tstruct ionic_rdma_reset_cmd rdma_reset;\n+\tstruct ionic_rdma_queue_cmd rdma_queue;\n+\tstruct ionic_fw_download_cmd fw_download;\n+\tstruct ionic_fw_control_cmd fw_control;\n+};\n+\n+union ionic_adminq_comp {\n+\tstruct ionic_admin_comp comp;\n+\tstruct ionic_nop_comp nop;\n+\tstruct ionic_q_init_comp q_init;\n+\tstruct ionic_lif_setattr_comp lif_setattr;\n+\tstruct ionic_lif_getattr_comp lif_getattr;\n+\tstruct ionic_rx_filter_add_comp rx_filter_add;\n+\tstruct ionic_fw_control_comp fw_control;\n+};\n+\n+#define IONIC_BARS_MAX\t\t\t6\n+#define IONIC_PCI_BAR_DBELL\t\t1\n+\n+/* BAR0 */\n+#define IONIC_BAR0_SIZE\t\t\t\t0x8000\n+\n+#define IONIC_BAR0_DEV_INFO_REGS_OFFSET\t\t0x0000\n+#define IONIC_BAR0_DEV_CMD_REGS_OFFSET\t\t0x0800\n+#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET\t0x0c00\n+#define IONIC_BAR0_INTR_STATUS_OFFSET\t\t0x1000\n+#define IONIC_BAR0_INTR_CTRL_OFFSET\t\t0x2000\n+#define IONIC_DEV_CMD_DONE\t\t\t0x00000001\n+\n+#define IONIC_ASIC_TYPE_CAPRI\t\t\t0\n+\n+/**\n+ * struct ionic_doorbell - Doorbell register layout\n+ * @p_index: Producer index\n+ * @ring: Selects the specific ring of the queue to update.\n+ * Type-specific meaning:\n+ * ring=0: Default producer/consumer queue.\n+ * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs\n+ * send events to EQs when armed. EQs send\n+ * interrupts when armed.\n+ * @qid: The queue id selects the queue destination for the\n+ * producer index and flags.\n+ */\n+struct ionic_doorbell {\n+\t__le16 p_index;\n+\tu8 ring;\n+\tu8 qid_lo;\n+\t__le16 qid_hi;\n+\tu16 rsvd2;\n+};\n+\n+struct ionic_intr_status {\n+\tu32 status[2];\n+};\n+\n+struct ionic_notifyq_cmd {\n+\t__le32 data;\t/* Not used but needed for qcq structure */\n+};\n+\n+union ionic_notifyq_comp {\n+\tstruct ionic_notifyq_event event;\n+\tstruct ionic_link_change_event link_change;\n+\tstruct ionic_reset_event reset;\n+\tstruct ionic_heartbeat_event heartbeat;\n+\tstruct ionic_log_event log;\n+};\n+\n+/* Deprecate */\n+struct ionic_identity {\n+\tunion ionic_drv_identity drv;\n+\tunion ionic_dev_identity dev;\n+\tunion ionic_lif_identity lif;\n+\tunion ionic_port_identity port;\n+\tunion ionic_qos_identity qos;\n+};\n+\n+#pragma pack(pop)\n+\n+#endif /* _IONIC_IF_H_ */\n", "prefixes": [ "v3", "02/17" ] }