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GET /api/patches/63659/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 63659,
    "url": "http://patches.dpdk.org/api/patches/63659/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-4-git-send-email-mchalla@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1575819342-20008-4-git-send-email-mchalla@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1575819342-20008-4-git-send-email-mchalla@marvell.com",
    "date": "2019-12-08T15:35:39",
    "name": "[v1,3/6] raw/octeontx2_ep: add device uninitialization",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b7b01150e886c2eec138eb87481818098f9e82be",
    "submitter": {
        "id": 1532,
        "url": "http://patches.dpdk.org/api/people/1532/?format=api",
        "name": "Mahipal Challa",
        "email": "mchalla@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-4-git-send-email-mchalla@marvell.com/mbox/",
    "series": [
        {
            "id": 7751,
            "url": "http://patches.dpdk.org/api/series/7751/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7751",
            "date": "2019-12-08T15:35:36",
            "name": "OCTEON TX2 End Point Driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/7751/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/63659/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/63659/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EF80AA04F1;\n\tSun,  8 Dec 2019 16:36:47 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 941E01BF98;\n\tSun,  8 Dec 2019 16:36:17 +0100 (CET)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 62F041BF94\n for <dev@dpdk.org>; Sun,  8 Dec 2019 16:36:15 +0100 (CET)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n xB8FUaVt028929 for <dev@dpdk.org>; Sun, 8 Dec 2019 07:36:14 -0800",
            "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 2wrcfpts1s-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 08 Dec 2019 07:36:14 -0800",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 8 Dec\n 2019 07:36:12 -0800",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n Transport; Sun, 8 Dec 2019 07:36:12 -0800",
            "from hyd1244.marvell.com (hyd1244.marvell.com [10.29.20.28])\n by maili.marvell.com (Postfix) with ESMTP id A71F03F7041;\n Sun,  8 Dec 2019 07:36:10 -0800 (PST)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=80hCgYuYOQRyHZhwEo9Fhd+JlrtLkusV04tYWqAmW/8=;\n b=EIdeqdvvzbbTOgQYfScYiWHohuoYezees5DMttg/qmclVbUqLuKV7nDLIK3tbTDxCNH9\n KvgwK6vZpNgNWu8/9YbJ/p7hsyjqXwq9shrrerqlkd5f/60uowfEYxYsxTDoALvYtwrQ\n mfxYtJDY2iMTY4GMaefvsxt0yvx4SldbQFvGrMqk+sSZeURx6fJHXHIXTmkGdov7Ntt9\n 1yPTPsKhDkqQaP7Oh8otUWvNpQvotSvnz60kMm79EG7t8cC9DJITpAFpqqo3eutQQjWG\n dgNSEL6Scca/hMdg+zAapcW42zYniOQcAXVHxy3h/imXozqrDZ9gqY1KY0ofxm35UTZR dg==",
        "From": "Mahipal Challa <mchalla@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<jerinj@marvell.com>, <pathreya@marvell.com>, <snilla@marvell.com>,\n <venkatn@marvell.com>",
        "Date": "Sun, 8 Dec 2019 21:05:39 +0530",
        "Message-ID": "<1575819342-20008-4-git-send-email-mchalla@marvell.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>",
        "References": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2019-12-08_04:2019-12-05,2019-12-08 signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 3/6] raw/octeontx2_ep: add device\n\tuninitialization",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add rawdev close/uninitialize operation for SDP\nVF devices.\n\nSigned-off-by: Mahipal Challa <mchalla@marvell.com>\n---\n drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 111 ++++++++++++++++++++++++++++++\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.c |  78 +++++++++++++++++++++\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.h |   8 +++\n drivers/raw/octeontx2_ep/otx2_ep_vf.c     |  44 ++++++++++++\n 4 files changed, 241 insertions(+)",
    "diff": "diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\nindex 8857004..584b818 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\n@@ -21,6 +21,59 @@\n #include \"otx2_common.h\"\n #include \"otx2_ep_enqdeq.h\"\n \n+static void\n+sdp_dmazone_free(const struct rte_memzone *mz)\n+{\n+\tconst struct rte_memzone *mz_tmp;\n+\tint ret = 0;\n+\n+\tif (mz == NULL) {\n+\t\totx2_err(\"Memzone %s : NULL\", mz->name);\n+\t\treturn;\n+\t}\n+\n+\tmz_tmp = rte_memzone_lookup(mz->name);\n+\tif (mz_tmp == NULL) {\n+\t\totx2_err(\"Memzone %s Not Found\", mz->name);\n+\t\treturn;\n+\t}\n+\n+\tret = rte_memzone_free(mz);\n+\tif (ret)\n+\t\totx2_err(\"Memzone free failed : ret = %d\", ret);\n+\n+}\n+\n+/* Free IQ resources */\n+int\n+sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)\n+{\n+\tstruct sdp_instr_queue *iq;\n+\n+\tiq = sdpvf->instr_queue[iq_no];\n+\tif (iq == NULL) {\n+\t\totx2_err(\"Invalid IQ[%d]\\n\", iq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trte_free(iq->req_list);\n+\tiq->req_list = NULL;\n+\n+\tif (iq->iq_mz) {\n+\t\tsdp_dmazone_free(iq->iq_mz);\n+\t\tiq->iq_mz = NULL;\n+\t}\n+\n+\trte_free(sdpvf->instr_queue[iq_no]);\n+\tsdpvf->instr_queue[iq_no] = NULL;\n+\n+\tsdpvf->num_iqs--;\n+\n+\totx2_info(\"IQ[%d] is deleted\", iq_no);\n+\n+\treturn 0;\n+}\n+\n /* IQ initialization */\n static int\n sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)\n@@ -126,6 +179,7 @@\n \treturn 0;\n \n delete_IQ:\n+\tsdp_delete_iqs(sdpvf, iq_no);\n \treturn -ENOMEM;\n }\n \n@@ -139,6 +193,61 @@\n \trte_atomic64_set(&droq->pkts_pending, 0);\n }\n \n+static void\n+sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,\n+\t\t\t\tstruct sdp_droq *droq)\n+{\n+\tuint32_t idx;\n+\n+\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n+\t\tif (droq->recv_buf_list[idx].buffer) {\n+\t\t\trte_mempool_put(sdpvf->enqdeq_mpool,\n+\t\t\t\tdroq->recv_buf_list[idx].buffer);\n+\n+\t\t\tdroq->recv_buf_list[idx].buffer = NULL;\n+\t\t}\n+\t}\n+\n+\tsdp_droq_reset_indices(droq);\n+}\n+\n+/* Free OQs resources */\n+int\n+sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)\n+{\n+\tstruct sdp_droq *droq;\n+\n+\tdroq = sdpvf->droq[oq_no];\n+\tif (droq == NULL) {\n+\t\totx2_err(\"Invalid droq[%d]\", oq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tsdp_droq_destroy_ring_buffers(sdpvf, droq);\n+\trte_free(droq->recv_buf_list);\n+\tdroq->recv_buf_list = NULL;\n+\n+\tif (droq->info_mz) {\n+\t\tsdp_dmazone_free(droq->info_mz);\n+\t\tdroq->info_mz = NULL;\n+\t}\n+\n+\tif (droq->desc_ring_mz) {\n+\t\tsdp_dmazone_free(droq->desc_ring_mz);\n+\t\tdroq->desc_ring_mz = NULL;\n+\t}\n+\n+\tmemset(droq, 0, SDP_DROQ_SIZE);\n+\n+\trte_free(sdpvf->droq[oq_no]);\n+\tsdpvf->droq[oq_no] = NULL;\n+\n+\tsdpvf->num_oqs--;\n+\n+\totx2_info(\"OQ[%d] is deleted\", oq_no);\n+\treturn 0;\n+}\n+\n static int\n sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,\n \t\tstruct sdp_droq *droq)\n@@ -290,5 +399,7 @@\n \treturn 0;\n \n delete_OQ:\n+\tsdp_delete_oqs(sdpvf, oq_no);\n \treturn -ENOMEM;\n }\n+\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\nindex 5db9b50..2c43d3f 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n@@ -63,6 +63,45 @@\n }\n \n static int\n+sdp_vfdev_exit(struct rte_rawdev *rawdev)\n+{\n+\tstruct sdp_device *sdpvf;\n+\tuint32_t rawdev_queues, q;\n+\n+\totx2_info(\"%s:\", __func__);\n+\n+\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n+\n+\tsdpvf->fn_list.disable_io_queues(sdpvf);\n+\n+\trawdev_queues = sdpvf->num_oqs;\n+\tfor (q = 0; q < rawdev_queues; q++) {\n+\t\tif (sdp_delete_oqs(sdpvf, q)) {\n+\t\t\totx2_err(\"Failed to delete OQ:%d\", q);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\totx2_info(\"Num OQs:%d freed\", sdpvf->num_oqs);\n+\n+\t/* Free the oqbuf_pool */\n+\trte_mempool_free(sdpvf->enqdeq_mpool);\n+\tsdpvf->enqdeq_mpool = NULL;\n+\n+\totx2_info(\"Enqdeq_mpool free done\");\n+\n+\trawdev_queues = sdpvf->num_iqs;\n+\tfor (q = 0; q < rawdev_queues; q++) {\n+\t\tif (sdp_delete_iqs(sdpvf, q)) {\n+\t\t\totx2_err(\"Failed to delete IQ:%d\", q);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\totx2_sdp_dbg(\"Num IQs:%d freed\", sdpvf->num_iqs);\n+\n+\treturn 0;\n+}\n+\n+static int\n sdp_chip_specific_setup(struct sdp_device *sdpvf)\n {\n \tstruct rte_pci_device *pdev = sdpvf->pci_dev;\n@@ -142,13 +181,49 @@\n \n \treturn 0;\n \n+/* Error handling  */\n oq_fail:\n+\t/* Free the allocated OQs */\n+\tfor (q = 0; q < sdpvf->num_oqs; q++)\n+\t\tsdp_delete_oqs(sdpvf, q);\n+\n iq_fail:\n+\t/* Free the allocated IQs */\n+\tfor (q = 0; q < sdpvf->num_iqs; q++)\n+\t\tsdp_delete_iqs(sdpvf, q);\n+\n setup_fail:\n \treturn -ENOMEM;\n }\n \n static int\n+sdp_rawdev_start(struct rte_rawdev *dev)\n+{\n+\tdev->started = 1;\n+\n+\treturn 0;\n+}\n+\n+static void\n+sdp_rawdev_stop(struct rte_rawdev *dev)\n+{\n+\tdev->started = 0;\n+}\n+\n+static int\n+sdp_rawdev_close(struct rte_rawdev *dev)\n+{\n+\tint ret;\n+\tret = sdp_vfdev_exit(dev);\n+\tif (ret) {\n+\t\totx2_err(\" SDP_EP rawdev exit error\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n {\n \tstruct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;\n@@ -173,6 +248,9 @@\n /* SDP VF endpoint rawdev ops */\n static const struct rte_rawdev_ops sdp_rawdev_ops = {\n \t.dev_configure  = sdp_rawdev_configure,\n+\t.dev_start      = sdp_rawdev_start,\n+\t.dev_stop       = sdp_rawdev_stop,\n+\t.dev_close      = sdp_rawdev_close,\n };\n \n static int\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\nindex bb36b6a..a01f48d 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n@@ -378,10 +378,16 @@ struct sdp_config {\n struct sdp_fn_list {\n \tvoid (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n \tvoid (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n+\n \tint (*setup_device_regs)(struct sdp_device *sdpvf);\n \tvoid (*enable_io_queues)(struct sdp_device *sdpvf);\n+\tvoid (*disable_io_queues)(struct sdp_device *sdpvf);\n+\n \tvoid (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);\n+\tvoid (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);\n+\n \tvoid (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);\n+\tvoid (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);\n };\n \n /* SRIOV information */\n@@ -447,7 +453,9 @@ struct sdp_device {\n \n const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);\n int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);\n+int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);\n \n int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);\n+int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);\n \n #endif /* _OTX2_EP_RAWDEV_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c\nindex b6120eb..8e79fe8 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_vf.c\n@@ -371,6 +371,44 @@\n \t\tsdp_vf_enable_oq(sdpvf, q_no);\n }\n \n+static void\n+sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\t/* Reset the doorbell register for this Input Queue. */\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+}\n+\n+static void\n+sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\treg_val &= ~0x1ull;\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+}\n+\n+static void\n+sdp_vf_disable_io_queues(struct sdp_device *sdpvf)\n+{\n+\tuint32_t q_no = 0;\n+\n+\t/* Disable Input Queues. */\n+\tfor (q_no = 0; q_no < sdpvf->num_iqs; q_no++)\n+\t\tsdp_vf_disable_iq(sdpvf, q_no);\n+\n+\t/* Disable Output Queues. */\n+\tfor (q_no = 0; q_no < sdpvf->num_oqs; q_no++)\n+\t\tsdp_vf_disable_oq(sdpvf, q_no);\n+}\n+\n int\n sdp_vf_setup_device(struct sdp_device *sdpvf)\n {\n@@ -396,10 +434,16 @@\n \n \tsdpvf->fn_list.setup_iq_regs       = sdp_vf_setup_iq_regs;\n \tsdpvf->fn_list.setup_oq_regs       = sdp_vf_setup_oq_regs;\n+\n \tsdpvf->fn_list.setup_device_regs   = sdp_vf_setup_device_regs;\n \tsdpvf->fn_list.enable_io_queues    = sdp_vf_enable_io_queues;\n+\tsdpvf->fn_list.disable_io_queues   = sdp_vf_disable_io_queues;\n+\n \tsdpvf->fn_list.enable_iq           = sdp_vf_enable_iq;\n+\tsdpvf->fn_list.disable_iq          = sdp_vf_disable_iq;\n+\n \tsdpvf->fn_list.enable_oq           = sdp_vf_enable_oq;\n+\tsdpvf->fn_list.disable_oq          = sdp_vf_disable_oq;\n \n \n \treturn 0;\n",
    "prefixes": [
        "v1",
        "3/6"
    ]
}