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GET /api/patches/63658/?format=api
{ "id": 63658, "url": "http://patches.dpdk.org/api/patches/63658/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-3-git-send-email-mchalla@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1575819342-20008-3-git-send-email-mchalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1575819342-20008-3-git-send-email-mchalla@marvell.com", "date": "2019-12-08T15:35:38", "name": "[v1,2/6] raw/octeontx2_ep: add device configuration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "686c3d1634dacaee454d212a132a5c57f437c348", "submitter": { "id": 1532, "url": "http://patches.dpdk.org/api/people/1532/?format=api", "name": "Mahipal Challa", "email": "mchalla@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-3-git-send-email-mchalla@marvell.com/mbox/", "series": [ { "id": 7751, "url": "http://patches.dpdk.org/api/series/7751/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7751", "date": "2019-12-08T15:35:36", "name": "OCTEON TX2 End Point Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/7751/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63658/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/63658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 98411A04F1;\n\tSun, 8 Dec 2019 16:36:33 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8D1851BF8D;\n\tSun, 8 Dec 2019 16:36:14 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id AE17A1BF89\n for <dev@dpdk.org>; Sun, 8 Dec 2019 16:36:13 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n xB8FUjhS028959 for <dev@dpdk.org>; Sun, 8 Dec 2019 07:36:13 -0800", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 2wrcfpts1q-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 08 Dec 2019 07:36:12 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 8 Dec\n 2019 07:36:10 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n Transport; Sun, 8 Dec 2019 07:36:10 -0800", "from hyd1244.marvell.com (hyd1244.marvell.com [10.29.20.28])\n by maili.marvell.com (Postfix) with ESMTP id 385603F703F;\n Sun, 8 Dec 2019 07:36:07 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=xTGl75BkGrE+5GQNfvtnxqrr2UvJle4nJ0SVBjfipDQ=;\n b=S34oiqHkxGky9TLZjVoR1/8Atp5CHt0gTA4GwBBZBM4g/AYJyoDb03TBqm/oeVo47S3Y\n RYDaCShu3NzZMb5H+JsXI7DJ7FyyV/QR8vOn/WGHrYcJFGcXMfxb6z06zzsQ+eNb90Pm\n gUde3AcRlmlZjjZuhKxCE9IyQOghOc1vmDY2eH7IoCkKjPBRkEPVCN/8OxzNt1uXwyNZ\n AIAk6tdErRrF29BgINfvQ2xaS2iw7DJjxgPO+UCOGMe93vqhrLN5FoiuH3LfQIwzZk4j\n K9JeQNK4bO5HsBkgybf1XMu+qkMa2MLyuQRijDaCh1lBFIm51gZZHKukBnorLUVTxSCN Eg==", "From": "Mahipal Challa <mchalla@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <pathreya@marvell.com>, <snilla@marvell.com>,\n <venkatn@marvell.com>", "Date": "Sun, 8 Dec 2019 21:05:38 +0530", "Message-ID": "<1575819342-20008-3-git-send-email-mchalla@marvell.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>", "References": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2019-12-08_04:2019-12-05,2019-12-08 signatures=0", "Subject": "[dpdk-dev] [PATCH v1 2/6] raw/octeontx2_ep: add device configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Register \"dev_configure\" API to configure/initialize the SDP\nVF PCIe devices.\n\nSigned-off-by: Mahipal Challa <mchalla@marvell.com>\n---\n doc/guides/rawdevs/octeontx2_ep.rst | 29 ++\n drivers/common/octeontx2/hw/otx2_sdp.h | 184 +++++++++\n drivers/common/octeontx2/otx2_common.c | 9 +\n drivers/common/octeontx2/otx2_common.h | 4 +\n .../octeontx2/rte_common_octeontx2_version.map | 6 +\n drivers/raw/octeontx2_ep/Makefile | 3 +\n drivers/raw/octeontx2_ep/meson.build | 4 +-\n drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 294 ++++++++++++++\n drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h | 11 +\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 148 +++++++\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 434 ++++++++++++++++++++-\n drivers/raw/octeontx2_ep/otx2_ep_vf.c | 408 +++++++++++++++++++\n drivers/raw/octeontx2_ep/otx2_ep_vf.h | 10 +\n 13 files changed, 1542 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst\nindex 5f5ed01..2507fcf 100644\n--- a/doc/guides/rawdevs/octeontx2_ep.rst\n+++ b/doc/guides/rawdevs/octeontx2_ep.rst\n@@ -39,3 +39,32 @@ entry `sriov_numvfs` for the corresponding PF driver.\n \n Once the required VFs are enabled, to be accessible from DPDK, VFs need to be\n bound to vfio-pci driver.\n+\n+Device Setup\n+------------\n+\n+The OCTEON TX2 SDP End Point VF devices will need to be bound to a\n+user-space IO driver for use. The script ``dpdk-devbind.py`` script\n+included with DPDK can be used to view the state of the devices and to bind\n+them to a suitable DPDK-supported kernel driver. When querying the status\n+of the devices, they will appear under the category of \"Misc (rawdev)\n+devices\", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be\n+used to see the state of those devices alone.\n+\n+Device Configuration\n+--------------------\n+\n+Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``\n+API, which takes the mempool as parameter. PMD uses this pool to send/receive\n+packets to/from the HW.\n+\n+The following code shows how the device is configured\n+\n+.. code-block:: c\n+\n+ struct sdp_rawdev_info config = {0};\n+ struct rte_rawdev_info rdev_info = {.dev_private = &config};\n+ config.enqdeq_mpool = (void *)rte_mempool_create(...);\n+\n+ rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info);\n+\ndiff --git a/drivers/common/octeontx2/hw/otx2_sdp.h b/drivers/common/octeontx2/hw/otx2_sdp.h\nnew file mode 100644\nindex 0000000..7e03317\n--- /dev/null\n+++ b/drivers/common/octeontx2/hw/otx2_sdp.h\n@@ -0,0 +1,184 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_SDP_HW_H_\n+#define __OTX2_SDP_HW_H_\n+\n+/* SDP VF IOQs */\n+#define SDP_MIN_RINGS_PER_VF (1)\n+#define SDP_MAX_RINGS_PER_VF (8)\n+\n+/* SDP VF IQ configuration */\n+#define SDP_VF_MAX_IQ_DESCRIPTORS (512)\n+#define SDP_VF_MIN_IQ_DESCRIPTORS (128)\n+\n+#define SDP_VF_DB_MIN (1)\n+#define SDP_VF_DB_TIMEOUT (1)\n+#define SDP_VF_INTR_THRESHOLD (0xFFFFFFFF)\n+\n+#define SDP_VF_64BYTE_INSTR (64)\n+#define SDP_VF_32BYTE_INSTR (32)\n+\n+/* SDP VF OQ configuration */\n+#define SDP_VF_MAX_OQ_DESCRIPTORS (512)\n+#define SDP_VF_MIN_OQ_DESCRIPTORS (128)\n+#define SDP_VF_OQ_BUF_SIZE (2048)\n+#define SDP_VF_OQ_REFIL_THRESHOLD (16)\n+\n+#define SDP_VF_OQ_INFOPTR_MODE (1)\n+#define SDP_VF_OQ_BUFPTR_MODE (0)\n+\n+#define SDP_VF_OQ_INTR_PKT (1)\n+#define SDP_VF_OQ_INTR_TIME (10)\n+#define SDP_VF_CFG_IO_QUEUES SDP_MAX_RINGS_PER_VF\n+\n+/* Wait time in milliseconds for FLR */\n+#define SDP_VF_PCI_FLR_WAIT (100)\n+#define SDP_VF_BUSY_LOOP_COUNT (10000)\n+\n+#define SDP_VF_MAX_IO_QUEUES SDP_MAX_RINGS_PER_VF\n+#define SDP_VF_MIN_IO_QUEUES SDP_MIN_RINGS_PER_VF\n+\n+/* SDP VF IOQs per rawdev */\n+#define SDP_VF_MAX_IOQS_PER_RAWDEV SDP_VF_MAX_IO_QUEUES\n+#define SDP_VF_DEFAULT_IOQS_PER_RAWDEV SDP_VF_MIN_IO_QUEUES\n+\n+/* SDP VF Register definitions */\n+#define SDP_VF_RING_OFFSET (0x1ull << 17)\n+\n+/* SDP VF IQ Registers */\n+#define SDP_VF_R_IN_CONTROL_START (0x10000)\n+#define SDP_VF_R_IN_ENABLE_START (0x10010)\n+#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)\n+#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)\n+#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)\n+#define SDP_VF_R_IN_CNTS_START (0x10050)\n+#define SDP_VF_R_IN_INT_LEVELS_START (0x10060)\n+#define SDP_VF_R_IN_PKT_CNT_START (0x10080)\n+#define SDP_VF_R_IN_BYTE_CNT_START (0x10090)\n+\n+#define SDP_VF_R_IN_CONTROL(ring) \\\n+\t(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_ENABLE(ring) \\\n+\t(SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_INSTR_BADDR(ring) \\\n+\t(SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_INSTR_RSIZE(ring) \\\n+\t(SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_INSTR_DBELL(ring) \\\n+\t(SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_CNTS(ring) \\\n+\t(SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_INT_LEVELS(ring) \\\n+\t(SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_PKT_CNT(ring) \\\n+\t(SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_IN_BYTE_CNT(ring) \\\n+\t(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+/* SDP VF IQ Masks */\n+#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)\n+#define\tSDP_VF_R_IN_CTL_RPVF_POS (48)\n+\n+#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28)\n+#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */\n+#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)\n+#define SDP_VF_R_IN_CTL_D_NSR (0x1ull << 8)\n+#define SDP_VF_R_IN_CTL_D_ESR (0x1ull << 6)\n+#define SDP_VF_R_IN_CTL_D_ROR (0x1ull << 5)\n+#define SDP_VF_R_IN_CTL_NSR (0x1ull << 3)\n+#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1)\n+#define SDP_VF_R_IN_CTL_ROR (0x1ull << 0)\n+\n+#define SDP_VF_R_IN_CTL_MASK \\\n+\t(SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B)\n+\n+/* SDP VF OQ Registers */\n+#define SDP_VF_R_OUT_CNTS_START (0x10100)\n+#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)\n+#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)\n+#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)\n+#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)\n+#define SDP_VF_R_OUT_CONTROL_START (0x10150)\n+#define SDP_VF_R_OUT_ENABLE_START (0x10160)\n+#define SDP_VF_R_OUT_PKT_CNT_START (0x10180)\n+#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)\n+\n+#define SDP_VF_R_OUT_CONTROL(ring) \\\n+\t(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_ENABLE(ring) \\\n+\t(SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_SLIST_BADDR(ring) \\\n+\t(SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \\\n+\t(SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_SLIST_DBELL(ring) \\\n+\t(SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_CNTS(ring) \\\n+\t(SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_INT_LEVELS(ring) \\\n+\t(SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_PKT_CNT(ring) \\\n+\t(SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+#define SDP_VF_R_OUT_BYTE_CNT(ring) \\\n+\t(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n+\n+/* SDP VF OQ Masks */\n+#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)\n+#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)\n+#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)\n+#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)\n+#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)\n+#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)\n+#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)\n+#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)\n+#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)\n+#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)\n+#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)\n+\n+#define SDP_VF_R_OUT_INT_LEVELS_BMODE (1ull << 63)\n+#define SDP_VF_R_OUT_INT_LEVELS_TIMET (32)\n+\n+/* SDP Instruction Header */\n+struct sdp_instr_ih {\n+\t/* Data Len */\n+\tuint64_t tlen:16;\n+\n+\t/* Reserved1 */\n+\tuint64_t rsvd1:20;\n+\n+\t/* PKIND for SDP */\n+\tuint64_t pkind:6;\n+\n+\t/* Front Data size */\n+\tuint64_t fsz:6;\n+\n+\t/* No. of entries in gather list */\n+\tuint64_t gsz:14;\n+\n+\t/* Gather indicator */\n+\tuint64_t gather:1;\n+\n+\t/* Reserved2 */\n+\tuint64_t rsvd2:1;\n+};\n+\n+#endif /* __OTX2_SDP_HW_H_ */\n+\ndiff --git a/drivers/common/octeontx2/otx2_common.c b/drivers/common/octeontx2/otx2_common.c\nindex 7e45366..1a257cf 100644\n--- a/drivers/common/octeontx2/otx2_common.c\n+++ b/drivers/common/octeontx2/otx2_common.c\n@@ -205,6 +205,10 @@ int otx2_npa_lf_obj_ref(void)\n * @internal\n */\n int otx2_logtype_dpi;\n+/**\n+ * @internal\n+ */\n+int otx2_logtype_ep;\n \n RTE_INIT(otx2_log_init);\n static void\n@@ -245,4 +249,9 @@ int otx2_npa_lf_obj_ref(void)\n \totx2_logtype_dpi = rte_log_register(\"pmd.raw.octeontx2.dpi\");\n \tif (otx2_logtype_dpi >= 0)\n \t\trte_log_set_level(otx2_logtype_dpi, RTE_LOG_NOTICE);\n+\n+\totx2_logtype_ep = rte_log_register(\"pmd.raw.octeontx2.ep\");\n+\tif (otx2_logtype_ep >= 0)\n+\t\trte_log_set_level(otx2_logtype_ep, RTE_LOG_NOTICE);\n+\n }\ndiff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h\nindex f62c45d..6bc55ca 100644\n--- a/drivers/common/octeontx2/otx2_common.h\n+++ b/drivers/common/octeontx2/otx2_common.h\n@@ -16,6 +16,7 @@\n #include \"hw/otx2_nix.h\"\n #include \"hw/otx2_npc.h\"\n #include \"hw/otx2_npa.h\"\n+#include \"hw/otx2_sdp.h\"\n #include \"hw/otx2_sso.h\"\n #include \"hw/otx2_ssow.h\"\n #include \"hw/otx2_tim.h\"\n@@ -85,6 +86,7 @@ struct otx2_idev_cfg {\n extern int otx2_logtype_tm;\n extern int otx2_logtype_tim;\n extern int otx2_logtype_dpi;\n+extern int otx2_logtype_ep;\n \n #define otx2_err(fmt, args...)\t\t\t\\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\",\t\\\n@@ -107,6 +109,7 @@ struct otx2_idev_cfg {\n #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)\n #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)\n #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)\n+#define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)\n \n /* PCI IDs */\n #define PCI_VENDOR_ID_CAVIUM\t\t\t0x177D\n@@ -121,6 +124,7 @@ struct otx2_idev_cfg {\n #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF\t\t0xA0FE\n #define PCI_DEVID_OCTEONTX2_RVU_AF_VF\t\t0xA0f8\n #define PCI_DEVID_OCTEONTX2_DPI_VF\t\t0xA081\n+#define PCI_DEVID_OCTEONTX2_EP_VF\t\t0xB203 /* OCTEON TX2 EP mode */\n #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF\t\t0xA0f6\n #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF\t\t0xA0f7\n \ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex adad21a..a51d719 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -33,3 +33,9 @@ DPDK_20.0 {\n \n \tlocal: *;\n };\n+\n+EXPERIMENTAL {\n+\tglobal:\n+\n+\totx2_logtype_ep;\n+};\ndiff --git a/drivers/raw/octeontx2_ep/Makefile b/drivers/raw/octeontx2_ep/Makefile\nindex 8cec6bd..02853fb 100644\n--- a/drivers/raw/octeontx2_ep/Makefile\n+++ b/drivers/raw/octeontx2_ep/Makefile\n@@ -36,5 +36,8 @@ LIBABIVER := 1\n # All source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += otx2_ep_rawdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += otx2_ep_enqdeq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += otx2_ep_vf.c\n+\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build\nindex e513131..99e6c6d 100644\n--- a/drivers/raw/octeontx2_ep/meson.build\n+++ b/drivers/raw/octeontx2_ep/meson.build\n@@ -3,4 +3,6 @@\n #\n \n deps += ['bus_pci', 'common_octeontx2', 'rawdev']\n-sources = files('otx2_ep_rawdev.c')\n+sources = files('otx2_ep_rawdev.c',\n+\t\t'otx2_ep_enqdeq.c',\n+\t\t'otx2_ep_vf.c')\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\nnew file mode 100644\nindex 0000000..8857004\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c\n@@ -0,0 +1,294 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <string.h>\n+#include <unistd.h>\n+#include <dirent.h>\n+#include <fcntl.h>\n+\n+#include <rte_bus.h>\n+#include <rte_bus_pci.h>\n+#include <rte_eal.h>\n+#include <rte_lcore.h>\n+#include <rte_mempool.h>\n+#include <rte_pci.h>\n+\n+#include <rte_common.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_ep_enqdeq.h\"\n+\n+/* IQ initialization */\n+static int\n+sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)\n+{\n+\tconst struct sdp_config *conf;\n+\tstruct sdp_instr_queue *iq;\n+\tuint32_t q_size;\n+\n+\tconf = sdpvf->conf;\n+\tiq = sdpvf->instr_queue[iq_no];\n+\tq_size = conf->iq.instr_type * conf->num_iqdef_descs;\n+\n+\t/* IQ memory creation for Instruction submission to OCTEON TX2 */\n+\tiq->iq_mz = rte_memzone_reserve_aligned(\"iqmz\",\n+\t\t\t\t\tq_size,\n+\t\t\t\t\trte_socket_id(),\n+\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (iq->iq_mz == NULL) {\n+\t\totx2_err(\"IQ[%d] memzone alloc failed\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\tiq->base_addr_dma = iq->iq_mz->iova;\n+\tiq->base_addr = (uint8_t *)iq->iq_mz->addr;\n+\n+\tif (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {\n+\t\totx2_err(\"IQ[%d] descs not in power of 2\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\tiq->nb_desc = conf->num_iqdef_descs;\n+\n+\t/* Create a IQ request list to hold requests that have been\n+\t * posted to OCTEON TX2. This list will be used for freeing the IQ\n+\t * data buffer(s) later once the OCTEON TX2 fetched the requests.\n+\t */\n+\tiq->req_list = rte_zmalloc_socket(\"request_list\",\n+\t\t\t(iq->nb_desc * SDP_IQREQ_LIST_SIZE),\n+\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\trte_socket_id());\n+\tif (iq->req_list == NULL) {\n+\t\totx2_err(\"IQ[%d] req_list alloc failed\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\totx2_info(\"IQ[%d]: base: %p basedma: %lx count: %d\",\n+\t\t iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,\n+\t\t iq->nb_desc);\n+\n+\tiq->sdp_dev = sdpvf;\n+\tiq->q_no = iq_no;\n+\tiq->fill_cnt = 0;\n+\tiq->host_write_index = 0;\n+\tiq->otx_read_index = 0;\n+\tiq->flush_index = 0;\n+\n+\t/* Initialize the spinlock for this instruction queue */\n+\trte_spinlock_init(&iq->lock);\n+\trte_spinlock_init(&iq->post_lock);\n+\n+\trte_atomic64_clear(&iq->iq_flush_running);\n+\n+\tsdpvf->io_qmask.iq |= (1ull << iq_no);\n+\n+\t/* Set 32B/64B mode for each input queue */\n+\tif (conf->iq.instr_type == 64)\n+\t\tsdpvf->io_qmask.iq64B |= (1ull << iq_no);\n+\n+\tiq->iqcmd_64B = (conf->iq.instr_type == 64);\n+\n+\t/* Set up IQ registers */\n+\tsdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);\n+\n+\treturn 0;\n+\n+iq_init_fail:\n+\treturn -ENOMEM;\n+\n+}\n+\n+int\n+sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)\n+{\n+\tstruct sdp_instr_queue *iq;\n+\n+\tiq = (struct sdp_instr_queue *)rte_zmalloc(\"sdp_IQ\", sizeof(*iq),\n+\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (iq == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsdpvf->instr_queue[iq_no] = iq;\n+\n+\tif (sdp_init_instr_queue(sdpvf, iq_no)) {\n+\t\totx2_err(\"IQ init is failed\");\n+\t\tgoto delete_IQ;\n+\t}\n+\totx2_info(\"IQ[%d] is created.\", sdpvf->num_iqs);\n+\n+\tsdpvf->num_iqs++;\n+\n+\n+\treturn 0;\n+\n+delete_IQ:\n+\treturn -ENOMEM;\n+}\n+\n+static void\n+sdp_droq_reset_indices(struct sdp_droq *droq)\n+{\n+\tdroq->read_idx = 0;\n+\tdroq->write_idx = 0;\n+\tdroq->refill_idx = 0;\n+\tdroq->refill_count = 0;\n+\trte_atomic64_set(&droq->pkts_pending, 0);\n+}\n+\n+static int\n+sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,\n+\t\tstruct sdp_droq *droq)\n+{\n+\tstruct sdp_droq_desc *desc_ring = droq->desc_ring;\n+\tuint32_t idx;\n+\tvoid *buf;\n+\n+\tfor (idx = 0; idx < droq->nb_desc; idx++) {\n+\t\trte_mempool_get(sdpvf->enqdeq_mpool, &buf);\n+\t\tif (buf == NULL) {\n+\t\t\totx2_err(\"OQ buffer alloc failed\");\n+\t\t\t/* sdp_droq_destroy_ring_buffers(droq);*/\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tdroq->recv_buf_list[idx].buffer = buf;\n+\t\tdroq->info_list[idx].length = 0;\n+\n+\t\t/* Map ring buffers into memory */\n+\t\tdesc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +\n+\t\t\t(idx * SDP_DROQ_INFO_SIZE));\n+\n+\t\tdesc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);\n+\t}\n+\n+\tsdp_droq_reset_indices(droq);\n+\n+\treturn 0;\n+}\n+\n+static void *\n+sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,\n+\tstruct sdp_droq *droq)\n+{\n+\tdroq->info_mz = rte_memzone_reserve_aligned(\"OQ_info_list\",\n+\t\t\t\t(droq->nb_desc * SDP_DROQ_INFO_SIZE),\n+\t\t\t\trte_socket_id(),\n+\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\n+\tif (droq->info_mz == NULL)\n+\t\treturn NULL;\n+\n+\tdroq->info_list_dma = droq->info_mz->iova;\n+\tdroq->info_alloc_size = droq->info_mz->len;\n+\tdroq->info_base_addr = (size_t)droq->info_mz->addr;\n+\n+\treturn droq->info_mz->addr;\n+}\n+\n+/* OQ initialization */\n+static int\n+sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)\n+{\n+\tconst struct sdp_config *conf = sdpvf->conf;\n+\tuint32_t c_refill_threshold;\n+\tuint32_t desc_ring_size;\n+\tstruct sdp_droq *droq;\n+\n+\totx2_info(\"OQ[%d] Init start\", q_no);\n+\n+\tdroq = sdpvf->droq[q_no];\n+\tdroq->sdp_dev = sdpvf;\n+\tdroq->q_no = q_no;\n+\n+\tc_refill_threshold = conf->oq.refill_threshold;\n+\tdroq->nb_desc = conf->num_oqdef_descs;\n+\tdroq->buffer_size = conf->oqdef_buf_size;\n+\n+\t/* OQ desc_ring set up */\n+\tdesc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;\n+\tdroq->desc_ring_mz = rte_memzone_reserve_aligned(\"sdp_oqmz\",\n+\t\t\t\t\t\tdesc_ring_size,\n+\t\t\t\t\t\trte_socket_id(),\n+\t\t\t\t\t\tRTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\n+\tif (droq->desc_ring_mz == NULL) {\n+\t\totx2_err(\"OQ:%d desc_ring allocation failed\", q_no);\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+\tdroq->desc_ring_dma = droq->desc_ring_mz->iova;\n+\tdroq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;\n+\n+\totx2_sdp_dbg(\"OQ[%d]: desc_ring: virt: 0x%p, dma: %lx\",\n+\t\t q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);\n+\totx2_sdp_dbg(\"OQ[%d]: num_desc: %d\", q_no, droq->nb_desc);\n+\n+\n+\t/* OQ info_list set up */\n+\tdroq->info_list = sdp_alloc_info_buffer(sdpvf, droq);\n+\tif (droq->info_list == NULL) {\n+\t\totx2_err(\"memory allocation failed for OQ[%d] info_list\", q_no);\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+\t/* OQ buf_list set up */\n+\tdroq->recv_buf_list = rte_zmalloc_socket(\"recv_buf_list\",\n+\t\t\t\t(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n+\tif (droq->recv_buf_list == NULL) {\n+\t\totx2_err(\"OQ recv_buf_list alloc failed\");\n+\t\tgoto init_droq_fail;\n+\t}\n+\n+\tif (sdp_droq_setup_ring_buffers(sdpvf, droq))\n+\t\tgoto init_droq_fail;\n+\n+\tdroq->refill_threshold = c_refill_threshold;\n+\trte_spinlock_init(&droq->lock);\n+\n+\n+\t/* Set up OQ registers */\n+\tsdpvf->fn_list.setup_oq_regs(sdpvf, q_no);\n+\n+\tsdpvf->io_qmask.oq |= (1ull << q_no);\n+\n+\treturn 0;\n+\n+init_droq_fail:\n+\treturn -ENOMEM;\n+}\n+\n+/* OQ configuration and setup */\n+int\n+sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)\n+{\n+\tstruct sdp_droq *droq;\n+\n+\t/* Allocate new droq. */\n+\tdroq = (struct sdp_droq *)rte_zmalloc(\"sdp_OQ\",\n+\t\t\t\tsizeof(*droq), RTE_CACHE_LINE_SIZE);\n+\tif (droq == NULL) {\n+\t\totx2_err(\"Droq[%d] Creation Failed\", oq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\tsdpvf->droq[oq_no] = droq;\n+\n+\tif (sdp_init_droq(sdpvf, oq_no)) {\n+\t\totx2_err(\"Droq[%d] Initialization failed\", oq_no);\n+\t\tgoto delete_OQ;\n+\t}\n+\totx2_info(\"OQ[%d] is created.\", oq_no);\n+\n+\tsdpvf->num_oqs++;\n+\n+\treturn 0;\n+\n+delete_OQ:\n+\treturn -ENOMEM;\n+}\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h\nnew file mode 100644\nindex 0000000..4c28283\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_EP_ENQDEQ_H_\n+#define _OTX2_EP_ENQDEQ_H_\n+\n+#include <rte_byteorder.h>\n+#include \"otx2_ep_rawdev.h\"\n+\n+#endif /* _OTX2_EP_ENQDEQ_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\nindex 04b4fac..5db9b50 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n@@ -17,6 +17,7 @@\n \n #include \"otx2_common.h\"\n #include \"otx2_ep_rawdev.h\"\n+#include \"otx2_ep_vf.h\"\n \n static const struct rte_pci_id pci_sdp_vf_map[] = {\n \t{\n@@ -28,6 +29,152 @@\n \t},\n };\n \n+/* SDP_VF default configuration */\n+const struct sdp_config default_sdp_conf = {\n+\t/* IQ attributes */\n+\t.iq = {\n+\t\t.max_iqs = SDP_VF_CFG_IO_QUEUES,\n+\t\t.instr_type = SDP_VF_64BYTE_INSTR,\n+\t\t.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *\n+\t\t\t\t SDP_VF_CFG_IO_QUEUES),\n+\t},\n+\n+\t/* OQ attributes */\n+\t.oq = {\n+\t\t.max_oqs = SDP_VF_CFG_IO_QUEUES,\n+\t\t.info_ptr = SDP_VF_OQ_INFOPTR_MODE,\n+\t\t.refill_threshold = SDP_VF_OQ_REFIL_THRESHOLD,\n+\t},\n+\n+\t.num_iqdef_descs = SDP_VF_MAX_IQ_DESCRIPTORS,\n+\t.num_oqdef_descs = SDP_VF_MAX_OQ_DESCRIPTORS,\n+\t.oqdef_buf_size = SDP_VF_OQ_BUF_SIZE,\n+\n+};\n+\n+const struct sdp_config*\n+sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)\n+{\n+\tconst struct sdp_config *default_conf = NULL;\n+\n+\tdefault_conf = &default_sdp_conf;\n+\n+\treturn default_conf;\n+}\n+\n+static int\n+sdp_chip_specific_setup(struct sdp_device *sdpvf)\n+{\n+\tstruct rte_pci_device *pdev = sdpvf->pci_dev;\n+\tuint32_t dev_id = pdev->id.device_id;\n+\tint ret;\n+\n+\tswitch (dev_id) {\n+\tcase PCI_DEVID_OCTEONTX2_EP_VF:\n+\t\tsdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_VF;\n+\t\tret = sdp_vf_setup_device(sdpvf);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\totx2_err(\"Unsupported device\");\n+\t\tret = -EINVAL;\n+\t}\n+\n+\tif (!ret)\n+\t\totx2_info(\"SDP dev_id[%d]\", dev_id);\n+\n+\treturn ret;\n+}\n+\n+/* SDP VF device initialization */\n+static int\n+sdp_vfdev_init(struct sdp_device *sdpvf)\n+{\n+\tuint32_t rawdev_queues, q;\n+\n+\tif (sdp_chip_specific_setup(sdpvf)) {\n+\t\totx2_err(\"Chip specific setup failed\");\n+\t\tgoto setup_fail;\n+\t}\n+\n+\tif (sdpvf->fn_list.setup_device_regs(sdpvf)) {\n+\t\totx2_err(\"Failed to configure device registers\");\n+\t\tgoto setup_fail;\n+\t}\n+\n+\trawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);\n+\n+\t/* Rawdev queues setup for enqueue/dequeue */\n+\tfor (q = 0; q < rawdev_queues; q++) {\n+\t\tif (sdp_setup_iqs(sdpvf, q)) {\n+\t\t\totx2_err(\"Failed to setup IQs\");\n+\t\t\tgoto iq_fail;\n+\t\t}\n+\t}\n+\totx2_info(\"Total[%d] IQs setup\", sdpvf->num_iqs);\n+\n+\tfor (q = 0; q < rawdev_queues; q++) {\n+\t\tif (sdp_setup_oqs(sdpvf, q)) {\n+\t\t\totx2_err(\"Failed to setup OQs\");\n+\t\t\tgoto oq_fail;\n+\t\t}\n+\t}\n+\totx2_info(\"Total [%d] OQs setup\", sdpvf->num_oqs);\n+\n+\t/* Enable IQ/OQ for this device */\n+\tsdpvf->fn_list.enable_io_queues(sdpvf);\n+\n+\t/* Send OQ desc credits for OQs, credits are always\n+\t * sent after the OQs are enabled.\n+\t */\n+\tfor (q = 0; q < rawdev_queues; q++) {\n+\t\trte_write32(sdpvf->droq[q]->nb_desc,\n+\t\t\t sdpvf->droq[q]->pkts_credit_reg);\n+\n+\t\trte_wmb();\n+\t\totx2_info(\"OQ[%d] dbells [%d]\", q,\n+\t\trte_read32(sdpvf->droq[q]->pkts_credit_reg));\n+\t}\n+\n+\trte_wmb();\n+\n+\totx2_info(\"SDP Device is Ready\");\n+\n+\treturn 0;\n+\n+oq_fail:\n+iq_fail:\n+setup_fail:\n+\treturn -ENOMEM;\n+}\n+\n+static int\n+sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n+{\n+\tstruct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;\n+\tstruct sdp_device *sdpvf;\n+\n+\tif (app_info == NULL) {\n+\t\totx2_err(\"Application config info [NULL]\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsdpvf = (struct sdp_device *)dev->dev_private;\n+\n+\tsdpvf->conf = app_info->app_conf;\n+\tsdpvf->enqdeq_mpool = app_info->enqdeq_mpool;\n+\n+\tsdp_vfdev_init(sdpvf);\n+\n+\treturn 0;\n+\n+}\n+\n+/* SDP VF endpoint rawdev ops */\n+static const struct rte_rawdev_ops sdp_rawdev_ops = {\n+\t.dev_configure = sdp_rawdev_configure,\n+};\n+\n static int\n otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t struct rte_pci_device *pci_dev)\n@@ -66,6 +213,7 @@\n \t\treturn -ENOMEM;\n \t}\n \n+\tsdp_rawdev->dev_ops = &sdp_rawdev_ops;\n \tsdp_rawdev->device = &pci_dev->device;\n \tsdp_rawdev->driver_name = pci_dev->driver->driver.name;\n \ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\nindex 7ae7a08..bb36b6a 100644\n--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n@@ -5,17 +5,449 @@\n #ifndef _OTX2_EP_RAWDEV_H_\n #define _OTX2_EP_RAWDEV_H_\n \n-#define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */\n+#include <rte_byteorder.h>\n+#include <rte_spinlock.h>\n+\n+\n+/* Input Request Header format */\n+struct sdp_instr_irh {\n+\t/* Request ID */\n+\tuint64_t rid:16;\n+\n+\t/* PCIe port to use for response */\n+\tuint64_t pcie_port:3;\n+\n+\t/* Scatter indicator 1=scatter */\n+\tuint64_t scatter:1;\n+\n+\t/* Size of Expected result OR no. of entries in scatter list */\n+\tuint64_t rlenssz:14;\n+\n+\t/* Desired destination port for result */\n+\tuint64_t dport:6;\n+\n+\t/* Opcode Specific parameters */\n+\tuint64_t param:8;\n+\n+\t/* Opcode for the return packet */\n+\tuint64_t opcode:16;\n+};\n+\n+/* SDP 32B instruction format */\n+struct sdp_instr_32B {\n+\t/* Pointer where the input data is available. */\n+\tuint64_t dptr;\n+\n+\t/* SDP Instruction Header. */\n+\tuint64_t ih;\n+\n+\t/** Pointer where the response for a RAW mode packet\n+\t * will be written by OCTEON TX2.\n+\t */\n+\tuint64_t rptr;\n+\n+\t/* Input Request Header. Additional info about the input. */\n+\tuint64_t irh;\n+};\n+#define SDP_32B_INSTR_SIZE\t(sizeof(sdp_instr_32B))\n+\n+/* SDP 64B instruction format */\n+struct sdp_instr_64B {\n+\t/* Pointer where the input data is available. */\n+\tuint64_t dptr;\n+\n+\t/* SDP Instruction Header. */\n+\tuint64_t ih;\n+\n+\t/** Pointer where the response for a RAW mode packet\n+\t * will be written by OCTEON TX2.\n+\t */\n+\tuint64_t rptr;\n+\n+\t/* Input Request Header. */\n+\tuint64_t irh;\n+\n+\t/* Additional headers available in a 64-byte instruction. */\n+\tuint64_t exhdr[4];\n+};\n+#define SDP_64B_INSTR_SIZE\t(sizeof(sdp_instr_64B))\n+\n+struct sdp_soft_instr {\n+\t/** Input data pointer. It is either pointing directly to input data\n+\t * or to a gather list.\n+\t */\n+\tvoid *dptr;\n+\n+\t/** Response from OCTEON TX2 comes at this address. It is either\n+\t * directlty pointing to output data buffer or to a scatter list.\n+\t */\n+\tvoid *rptr;\n+\n+\t/* The instruction header. All input commands have this field. */\n+\tstruct sdp_instr_ih ih;\n+\n+\t/* Input request header. */\n+\tstruct sdp_instr_irh irh;\n+\n+\t/** The PCI instruction to be sent to OCTEON TX2. This is stored in the\n+\t * instr to retrieve the physical address of buffers when instr is\n+\t * freed.\n+\t */\n+\tstruct sdp_instr_64B command;\n+\n+\t/** If a gather list was allocated, this ptr points to the buffer used\n+\t * for the gather list. The gather list has to be 8B aligned, so this\n+\t * value may be different from dptr.\n+\t */\n+\tvoid *gather_ptr;\n+\n+\t/* Total data bytes transferred in the gather mode request. */\n+\tuint64_t gather_bytes;\n+\n+\t/** If a scatter list was allocated, this ptr points to the buffer used\n+\t * for the scatter list. The scatter list has to be 8B aligned, so\n+\t * this value may be different from rptr.\n+\t */\n+\tvoid *scatter_ptr;\n+\n+\t/* Total data bytes to be received in the scatter mode request. */\n+\tuint64_t scatter_bytes;\n+\n+\t/* IQ number to which this instruction has to be submitted. */\n+\tuint32_t q_no;\n+\n+\t/* IQ instruction request type. */\n+\tuint32_t reqtype;\n+};\n+#define SDP_SOFT_INSTR_SIZE\t(sizeof(sdp_soft_instr))\n+\n+/* SDP IQ request list */\n+struct sdp_instr_list {\n+\tvoid *buf;\n+\tuint32_t reqtype;\n+};\n+#define SDP_IQREQ_LIST_SIZE\t(sizeof(struct sdp_instr_list))\n+\n+/* Structure to define the configuration attributes for each Input queue. */\n+struct sdp_iq_config {\n+\t/* Max number of IQs available */\n+\tuint16_t max_iqs;\n+\n+\t/* Command size - 32 or 64 bytes */\n+\tuint16_t instr_type;\n+\n+\t/* Pending list size, usually set to the sum of the size of all IQs */\n+\tuint32_t pending_list_size;\n+};\n+\n+/** The instruction (input) queue.\n+ * The input queue is used to post raw (instruction) mode data or packet data\n+ * to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one\n+ * such structure to represent it.\n+ */\n+struct sdp_instr_queue {\n+\t/* A spinlock to protect access to the input ring. */\n+\trte_spinlock_t lock;\n+\trte_spinlock_t post_lock;\n+\n+\tstruct sdp_device *sdp_dev;\n+\trte_atomic64_t iq_flush_running;\n+\n+\tuint32_t q_no;\n+\tuint32_t pkt_in_done;\n+\n+\t/* Flag for 64 byte commands. */\n+\tuint32_t iqcmd_64B:1;\n+\tuint32_t rsvd:17;\n+\tuint32_t status:8;\n+\n+\t/* Number of descriptors in this ring. */\n+\tuint32_t nb_desc;\n+\n+\t/* Input ring index, where the driver should write the next packet */\n+\tuint32_t host_write_index;\n+\n+\t/* Input ring index, where the OCTEON TX2 should read the next packet */\n+\tuint32_t otx_read_index;\n+\n+\t/** This index aids in finding the window in the queue where OCTEON TX2\n+\t * has read the commands.\n+\t */\n+\tuint32_t flush_index;\n+\n+\t/* This keeps track of the instructions pending in this queue. */\n+\trte_atomic64_t instr_pending;\n+\n+\tuint32_t reset_instr_cnt;\n+\n+\t/* Pointer to the Virtual Base addr of the input ring. */\n+\tuint8_t *base_addr;\n+\n+\t/* This IQ request list */\n+\tstruct sdp_instr_list *req_list;\n+\n+\t/* SDP doorbell register for the ring. */\n+\tvoid *doorbell_reg;\n+\n+\t/* SDP instruction count register for this ring. */\n+\tvoid *inst_cnt_reg;\n+\n+\t/* Number of instructions pending to be posted to OCTEON TX2. */\n+\tuint32_t fill_cnt;\n+\n+\t/* DMA mapped base address of the input descriptor ring. */\n+\tuint64_t base_addr_dma;\n+\n+\t/* Memory zone */\n+\tconst struct rte_memzone *iq_mz;\n+};\n+\n+/* DROQ packet format for application i/f. */\n+struct sdp_droq_pkt {\n+\t/* DROQ packet data buffer pointer. */\n+\tuint8_t\t *data;\n+\n+\t/* DROQ packet data length */\n+\tuint32_t len;\n+\n+\tuint32_t misc;\n+};\n+\n+/** Descriptor format.\n+ * The descriptor ring is made of descriptors which have 2 64-bit values:\n+ * -# Physical (bus) address of the data buffer.\n+ * -# Physical (bus) address of a sdp_droq_info structure.\n+ * The device DMA's incoming packets and its information at the address\n+ * given by these descriptor fields.\n+ */\n+struct sdp_droq_desc {\n+\t/* The buffer pointer */\n+\tuint64_t buffer_ptr;\n+\n+\t/* The Info pointer */\n+\tuint64_t info_ptr;\n+};\n+#define SDP_DROQ_DESC_SIZE\t(sizeof(struct sdp_droq_desc))\n+\n+/* Receive Header */\n+union sdp_rh {\n+\tuint64_t rh64;\n+};\n+#define SDP_RH_SIZE (sizeof(union sdp_rh))\n+\n+/** Information about packet DMA'ed by OCTEON TX2.\n+ * The format of the information available at Info Pointer after OCTEON TX2\n+ * has posted a packet. Not all descriptors have valid information. Only\n+ * the Info field of the first descriptor for a packet has information\n+ * about the packet.\n+ */\n+struct sdp_droq_info {\n+\t/* The Output Receive Header. */\n+\tunion sdp_rh rh;\n+\n+\t/* The Length of the packet. */\n+\tuint64_t length;\n+};\n+#define SDP_DROQ_INFO_SIZE\t(sizeof(struct sdp_droq_info))\n+\n+/** Pointer to data buffer.\n+ * Driver keeps a pointer to the data buffer that it made available to\n+ * the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)\n+ * addresses, this field is required for the driver to keep track of\n+ * the virtual address pointers.\n+ */\n+struct sdp_recv_buffer {\n+\t/* Packet buffer, including meta data. */\n+\tvoid *buffer;\n+\n+\t/* Data in the packet buffer. */\n+\t/* uint8_t *data; */\n+};\n+#define SDP_DROQ_RECVBUF_SIZE\t(sizeof(struct sdp_recv_buffer))\n+\n+/* Structure to define the configuration attributes for each Output queue. */\n+struct sdp_oq_config {\n+\t/* Max number of OQs available */\n+\tuint16_t max_oqs;\n+\n+\t/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */\n+\tuint16_t info_ptr;\n+\n+\t/** The number of buffers that were consumed during packet processing by\n+\t * the driver on this Output queue before the driver attempts to\n+\t * replenish the descriptor ring with new buffers.\n+\t */\n+\tuint32_t refill_threshold;\n+};\n+\n+/* The Descriptor Ring Output Queue(DROQ) structure. */\n+struct sdp_droq {\n+\t/* A spinlock to protect access to this ring. */\n+\trte_spinlock_t lock;\n+\n+\tstruct sdp_device *sdp_dev;\n+\t/* The 8B aligned descriptor ring starts at this address. */\n+\tstruct sdp_droq_desc *desc_ring;\n+\n+\tuint32_t q_no;\n+\tuint32_t last_pkt_count;\n+\n+\t/* Driver should read the next packet at this index */\n+\tuint32_t read_idx;\n+\n+\t/* OCTEON TX2 will write the next packet at this index */\n+\tuint32_t write_idx;\n+\n+\t/* At this index, the driver will refill the descriptor's buffer */\n+\tuint32_t refill_idx;\n+\n+\t/* Packets pending to be processed */\n+\trte_atomic64_t pkts_pending;\n+\n+\t/* Number of descriptors in this ring. */\n+\tuint32_t nb_desc;\n+\n+\t/* The number of descriptors pending to refill. */\n+\tuint32_t refill_count;\n+\n+\tuint32_t refill_threshold;\n+\n+\t/* The 8B aligned info ptrs begin from this address. */\n+\tstruct sdp_droq_info *info_list;\n+\n+\t/* receive buffer list contains virtual addresses of the buffers. */\n+\tstruct sdp_recv_buffer *recv_buf_list;\n+\n+\t/* The size of each buffer pointed by the buffer pointer. */\n+\tuint32_t buffer_size;\n+\n+\t/** Pointer to the mapped packet credit register.\n+\t * Host writes number of info/buffer ptrs available to this register\n+\t */\n+\tvoid *pkts_credit_reg;\n+\n+\t/** Pointer to the mapped packet sent register. OCTEON TX2 writes the\n+\t * number of packets DMA'ed to host memory in this register.\n+\t */\n+\tvoid *pkts_sent_reg;\n+\n+\t/* DMA mapped address of the DROQ descriptor ring. */\n+\tsize_t desc_ring_dma;\n+\n+\t/* Info_ptr list is allocated at this virtual address. */\n+\tsize_t info_base_addr;\n+\n+\t/* DMA mapped address of the info list */\n+\tsize_t info_list_dma;\n+\n+\t/* Allocated size of info list. */\n+\tuint32_t info_alloc_size;\n+\n+\t/* Memory zone **/\n+\tconst struct rte_memzone *desc_ring_mz;\n+\tconst struct rte_memzone *info_mz;\n+};\n+#define SDP_DROQ_SIZE\t\t(sizeof(struct sdp_droq))\n+\n+/* IQ/OQ mask */\n+struct sdp_io_enable {\n+\tuint64_t iq;\n+\tuint64_t oq;\n+\tuint64_t iq64B;\n+};\n+\n+/* Structure to define the configuration. */\n+struct sdp_config {\n+\t/* Input Queue attributes. */\n+\tstruct sdp_iq_config iq;\n+\n+\t/* Output Queue attributes. */\n+\tstruct sdp_oq_config oq;\n+\n+\t/* Num of desc for IQ rings */\n+\tuint32_t num_iqdef_descs;\n+\n+\t/* Num of desc for OQ rings */\n+\tuint32_t num_oqdef_descs;\n+\n+\t/* OQ buffer size */\n+\tuint32_t oqdef_buf_size;\n+};\n+\n+/* Required functions for each VF device */\n+struct sdp_fn_list {\n+\tvoid (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n+\tvoid (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);\n+\tint (*setup_device_regs)(struct sdp_device *sdpvf);\n+\tvoid (*enable_io_queues)(struct sdp_device *sdpvf);\n+\tvoid (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);\n+\tvoid (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);\n+};\n+\n+/* SRIOV information */\n+struct sdp_sriov_info {\n+\t/* Number of rings assigned to VF */\n+\tuint32_t rings_per_vf;\n+\n+\t/* Number of VF devices enabled */\n+\tuint32_t num_vfs;\n+};\n+\n+\n+/* Information to be passed from application */\n+struct sdp_rawdev_info {\n+\tstruct rte_mempool *enqdeq_mpool;\n+\tconst struct sdp_config *app_conf;\n+};\n \n /* SDP EP VF device */\n struct sdp_device {\n \t/* PCI device pointer */\n \tstruct rte_pci_device *pci_dev;\n+\tuint16_t chip_id;\n+\tuint16_t pf_num;\n \tuint16_t vf_num;\n \n+\t/* This device's PCIe port used for traffic. */\n+\tuint16_t pcie_port;\n+\tuint32_t pkind;\n+\n+\t/* The state of this device */\n+\trte_atomic64_t status;\n+\n \t/* Memory mapped h/w address */\n \tuint8_t *hw_addr;\n \n+\tstruct sdp_fn_list fn_list;\n+\n+\t/* Num IQs */\n+\tuint32_t num_iqs;\n+\n+\t/* The input instruction queues */\n+\tstruct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];\n+\n+\t/* Num OQs */\n+\tuint32_t num_oqs;\n+\n+\t/* The DROQ output queues */\n+\tstruct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];\n+\n+\t/* IOQ data buffer pool */\n+\tstruct rte_mempool *enqdeq_mpool;\n+\n+\t/* IOQ mask */\n+\tstruct sdp_io_enable io_qmask;\n+\n+\t/* SR-IOV info */\n+\tstruct sdp_sriov_info sriov_info;\n+\n+\t/* Device configuration */\n+\tconst struct sdp_config *conf;\n };\n \n+const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);\n+int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);\n+\n+int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);\n+\n #endif /* _OTX2_EP_RAWDEV_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c\nnew file mode 100644\nindex 0000000..b6120eb\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_vf.c\n@@ -0,0 +1,408 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_ep_rawdev.h\"\n+#include \"otx2_ep_vf.h\"\n+\n+static int\n+sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)\n+{\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\t/* There is no RST for a ring.\n+\t * Clear all registers one by one after disabling the ring\n+\t */\n+\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF; /* ~0ull */\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, sdpvf->hw_addr +\n+\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(sdpvf->hw_addr +\n+\t\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n+static int\n+sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)\n+{\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));\n+\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF;\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, sdpvf->hw_addr +\n+\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(sdpvf->hw_addr +\n+\t\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\twhile ((d64 != 0) && (loop--)) {\n+\t\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));\n+\totx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n+static void\n+sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\t/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs\n+\t * IS_64B is by default enabled.\n+\t */\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n+\n+\treg_val |= SDP_VF_R_IN_CTL_RDSIZE;\n+\treg_val |= SDP_VF_R_IN_CTL_IS_64B;\n+\treg_val |= SDP_VF_R_IN_CTL_ESR;\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));\n+\n+}\n+\n+static void\n+sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n+\n+\treg_val |= (SDP_VF_R_OUT_CTL_IMODE);\n+\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);\n+\treg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);\n+\n+\t/* INFO/DATA ptr swap is required */\n+\treg_val |= (SDP_VF_R_OUT_CTL_ES_P);\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n+\n+}\n+\n+static int\n+sdp_vf_reset_input_queues(struct sdp_device *sdpvf)\n+{\n+\tuint32_t q_no = 0;\n+\n+\totx2_sdp_dbg(\"%s :\", __func__);\n+\n+\tfor (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)\n+\t\tsdp_vf_reset_iq(sdpvf, q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+sdp_vf_reset_output_queues(struct sdp_device *sdpvf)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\totx2_sdp_dbg(\" %s :\", __func__);\n+\n+\tfor (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)\n+\t\tsdp_vf_reset_oq(sdpvf, q_no);\n+\n+\treturn 0;\n+}\n+\n+static void\n+sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\tsdp_vf_reset_input_queues(sdpvf);\n+\n+\tfor (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)\n+\t\tsdp_vf_setup_global_iq_reg(sdpvf, q_no);\n+}\n+\n+static void\n+sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)\n+{\n+\tuint32_t q_no;\n+\n+\tsdp_vf_reset_output_queues(sdpvf);\n+\n+\tfor (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)\n+\t\tsdp_vf_setup_global_oq_reg(sdpvf, q_no);\n+\n+}\n+\n+static int\n+sdp_vf_setup_device_regs(struct sdp_device *sdpvf)\n+{\n+\tsdp_vf_setup_global_input_regs(sdpvf);\n+\tsdp_vf_setup_global_output_regs(sdpvf);\n+\n+\treturn 0;\n+}\n+\n+static void\n+sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)\n+{\n+\tstruct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));\n+\n+\t/* Wait till IDLE to set to 1, not supposed to configure BADDR\n+\t * as long as IDLE is 0\n+\t */\n+\tif (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {\n+\t\tdo {\n+\t\t\treg_val = otx2_read64(sdpvf->hw_addr +\n+\t\t\t\t\t SDP_VF_R_IN_CONTROL(iq_no));\n+\t\t} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));\n+\t}\n+\n+\t/* Write the start of the input queue's ring and its size */\n+\totx2_write64(iq->base_addr_dma, sdpvf->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_BADDR(iq_no));\n+\totx2_write64(iq->nb_desc, sdpvf->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_RSIZE(iq_no));\n+\n+\t/* Remember the doorbell & instruction count register addr\n+\t * for this queue\n+\t */\n+\tiq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +\n+\t\t\t SDP_VF_R_IN_INSTR_DBELL(iq_no);\n+\tiq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +\n+\t\t\t SDP_VF_R_IN_CNTS(iq_no);\n+\n+\totx2_sdp_dbg(\"InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\",\n+\t\t iq_no, iq->doorbell_reg, iq->inst_cnt_reg);\n+\n+\t/* Store the current instrn counter(used in flush_iq calculation) */\n+\tiq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);\n+\n+\t/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR\n+\t * to raise\n+\t */\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n+\treg_val = 0xffffffff;\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));\n+\n+}\n+\n+static void\n+sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t oq_ctl = 0ull;\n+\n+\tstruct sdp_droq *droq = sdpvf->droq[oq_no];\n+\n+\t/* Wait on IDLE to set to 1, supposed to configure BADDR\n+\t * as log as IDLE is 0\n+\t */\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\twhile (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {\n+\t\treg_val = otx2_read64(sdpvf->hw_addr +\n+\t\t\t\t SDP_VF_R_OUT_CONTROL(oq_no));\n+\t}\n+\n+\totx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +\n+\t\t SDP_VF_R_OUT_SLIST_BADDR(oq_no));\n+\totx2_write64(droq->nb_desc, sdpvf->hw_addr +\n+\t\t SDP_VF_R_OUT_SLIST_RSIZE(oq_no));\n+\n+\toq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\t/* Clear the ISIZE and BSIZE (22-0) */\n+\toq_ctl &= ~(0x7fffffull);\n+\n+\t/* Populate the BSIZE (15-0) */\n+\toq_ctl |= (droq->buffer_size & 0xffff);\n+\n+\t/* Populate ISIZE(22-16) */\n+\toq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);\n+\totx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));\n+\n+\t/* Mapped address of the pkt_sent and pkts_credit regs */\n+\tdroq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +\n+\t\t\t SDP_VF_R_OUT_CNTS(oq_no);\n+\tdroq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +\n+\t\t\t\tSDP_VF_R_OUT_SLIST_DBELL(oq_no);\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));\n+\n+\t/* Clear PKT_CNT register */\n+\trte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +\n+\t\t SDP_VF_R_OUT_PKT_CNT(oq_no));\n+\n+\t/* Clear the OQ doorbell */\n+\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\twhile ((rte_read32(droq->pkts_credit_reg) != 0ull)) {\n+\t\trte_write32(0xFFFFFFFF, droq->pkts_credit_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+\totx2_sdp_dbg(\"SDP_R[%d]_credit:%x\", oq_no,\n+\t\t rte_read32(droq->pkts_credit_reg));\n+\n+\t/* Clear the OQ_OUT_CNTS doorbell */\n+\treg_val = rte_read32(droq->pkts_sent_reg);\n+\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\n+\totx2_sdp_dbg(\"SDP_R[%d]_sent: %x\", oq_no,\n+\t\t rte_read32(droq->pkts_sent_reg));\n+\n+\twhile (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {\n+\t\treg_val = rte_read32(droq->pkts_sent_reg);\n+\t\trte_write32((uint32_t)reg_val, droq->pkts_sent_reg);\n+\t\trte_delay_ms(1);\n+\t}\n+\n+}\n+\n+static void\n+sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\n+\t/* Resetting doorbells during IQ enabling also to handle abrupt\n+\t * guest reboot. IQ reset does not clear the doorbells.\n+\t */\n+\totx2_write64(0xFFFFFFFF, sdpvf->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile (((otx2_read64(sdpvf->hw_addr +\n+\t\t SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {\n+\n+\t\trte_delay_ms(1);\n+\t}\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\n+\totx2_info(\"IQ[%d] enable done\", q_no);\n+\n+}\n+\n+static void\n+sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)\n+{\n+\tvolatile uint64_t reg_val = 0ull;\n+\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\treg_val |= 0x1ull;\n+\totx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+\totx2_info(\"OQ[%d] enable done\", q_no);\n+}\n+\n+static void\n+sdp_vf_enable_io_queues(struct sdp_device *sdpvf)\n+{\n+\tuint32_t q_no = 0;\n+\n+\tfor (q_no = 0; q_no < sdpvf->num_iqs; q_no++)\n+\t\tsdp_vf_enable_iq(sdpvf, q_no);\n+\n+\tfor (q_no = 0; q_no < sdpvf->num_oqs; q_no++)\n+\t\tsdp_vf_enable_oq(sdpvf, q_no);\n+}\n+\n+int\n+sdp_vf_setup_device(struct sdp_device *sdpvf)\n+{\n+\tuint64_t reg_val = 0ull;\n+\n+\t/* If application doesn't provide its conf, use driver default conf */\n+\tif (sdpvf->conf == NULL) {\n+\t\tsdpvf->conf = sdp_get_defconf(sdpvf);\n+\t\tif (sdpvf->conf == NULL) {\n+\t\t\totx2_err(\"SDP VF default config not found\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\totx2_info(\"Default config is used\");\n+\t}\n+\n+\t/* Get IOQs (RPVF] count */\n+\treg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));\n+\n+\tsdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)\n+\t\t\t\t\t & SDP_VF_R_IN_CTL_RPVF_MASK);\n+\n+\totx2_info(\"SDP RPVF: %d\", sdpvf->sriov_info.rings_per_vf);\n+\n+\tsdpvf->fn_list.setup_iq_regs = sdp_vf_setup_iq_regs;\n+\tsdpvf->fn_list.setup_oq_regs = sdp_vf_setup_oq_regs;\n+\tsdpvf->fn_list.setup_device_regs = sdp_vf_setup_device_regs;\n+\tsdpvf->fn_list.enable_io_queues = sdp_vf_enable_io_queues;\n+\tsdpvf->fn_list.enable_iq = sdp_vf_enable_iq;\n+\tsdpvf->fn_list.enable_oq = sdp_vf_enable_oq;\n+\n+\n+\treturn 0;\n+\n+}\n+\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h\nnew file mode 100644\nindex 0000000..974f856\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_vf.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+#ifndef _OTX2_EP_VF_H_\n+#define _OTX2_EP_VF_H_\n+int\n+sdp_vf_setup_device(struct sdp_device *sdpvf);\n+\n+#endif /*_OTX2_EP_VF_H_ */\n+\n", "prefixes": [ "v1", "2/6" ] }