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GET /api/patches/63657/?format=api
{ "id": 63657, "url": "http://patches.dpdk.org/api/patches/63657/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-2-git-send-email-mchalla@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1575819342-20008-2-git-send-email-mchalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1575819342-20008-2-git-send-email-mchalla@marvell.com", "date": "2019-12-08T15:35:37", "name": "[v1,1/6] raw/octeontx2_ep: add build infra and device probe", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b72fdd47fc41d856286e554726e561c7b2072329", "submitter": { "id": 1532, "url": "http://patches.dpdk.org/api/people/1532/?format=api", "name": "Mahipal Challa", "email": "mchalla@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1575819342-20008-2-git-send-email-mchalla@marvell.com/mbox/", "series": [ { "id": 7751, "url": "http://patches.dpdk.org/api/series/7751/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7751", "date": "2019-12-08T15:35:36", "name": "OCTEON TX2 End Point Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/7751/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63657/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/63657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C5591A04F1;\n\tSun, 8 Dec 2019 16:36:20 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8832E1BF7E;\n\tSun, 8 Dec 2019 16:36:11 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 91FDD1BF7B\n for <dev@dpdk.org>; Sun, 8 Dec 2019 16:36:10 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n xB8FTmil028132 for <dev@dpdk.org>; Sun, 8 Dec 2019 07:36:10 -0800", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0b-0016f401.pphosted.com with ESMTP id 2wrcfpts1m-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 08 Dec 2019 07:36:09 -0800", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 8 Dec\n 2019 07:36:07 -0800", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n Transport; Sun, 8 Dec 2019 07:36:07 -0800", "from hyd1244.marvell.com (hyd1244.marvell.com [10.29.20.28])\n by maili.marvell.com (Postfix) with ESMTP id 133A63F7040;\n Sun, 8 Dec 2019 07:36:05 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=Gq3L/6EOoQw8hSgPH5tS8VR6Ub/vhdrSM1RxhXpkZEs=;\n b=XkC2VHLsT+Zc6wM9uj1NHfJvLJCRrr1o5zD78cXJQAuXxg3qgTZgo5oE4wzgOCG73jmI\n sOOaiSzA9ZIl3RixZXut+QkGa8XaFW+sjz6VXxxEDrgjDAmLt/gpNGgrOsOfxuBjyK8F\n FUB8elAF5i45ZTzkBRlHtqEIoeIbFbHDWcqUOaCc0NbgEob0kYVOWq8V3/zVXen5/2Ek\n 6lRsKFkQWcOW6TrrbybAtNAxY3jG7MKog1ykRjkUPCklzvRJk9UDTx9h/ym6jUZEqEwg\n L54OIggOGyFGERA4jSGrFihFHELiAdcPD04aqaxUXGmFEcN4X0oSQC2f0xMibgtcJ/1E JQ==", "From": "Mahipal Challa <mchalla@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <pathreya@marvell.com>, <snilla@marvell.com>,\n <venkatn@marvell.com>", "Date": "Sun, 8 Dec 2019 21:05:37 +0530", "Message-ID": "<1575819342-20008-2-git-send-email-mchalla@marvell.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>", "References": "<1575819342-20008-1-git-send-email-mchalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,18.0.572\n definitions=2019-12-08_04:2019-12-05,2019-12-08 signatures=0", "Subject": "[dpdk-dev] [PATCH v1 1/6] raw/octeontx2_ep: add build infra and\n\tdevice probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the OCTEON TX2 SDP EP device probe along with the\nbuild infrastructure for Make and meson builds.\n\nSigned-off-by: Mahipal Challa <mchalla@marvell.com>\n---\n MAINTAINERS | 5 +\n config/common_base | 5 +\n doc/guides/rawdevs/index.rst | 1 +\n doc/guides/rawdevs/octeontx2_ep.rst | 41 +++++++\n drivers/raw/Makefile | 1 +\n drivers/raw/meson.build | 1 +\n drivers/raw/octeontx2_ep/Makefile | 40 +++++++\n drivers/raw/octeontx2_ep/meson.build | 6 +\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 132 +++++++++++++++++++++\n drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 21 ++++\n .../rte_rawdev_octeontx2_ep_version.map | 4 +\n mk/rte.app.mk | 2 +\n 12 files changed, 259 insertions(+)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 4395d8d..24f1240 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1173,6 +1173,11 @@ M: Vamsi Attunuru <vattunuru@marvell.com>\n F: drivers/raw/octeontx2_dma/\n F: doc/guides/rawdevs/octeontx2_dma.rst\n \n+Marvell OCTEON TX2 EP\n+M: Mahipal Challa <mchalla@marvell.com>\n+F: drivers/raw/octeontx2_ep/\n+F: doc/guides/rawdevs/octeontx2_ep.rst\n+\n NTB\n M: Xiaoyun Li <xiaoyun.li@intel.com>\n M: Jingjing Wu <jingjing.wu@intel.com>\ndiff --git a/config/common_base b/config/common_base\nindex 7dec7ed..8e7dad2 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -796,6 +796,11 @@ CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=y\n CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV=y\n \n #\n+# Compile PMD for octeontx2 EP raw device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV=y\n+\n+#\n # Compile PMD for NTB raw device\n #\n CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV=y\ndiff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst\nindex 22bc013..f64ec44 100644\n--- a/doc/guides/rawdevs/index.rst\n+++ b/doc/guides/rawdevs/index.rst\n@@ -17,3 +17,4 @@ application through rawdev API.\n ioat\n ntb\n octeontx2_dma\n+ octeontx2_ep\ndiff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst\nnew file mode 100644\nindex 0000000..5f5ed01\n--- /dev/null\n+++ b/doc/guides/rawdevs/octeontx2_ep.rst\n@@ -0,0 +1,41 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Marvell International Ltd.\n+\n+Marvell OCTEON TX2 End Point Rawdev Driver\n+==========================================\n+\n+OCTEON TX2 has an internal SDP unit which provides End Point mode of operation\n+by exposing its IOQs to Host, IOQs are used for packet I/O between Host and\n+OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is\n+associated with a set of IOQ pairs.\n+\n+Features\n+--------\n+\n+This OCTEON TX2 End Point mode PMD supports\n+\n+#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.\n+\n+#. Packet Output - OCTEON TX2 to Host with info pointer mode.\n+\n+Config File Options\n+~~~~~~~~~~~~~~~~~~~\n+\n+The following options can be modified in the ``config`` file.\n+\n+- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV`` (default ``y``)\n+\n+ Toggle compilation of the ``lrte_pmd_octeontx2_ep`` driver.\n+\n+Initialization\n+--------------\n+\n+The number of SDP VFs enabled, can be controlled by setting sysfs\n+entry `sriov_numvfs` for the corresponding PF driver.\n+\n+.. code-block:: console\n+\n+ echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\\:04\\:00.0/sriov_numvfs\n+\n+Once the required VFs are enabled, to be accessible from DPDK, VFs need to be\n+bound to vfio-pci driver.\ndiff --git a/drivers/raw/Makefile b/drivers/raw/Makefile\nindex 0b6d13d..80b043e 100644\n--- a/drivers/raw/Makefile\n+++ b/drivers/raw/Makefile\n@@ -13,5 +13,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += ifpga\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += ioat\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += ntb\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += octeontx2_dma\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += octeontx2_ep\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/raw/meson.build b/drivers/raw/meson.build\nindex d7037cd..bb57977 100644\n--- a/drivers/raw/meson.build\n+++ b/drivers/raw/meson.build\n@@ -4,6 +4,7 @@\n drivers = ['dpaa2_cmdif', 'dpaa2_qdma',\n \t'ifpga', 'ioat', 'ntb',\n \t'octeontx2_dma',\n+\t'octeontx2_ep',\n \t'skeleton']\n std_deps = ['rawdev']\n config_flag_fmt = 'RTE_LIBRTE_PMD_@0@_RAWDEV'\ndiff --git a/drivers/raw/octeontx2_ep/Makefile b/drivers/raw/octeontx2_ep/Makefile\nnew file mode 100644\nindex 0000000..8cec6bd\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/Makefile\n@@ -0,0 +1,40 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# Library name\n+LIB = librte_rawdev_octeontx2_ep.a\n+\n+# Build flags\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+\n+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2/\n+CFLAGS += -I$(RTE_SDK)/drivers/raw/octeontx2_ep/\n+\n+LDLIBS += -lrte_eal\n+LDLIBS += -lrte_rawdev\n+LDLIBS += -lrte_bus_pci\n+LDLIBS += -lrte_mempool\n+LDLIBS += -lrte_common_octeontx2\n+\n+ifneq ($(CONFIG_RTE_ARCH_64),y)\n+CFLAGS += -Wno-int-to-pointer-cast\n+CFLAGS += -Wno-pointer-to-int-cast\n+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)\n+CFLAGS += -diag-disable 2259\n+endif\n+endif\n+\n+EXPORT_MAP := rte_rawdev_octeontx2_ep_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# All source are stored in SRCS-y\n+#\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += otx2_ep_rawdev.c\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build\nnew file mode 100644\nindex 0000000..e513131\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/meson.build\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+deps += ['bus_pci', 'common_octeontx2', 'rawdev']\n+sources = files('otx2_ep_rawdev.c')\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\nnew file mode 100644\nindex 0000000..04b4fac\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c\n@@ -0,0 +1,132 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+#include <string.h>\n+#include <unistd.h>\n+\n+#include <rte_bus.h>\n+#include <rte_bus_pci.h>\n+#include <rte_eal.h>\n+#include <rte_lcore.h>\n+#include <rte_mempool.h>\n+#include <rte_pci.h>\n+\n+#include <rte_common.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_ep_rawdev.h\"\n+\n+static const struct rte_pci_id pci_sdp_vf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t PCI_DEVID_OCTEONTX2_EP_VF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static int\n+otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct sdp_device *sdpvf = NULL;\n+\tstruct rte_rawdev *sdp_rawdev;\n+\tuint16_t vf_id;\n+\n+\t/* Single process support */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (pci_dev->mem_resource[0].addr)\n+\t\totx2_info(\"SDP_EP BAR0 is mapped:\");\n+\telse {\n+\t\totx2_err(\"SDP_EP: Failed to map device BARs\");\n+\t\totx2_err(\"BAR0 %p\\n BAR2 %p\",\n+\t\t\tpci_dev->mem_resource[0].addr,\n+\t\t\tpci_dev->mem_resource[2].addr);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tmemset(name, 0, sizeof(name));\n+\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"SDPEP:%x:%02x.%x\",\n+\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n+\t\t pci_dev->addr.function);\n+\n+\t/* Allocate rawdev pmd */\n+\tsdp_rawdev = rte_rawdev_pmd_allocate(name,\n+\t\t\t\t\t sizeof(struct sdp_device),\n+\t\t\t\t\t rte_socket_id());\n+\n+\tif (sdp_rawdev == NULL) {\n+\t\totx2_err(\"SDP_EP VF rawdev allocation failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tsdp_rawdev->device = &pci_dev->device;\n+\tsdp_rawdev->driver_name = pci_dev->driver->driver.name;\n+\n+\tsdpvf = (struct sdp_device *)sdp_rawdev->dev_private;\n+\tsdpvf->hw_addr = pci_dev->mem_resource[0].addr;\n+\tsdpvf->pci_dev = pci_dev;\n+\n+\t/* Discover the VF number being probed */\n+\tvf_id = ((pci_dev->addr.devid & 0x1F) << 3) |\n+\t\t (pci_dev->addr.function & 0x7);\n+\n+\tvf_id -= 1;\n+\tsdpvf->vf_num = vf_id;\n+\n+\totx2_info(\"SDP_EP VF[%d] probe done\", vf_id);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n+\tstruct rte_rawdev *rawdev;\n+\tstruct sdp_device *sdpvf;\n+\n+\t/* Single process support */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tif (pci_dev == NULL) {\n+\t\totx2_err(\"SDP_EP:invalid pci_dev!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\n+\tmemset(name, 0, sizeof(name));\n+\tsnprintf(name, RTE_RAWDEV_NAME_MAX_LEN, \"SDPEP:%x:%02x.%x\",\n+\t\t pci_dev->addr.bus, pci_dev->addr.devid,\n+\t\t pci_dev->addr.function);\n+\n+\trawdev = rte_rawdev_pmd_get_named_dev(name);\n+\tif (rawdev == NULL) {\n+\t\totx2_err(\"SDP_EP: invalid device name (%s)\", name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsdpvf = (struct sdp_device *)rawdev->dev_private;\n+\totx2_info(\"Removing SDP_EP VF[%d] \", sdpvf->vf_num);\n+\n+\t/* rte_rawdev_close is called by pmd_release */\n+\treturn rte_rawdev_pmd_release(rawdev);\n+}\n+\n+static struct rte_pci_driver rte_sdp_rawdev_pmd = {\n+\t.id_table = pci_sdp_vf_map,\n+\t.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),\n+\t.probe = otx2_sdp_rawdev_probe,\n+\t.remove = otx2_sdp_rawdev_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);\n+RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, \"vfio-pci\");\ndiff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\nnew file mode 100644\nindex 0000000..7ae7a08\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_EP_RAWDEV_H_\n+#define _OTX2_EP_RAWDEV_H_\n+\n+#define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */\n+\n+/* SDP EP VF device */\n+struct sdp_device {\n+\t/* PCI device pointer */\n+\tstruct rte_pci_device *pci_dev;\n+\tuint16_t vf_num;\n+\n+\t/* Memory mapped h/w address */\n+\tuint8_t *hw_addr;\n+\n+};\n+\n+#endif /* _OTX2_EP_RAWDEV_H_ */\ndiff --git a/drivers/raw/octeontx2_ep/rte_rawdev_octeontx2_ep_version.map b/drivers/raw/octeontx2_ep/rte_rawdev_octeontx2_ep_version.map\nnew file mode 100644\nindex 0000000..ff357af\n--- /dev/null\n+++ b/drivers/raw/octeontx2_ep/rte_rawdev_octeontx2_ep_version.map\n@@ -0,0 +1,4 @@\n+DPDK_20.02 {\n+\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 05ea034..24353e9 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -116,6 +116,7 @@ OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)\n ifeq ($(findstring y,$(OCTEONTX2-y)),y)\n _LDLIBS-y += -lrte_common_octeontx2\n@@ -336,6 +337,7 @@ endif # CONFIG_RTE_LIBRTE_IFPGA_BUS\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += -lrte_rawdev_ioat\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += -lrte_rawdev_ntb\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += -lrte_rawdev_octeontx2_dma\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV) += -lrte_rawdev_octeontx2_ep\n endif # CONFIG_RTE_LIBRTE_RAWDEV\n \n endif # !CONFIG_RTE_BUILD_SHARED_LIBS\n", "prefixes": [ "v1", "1/6" ] }