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GET /api/patches/63612/?format=api
{ "id": 63612, "url": "http://patches.dpdk.org/api/patches/63612/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191206181336.6180-2-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191206181336.6180-2-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191206181336.6180-2-arkadiuszx.kusztal@intel.com", "date": "2019-12-06T18:13:35", "name": "[1/2] crypto/qat: add chacha poly implementation", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b97e0cb095a3416d848c7cdb270c70e99ba92b61", "submitter": { "id": 452, "url": "http://patches.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191206181336.6180-2-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 7744, "url": "http://patches.dpdk.org/api/series/7744/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7744", "date": "2019-12-06T18:13:34", "name": "Add chacha20-poly1305 algorithm to QAT", "version": 1, "mbox": "http://patches.dpdk.org/series/7744/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63612/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63612/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 833F1A04F2;\n\tFri, 6 Dec 2019 19:13:55 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D1F941BF81;\n\tFri, 6 Dec 2019 19:13:49 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id 93DFC5B3A\n for <dev@dpdk.org>; Fri, 6 Dec 2019 19:13:47 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 06 Dec 2019 10:13:47 -0800", "from akusztax-mobl.ger.corp.intel.com ([10.104.116.190])\n by orsmga002.jf.intel.com with ESMTP; 06 Dec 2019 10:13:45 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,285,1571727600\"; d=\"scan'208\";a=\"224088064\"", "From": "Arek Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "akhil.goyal@nxp.com, fiona.trahe@intel.com,\n Arek Kusztal <arkadiuszx.kusztal@intel.com>", "Date": "Fri, 6 Dec 2019 19:13:35 +0100", "Message-Id": "<20191206181336.6180-2-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.19.1.windows.1", "In-Reply-To": "<20191206181336.6180-1-arkadiuszx.kusztal@intel.com>", "References": "<20191206181336.6180-1-arkadiuszx.kusztal@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 1/2] crypto/qat: add chacha poly implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patchset adds Chacha20-Poly1305 implementation to Intel\nQuickAssist Technology pmd.\n\nSigned-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>\n---\n doc/guides/cryptodevs/qat.rst | 1 +\n doc/guides/rel_notes/release_20_02.rst | 4 ++++\n drivers/common/qat/qat_adf/icp_qat_hw.h | 17 ++++++++++++++--\n drivers/crypto/qat/qat_sym_capabilities.h | 32 +++++++++++++++++++++++++++++++\n drivers/crypto/qat/qat_sym_pmd.c | 11 ++++++++++-\n drivers/crypto/qat/qat_sym_session.c | 20 +++++++++++++++----\n 6 files changed, 78 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst\nindex 6197875..479f5cc 100644\n--- a/doc/guides/cryptodevs/qat.rst\n+++ b/doc/guides/cryptodevs/qat.rst\n@@ -70,6 +70,7 @@ Supported AEAD algorithms:\n \n * ``RTE_CRYPTO_AEAD_AES_GCM``\n * ``RTE_CRYPTO_AEAD_AES_CCM``\n+* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``\n \n \n Limitations\ndiff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst\nindex 6b60f47..72504ab 100644\n--- a/doc/guides/rel_notes/release_20_02.rst\n+++ b/doc/guides/rel_notes/release_20_02.rst\n@@ -60,6 +60,10 @@ New Features\n \n Chacha20-Poly1305 AEAD algorithm can now be supported in Cryptodev.\n \n+* **Updated the Intel QuickAssist Technology (QAT) symmetric crypto PMD.**\n+\n+ Added Chacha20-Poly1305 AEAD algorithm.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h\nindex cef6486..ed04178 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_hw.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h\n@@ -51,7 +51,10 @@ enum icp_qat_hw_auth_algo {\n \tICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,\n \tICP_QAT_HW_AUTH_RESERVED_3 = 18,\n \tICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,\n-\tICP_QAT_HW_AUTH_ALGO_DELIMITER = 20\n+\tICP_QAT_HW_AUTH_ALGO_SHAKE_128 = 20,\n+\tICP_QAT_HW_AUTH_ALGO_SHAKE_256 = 21,\n+\tICP_QAT_HW_AUTH_ALGO_POLY = 22,\n+\tICP_QAT_HW_AUTH_ALGO_DELIMITER = 23\n };\n \n enum icp_qat_hw_auth_mode {\n@@ -204,7 +207,9 @@ enum icp_qat_hw_cipher_algo {\n \tICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,\n \tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,\n \tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,\n-\tICP_QAT_HW_CIPHER_DELIMITER = 10\n+\tICP_QAT_HW_CIPHER_ALGO_SM4 = 10,\n+\tICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11,\n+\tICP_QAT_HW_CIPHER_DELIMITER = 12\n };\n \n enum icp_qat_hw_cipher_mode {\n@@ -306,6 +311,14 @@ enum icp_qat_hw_cipher_convert {\n #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16\n #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16\n #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2\n+#define ICP_QAT_HW_SM4_KEY_SZ 16\n+#define ICP_QAT_HW_SM4_IV_SZ 16\n+#define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32\n+#define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12\n+#define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64\n+#define ICP_QAT_HW_SPC_CTR_SZ 16\n+#define ICP_QAT_HW_CHACHAPOLY_ICV__SZ 16\n+#define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14\n \n #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ\n \ndiff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h\nindex 028a56c..acc5045 100644\n--- a/drivers/crypto/qat/qat_sym_capabilities.h\n+++ b/drivers/crypto/qat/qat_sym_capabilities.h\n@@ -594,4 +594,36 @@\n \t\t}, }\t\t\t\t\t\t\t\\\n \t}\n \n+#define QAT_EXTRA_GEN3_SYM_CAPABILITIES\t\t\t\t\t\\\n+\t{\t/* Chacha20-Poly1305 */\t\t\t\t\t\\\n+\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\t\t\t\\\n+\t\t{.sym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\t\\\n+\t\t\t{.aead = {\t\t\t\t\t\\\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305,\t\\\n+\t\t\t\t.block_size = 64,\t\t\t\\\n+\t\t\t\t.key_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 32,\t\t\t\\\n+\t\t\t\t\t.max = 32,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.digest_size = {\t\t\t\\\n+\t\t\t\t\t.min = 16,\t\t\t\\\n+\t\t\t\t\t.max = 16,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.aad_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 0,\t\t\t\\\n+\t\t\t\t\t.max = 240,\t\t\t\\\n+\t\t\t\t\t.increment = 1\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t\t.iv_size = {\t\t\t\t\\\n+\t\t\t\t\t.min = 12,\t\t\t\\\n+\t\t\t\t\t.max = 12,\t\t\t\\\n+\t\t\t\t\t.increment = 0\t\t\t\\\n+\t\t\t\t},\t\t\t\t\t\\\n+\t\t\t}, }\t\t\t\t\t\t\\\n+\t\t}, }\t\t\t\t\t\t\t\\\n+\t}\n+\n #endif /* _QAT_SYM_CAPABILITIES_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 71f21ce..a6e2d24 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -27,6 +27,13 @@ static const struct rte_cryptodev_capabilities qat_gen2_sym_capabilities[] = {\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \n+static const struct rte_cryptodev_capabilities qat_gen3_sym_capabilities[] = {\n+\tQAT_BASE_GEN1_SYM_CAPABILITIES,\n+\tQAT_EXTRA_GEN2_SYM_CAPABILITIES,\n+\tQAT_EXTRA_GEN3_SYM_CAPABILITIES,\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n static int qat_sym_qp_release(struct rte_cryptodev *dev,\n \tuint16_t queue_pair_id);\n \n@@ -291,9 +298,11 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev)\n \t\tinternals->qat_dev_capabilities = qat_gen1_sym_capabilities;\n \t\tbreak;\n \tcase QAT_GEN2:\n-\tcase QAT_GEN3:\n \t\tinternals->qat_dev_capabilities = qat_gen2_sym_capabilities;\n \t\tbreak;\n+\tcase QAT_GEN3:\n+\t\tinternals->qat_dev_capabilities = qat_gen3_sym_capabilities;\n+\t\tbreak;\n \tdefault:\n \t\tinternals->qat_dev_capabilities = qat_gen2_sym_capabilities;\n \t\tQAT_LOG(DEBUG,\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 72290ba..c6ca42c 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -519,7 +519,8 @@ qat_sym_session_handle_single_pass(struct qat_sym_dev_private *internals,\n \t\tsession->is_single_pass = 1;\n \t\tsession->min_qat_dev_gen = QAT_GEN3;\n \t\tsession->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER;\n-\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_AEAD_MODE;\n+\t\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM)\n+\t\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_AEAD_MODE;\n \t\tsession->cipher_iv.offset = aead_xform->iv.offset;\n \t\tsession->cipher_iv.length = aead_xform->iv.length;\n \t\tif (qat_sym_session_aead_create_cd_cipher(session,\n@@ -566,6 +567,7 @@ qat_sym_session_handle_single_pass(struct qat_sym_dev_private *internals,\n \t\t\t\t\taead_xform->aad_length);\n \t\tcipher_param->spc_aad_sz = aead_xform->aad_length;\n \t\tcipher_param->spc_auth_res_sz = aead_xform->digest_length;\n+\n \t}\n \treturn 0;\n }\n@@ -727,6 +729,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \tsession->cipher_iv.offset = xform->aead.iv.offset;\n \tsession->cipher_iv.length = xform->aead.iv.length;\n \n+\tsession->is_single_pass = 0;\n \tswitch (aead_xform->algo) {\n \tcase RTE_CRYPTO_AEAD_AES_GCM:\n \t\tif (qat_sym_validate_aes_key(aead_xform->key.length,\n@@ -746,15 +749,24 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC;\n \t\tbreak;\n+\tcase RTE_CRYPTO_AEAD_CHACHA20_POLY1305:\n+\t\tif (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)\n+\t\t\treturn -EINVAL;\n+\t\tsession->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tsession->min_qat_dev_gen = QAT_GEN3;\n+\t\tsession->is_single_pass = 1;\n+\t\tbreak;\n \tdefault:\n \t\tQAT_LOG(ERR, \"Crypto: Undefined AEAD specified %u\\n\",\n \t\t\t\taead_xform->algo);\n \t\treturn -EINVAL;\n \t}\n \n-\tsession->is_single_pass = 0;\n-\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t/* Use faster Single-Pass GCM if possible */\n+\tif (aead_xform->algo == RTE_CRYPTO_AEAD_AES_GCM ||\n+\t\taead_xform->algo == RTE_CRYPTO_AEAD_CHACHA20_POLY1305) {\n+\t\t/* Use faster Single-Pass GCM if possible, for ChachaPoly\n+\t\t\tit always is single pass */\n \t\tint res = qat_sym_session_handle_single_pass(\n \t\t\t\tdev->data->dev_private, session, aead_xform);\n \t\tif (res < 0)\n", "prefixes": [ "1/2" ] }