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{
    "id": 63527,
    "url": "http://patches.dpdk.org/api/patches/63527/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191203070318.39620-6-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191203070318.39620-6-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191203070318.39620-6-qi.z.zhang@intel.com",
    "date": "2019-12-03T07:03:06",
    "name": "[05/17] net/iavf/base: remove unused code",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "be5b3f40831a5243a0325fcb5d2eeeae9749c494",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191203070318.39620-6-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 7716,
            "url": "http://patches.dpdk.org/api/series/7716/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7716",
            "date": "2019-12-03T07:03:01",
            "name": "iavf base code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/7716/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/63527/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/63527/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 907FDA04B5;\n\tTue,  3 Dec 2019 08:01:10 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 80C6C5B3C;\n\tTue,  3 Dec 2019 08:00:27 +0100 (CET)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 6C87C1BF78\n for <dev@dpdk.org>; Tue,  3 Dec 2019 08:00:24 +0100 (CET)",
            "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 02 Dec 2019 23:00:23 -0800",
            "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga005.fm.intel.com with ESMTP; 02 Dec 2019 23:00:20 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.69,272,1571727600\"; d=\"scan'208\";a=\"410729681\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "xiaolong.ye@intel.com",
        "Cc": "haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Tue,  3 Dec 2019 15:03:06 +0800",
        "Message-Id": "<20191203070318.39620-6-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20191203070318.39620-1-qi.z.zhang@intel.com>",
        "References": "<20191203070318.39620-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 05/17] net/iavf/base: remove unused code",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Remove unused APIs in iavf_prototype.h, iavf_adminq_cmd.h\niavf_type.h, iavf_adminq.h and iavf_common.c\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/iavf/base/iavf_adminq.c     |   27 +-\n drivers/net/iavf/base/iavf_adminq.h     |   43 -\n drivers/net/iavf/base/iavf_adminq_cmd.h | 2344 ++-----------------------------\n drivers/net/iavf/base/iavf_common.c     |  787 -----------\n drivers/net/iavf/base/iavf_prototype.h  |   83 --\n drivers/net/iavf/base/iavf_type.h       | 1109 +--------------\n 6 files changed, 168 insertions(+), 4225 deletions(-)",
    "diff": "diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c\nindex 193e2e7d1..68c51daac 100644\n--- a/drivers/net/iavf/base/iavf_adminq.c\n+++ b/drivers/net/iavf/base/iavf_adminq.c\n@@ -17,18 +17,16 @@\n STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)\n {\n \t/* set head and tail registers in our local struct */\n-\tif (iavf_is_vf(hw)) {\n-\t\thw->aq.asq.tail = IAVF_VF_ATQT1;\n-\t\thw->aq.asq.head = IAVF_VF_ATQH1;\n-\t\thw->aq.asq.len  = IAVF_VF_ATQLEN1;\n-\t\thw->aq.asq.bal  = IAVF_VF_ATQBAL1;\n-\t\thw->aq.asq.bah  = IAVF_VF_ATQBAH1;\n-\t\thw->aq.arq.tail = IAVF_VF_ARQT1;\n-\t\thw->aq.arq.head = IAVF_VF_ARQH1;\n-\t\thw->aq.arq.len  = IAVF_VF_ARQLEN1;\n-\t\thw->aq.arq.bal  = IAVF_VF_ARQBAL1;\n-\t\thw->aq.arq.bah  = IAVF_VF_ARQBAH1;\n-\t}\n+\thw->aq.asq.tail = IAVF_VF_ATQT1;\n+\thw->aq.asq.head = IAVF_VF_ATQH1;\n+\thw->aq.asq.len  = IAVF_VF_ATQLEN1;\n+\thw->aq.asq.bal  = IAVF_VF_ATQBAL1;\n+\thw->aq.asq.bah  = IAVF_VF_ATQBAH1;\n+\thw->aq.arq.tail = IAVF_VF_ARQT1;\n+\thw->aq.arq.head = IAVF_VF_ARQH1;\n+\thw->aq.arq.len  = IAVF_VF_ARQLEN1;\n+\thw->aq.arq.bal  = IAVF_VF_ARQBAL1;\n+\thw->aq.arq.bah  = IAVF_VF_ARQBAH1;\n }\n \n /**\n@@ -549,8 +547,6 @@ enum iavf_status iavf_init_adminq(struct iavf_hw *hw)\n \tif (ret_code != IAVF_SUCCESS)\n \t\tgoto init_adminq_free_asq;\n \n-\tret_code = IAVF_SUCCESS;\n-\n \t/* success! */\n \tgoto init_adminq_exit;\n \n@@ -580,9 +576,6 @@ enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)\n \tiavf_destroy_spinlock(&hw->aq.asq_spinlock);\n \tiavf_destroy_spinlock(&hw->aq.arq_spinlock);\n \n-\tif (hw->nvm_buff.va)\n-\t\tiavf_free_virt_mem(hw, &hw->nvm_buff);\n-\n \treturn ret_code;\n }\n \ndiff --git a/drivers/net/iavf/base/iavf_adminq.h b/drivers/net/iavf/base/iavf_adminq.h\nindex 715621644..bdc5e0187 100644\n--- a/drivers/net/iavf/base/iavf_adminq.h\n+++ b/drivers/net/iavf/base/iavf_adminq.h\n@@ -84,49 +84,6 @@ struct iavf_adminq_info {\n \tenum iavf_admin_queue_err arq_last_status;\n };\n \n-/**\n- * iavf_aq_rc_to_posix - convert errors to user-land codes\n- * aq_ret: AdminQ handler error code can override aq_rc\n- * aq_rc: AdminQ firmware error code to convert\n- **/\n-STATIC INLINE int iavf_aq_rc_to_posix(int aq_ret, int aq_rc)\n-{\n-\tint aq_to_posix[] = {\n-\t\t0,           /* IAVF_AQ_RC_OK */\n-\t\t-EPERM,      /* IAVF_AQ_RC_EPERM */\n-\t\t-ENOENT,     /* IAVF_AQ_RC_ENOENT */\n-\t\t-ESRCH,      /* IAVF_AQ_RC_ESRCH */\n-\t\t-EINTR,      /* IAVF_AQ_RC_EINTR */\n-\t\t-EIO,        /* IAVF_AQ_RC_EIO */\n-\t\t-ENXIO,      /* IAVF_AQ_RC_ENXIO */\n-\t\t-E2BIG,      /* IAVF_AQ_RC_E2BIG */\n-\t\t-EAGAIN,     /* IAVF_AQ_RC_EAGAIN */\n-\t\t-ENOMEM,     /* IAVF_AQ_RC_ENOMEM */\n-\t\t-EACCES,     /* IAVF_AQ_RC_EACCES */\n-\t\t-EFAULT,     /* IAVF_AQ_RC_EFAULT */\n-\t\t-EBUSY,      /* IAVF_AQ_RC_EBUSY */\n-\t\t-EEXIST,     /* IAVF_AQ_RC_EEXIST */\n-\t\t-EINVAL,     /* IAVF_AQ_RC_EINVAL */\n-\t\t-ENOTTY,     /* IAVF_AQ_RC_ENOTTY */\n-\t\t-ENOSPC,     /* IAVF_AQ_RC_ENOSPC */\n-\t\t-ENOSYS,     /* IAVF_AQ_RC_ENOSYS */\n-\t\t-ERANGE,     /* IAVF_AQ_RC_ERANGE */\n-\t\t-EPIPE,      /* IAVF_AQ_RC_EFLUSHED */\n-\t\t-ESPIPE,     /* IAVF_AQ_RC_BAD_ADDR */\n-\t\t-EROFS,      /* IAVF_AQ_RC_EMODE */\n-\t\t-EFBIG,      /* IAVF_AQ_RC_EFBIG */\n-\t};\n-\n-\t/* aq_rc is invalid if AQ timed out */\n-\tif (aq_ret == IAVF_ERR_ADMIN_QUEUE_TIMEOUT)\n-\t\treturn -EAGAIN;\n-\n-\tif (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))\n-\t\treturn -ERANGE;\n-\n-\treturn aq_to_posix[aq_rc];\n-}\n-\n /* general information */\n #define IAVF_AQ_LARGE_BUF\t512\n #define IAVF_ASQ_CMD_TIMEOUT\t250000  /* usecs */\ndiff --git a/drivers/net/iavf/base/iavf_adminq_cmd.h b/drivers/net/iavf/base/iavf_adminq_cmd.h\nindex 45388c8b7..b0ee0b082 100644\n--- a/drivers/net/iavf/base/iavf_adminq_cmd.h\n+++ b/drivers/net/iavf/base/iavf_adminq_cmd.h\n@@ -11,7 +11,6 @@\n  * This file needs to comply with the Linux Kernel coding style.\n  */\n \n-\n #define IAVF_FW_API_VERSION_MAJOR\t0x0001\n #define IAVF_FW_API_VERSION_MINOR_X722\t0x0005\n #define IAVF_FW_API_VERSION_MINOR_X710\t0x0007\n@@ -317,33 +316,6 @@ enum iavf_admin_queue_opc {\n  */\n #define IAVF_CHECK_CMD_LENGTH(X)\tIAVF_CHECK_STRUCT_LEN(16, X)\n \n-/* internal (0x00XX) commands */\n-\n-/* Get version (direct 0x0001) */\n-struct iavf_aqc_get_version {\n-\t__le32 rom_ver;\n-\t__le32 fw_build;\n-\t__le16 fw_major;\n-\t__le16 fw_minor;\n-\t__le16 api_major;\n-\t__le16 api_minor;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);\n-\n-/* Send driver version (indirect 0x0002) */\n-struct iavf_aqc_driver_version {\n-\tu8\tdriver_major_ver;\n-\tu8\tdriver_minor_ver;\n-\tu8\tdriver_build_ver;\n-\tu8\tdriver_subbuild_ver;\n-\tu8\treserved[4];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);\n-\n /* Queue Shutdown (direct 0x0003) */\n struct iavf_aqc_queue_shutdown {\n \t__le32\tdriver_unloading;\n@@ -353,493 +325,9 @@ struct iavf_aqc_queue_shutdown {\n \n IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);\n \n-/* Set PF context (0x0004, direct) */\n-struct iavf_aqc_set_pf_context {\n-\tu8\tpf_id;\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);\n-\n-/* Request resource ownership (direct 0x0008)\n- * Release resource ownership (direct 0x0009)\n- */\n-#define IAVF_AQ_RESOURCE_NVM\t\t\t1\n-#define IAVF_AQ_RESOURCE_SDP\t\t\t2\n-#define IAVF_AQ_RESOURCE_ACCESS_READ\t\t1\n-#define IAVF_AQ_RESOURCE_ACCESS_WRITE\t\t2\n-#define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT\t3000\n-#define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT\t180000\n-\n-struct iavf_aqc_request_resource {\n-\t__le16\tresource_id;\n-\t__le16\taccess_type;\n-\t__le32\ttimeout;\n-\t__le32\tresource_number;\n-\tu8\treserved[4];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);\n-\n-/* Get function capabilities (indirect 0x000A)\n- * Get device capabilities (indirect 0x000B)\n- */\n-struct iavf_aqc_list_capabilites {\n-\tu8 command_flags;\n-#define IAVF_AQ_LIST_CAP_PF_INDEX_EN\t1\n-\tu8 pf_index;\n-\tu8 reserved[2];\n-\t__le32 count;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);\n-\n-struct iavf_aqc_list_capabilities_element_resp {\n-\t__le16\tid;\n-\tu8\tmajor_rev;\n-\tu8\tminor_rev;\n-\t__le32\tnumber;\n-\t__le32\tlogical_id;\n-\t__le32\tphys_id;\n-\tu8\treserved[16];\n-};\n-\n-/* list of caps */\n-\n-#define IAVF_AQ_CAP_ID_SWITCH_MODE\t0x0001\n-#define IAVF_AQ_CAP_ID_MNG_MODE\t\t0x0002\n-#define IAVF_AQ_CAP_ID_NPAR_ACTIVE\t0x0003\n-#define IAVF_AQ_CAP_ID_OS2BMC_CAP\t0x0004\n-#define IAVF_AQ_CAP_ID_FUNCTIONS_VALID\t0x0005\n-#define IAVF_AQ_CAP_ID_ALTERNATE_RAM\t0x0006\n-#define IAVF_AQ_CAP_ID_WOL_AND_PROXY\t0x0008\n-#define IAVF_AQ_CAP_ID_SRIOV\t\t0x0012\n-#define IAVF_AQ_CAP_ID_VF\t\t0x0013\n-#define IAVF_AQ_CAP_ID_VMDQ\t\t0x0014\n-#define IAVF_AQ_CAP_ID_8021QBG\t\t0x0015\n-#define IAVF_AQ_CAP_ID_8021QBR\t\t0x0016\n-#define IAVF_AQ_CAP_ID_VSI\t\t0x0017\n-#define IAVF_AQ_CAP_ID_DCB\t\t0x0018\n-#define IAVF_AQ_CAP_ID_FCOE\t\t0x0021\n-#define IAVF_AQ_CAP_ID_ISCSI\t\t0x0022\n-#define IAVF_AQ_CAP_ID_RSS\t\t0x0040\n-#define IAVF_AQ_CAP_ID_RXQ\t\t0x0041\n-#define IAVF_AQ_CAP_ID_TXQ\t\t0x0042\n-#define IAVF_AQ_CAP_ID_MSIX\t\t0x0043\n-#define IAVF_AQ_CAP_ID_VF_MSIX\t\t0x0044\n-#define IAVF_AQ_CAP_ID_FLOW_DIRECTOR\t0x0045\n-#define IAVF_AQ_CAP_ID_1588\t\t0x0046\n-#define IAVF_AQ_CAP_ID_IWARP\t\t0x0051\n-#define IAVF_AQ_CAP_ID_LED\t\t0x0061\n-#define IAVF_AQ_CAP_ID_SDP\t\t0x0062\n-#define IAVF_AQ_CAP_ID_MDIO\t\t0x0063\n-#define IAVF_AQ_CAP_ID_WSR_PROT\t\t0x0064\n-#define IAVF_AQ_CAP_ID_NVM_MGMT\t\t0x0080\n-#define IAVF_AQ_CAP_ID_FLEX10\t\t0x00F1\n-#define IAVF_AQ_CAP_ID_CEM\t\t0x00F2\n-\n-/* Set CPPM Configuration (direct 0x0103) */\n-struct iavf_aqc_cppm_configuration {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQ_CPPM_EN_LTRC\t0x0800\n-#define IAVF_AQ_CPPM_EN_DMCTH\t0x1000\n-#define IAVF_AQ_CPPM_EN_DMCTLX\t0x2000\n-#define IAVF_AQ_CPPM_EN_HPTC\t0x4000\n-#define IAVF_AQ_CPPM_EN_DMARC\t0x8000\n-\t__le16\tttlx;\n-\t__le32\tdmacr;\n-\t__le16\tdmcth;\n-\tu8\thptc;\n-\tu8\treserved;\n-\t__le32\tpfltrc;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);\n-\n-/* Set ARP Proxy command / response (indirect 0x0104) */\n-struct iavf_aqc_arp_proxy_data {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQ_ARP_INIT_IPV4\t0x0800\n-#define IAVF_AQ_ARP_UNSUP_CTL\t0x1000\n-#define IAVF_AQ_ARP_ENA\t\t0x2000\n-#define IAVF_AQ_ARP_ADD_IPV4\t0x4000\n-#define IAVF_AQ_ARP_DEL_IPV4\t0x8000\n-\t__le16\ttable_id;\n-\t__le32\tenabled_offloads;\n-#define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE\t0x00000020\n-#define IAVF_AQ_ARP_OFFLOAD_ENABLE\t\t0x00000800\n-\t__le32\tip_addr;\n-\tu8\tmac_addr[6];\n-\tu8\treserved[2];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);\n-\n-/* Set NS Proxy Table Entry Command (indirect 0x0105) */\n-struct iavf_aqc_ns_proxy_data {\n-\t__le16\ttable_idx_mac_addr_0;\n-\t__le16\ttable_idx_mac_addr_1;\n-\t__le16\ttable_idx_ipv6_0;\n-\t__le16\ttable_idx_ipv6_1;\n-\t__le16\tcontrol;\n-#define IAVF_AQ_NS_PROXY_ADD_0\t\t0x0001\n-#define IAVF_AQ_NS_PROXY_DEL_0\t\t0x0002\n-#define IAVF_AQ_NS_PROXY_ADD_1\t\t0x0004\n-#define IAVF_AQ_NS_PROXY_DEL_1\t\t0x0008\n-#define IAVF_AQ_NS_PROXY_ADD_IPV6_0\t0x0010\n-#define IAVF_AQ_NS_PROXY_DEL_IPV6_0\t0x0020\n-#define IAVF_AQ_NS_PROXY_ADD_IPV6_1\t0x0040\n-#define IAVF_AQ_NS_PROXY_DEL_IPV6_1\t0x0080\n-#define IAVF_AQ_NS_PROXY_COMMAND_SEQ\t0x0100\n-#define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL\t0x0200\n-#define IAVF_AQ_NS_PROXY_INIT_MAC_TBL\t0x0400\n-#define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE\t0x0800\n-#define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE\t0x1000\n-\tu8\tmac_addr_0[6];\n-\tu8\tmac_addr_1[6];\n-\tu8\tlocal_mac_addr[6];\n-\tu8\tipv6_addr_0[16]; /* Warning! spec specifies BE byte order */\n-\tu8\tipv6_addr_1[16];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);\n-\n-/* Manage LAA Command (0x0106) - obsolete */\n-struct iavf_aqc_mng_laa {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQ_LAA_FLAG_WR\t0x8000\n-\tu8\treserved[2];\n-\t__le32\tsal;\n-\t__le16\tsah;\n-\tu8\treserved2[6];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);\n-\n-/* Manage MAC Address Read Command (indirect 0x0107) */\n-struct iavf_aqc_mac_address_read {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQC_LAN_ADDR_VALID\t\t0x10\n-#define IAVF_AQC_SAN_ADDR_VALID\t\t0x20\n-#define IAVF_AQC_PORT_ADDR_VALID\t0x40\n-#define IAVF_AQC_WOL_ADDR_VALID\t\t0x80\n-#define IAVF_AQC_MC_MAG_EN_VALID\t0x100\n #define IAVF_AQC_WOL_PRESERVE_STATUS\t0x200\n-#define IAVF_AQC_ADDR_VALID_MASK\t0x3F0\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);\n-\n-struct iavf_aqc_mac_address_read_data {\n-\tu8 pf_lan_mac[6];\n-\tu8 pf_san_mac[6];\n-\tu8 port_mac[6];\n-\tu8 pf_wol_mac[6];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);\n-\n-/* Manage MAC Address Write Command (0x0108) */\n-struct iavf_aqc_mac_address_write {\n-\t__le16\tcommand_flags;\n #define IAVF_AQC_MC_MAG_EN\t\t0x0100\n #define IAVF_AQC_WOL_PRESERVE_ON_PFR\t0x0200\n-#define IAVF_AQC_WRITE_TYPE_LAA_ONLY\t0x0000\n-#define IAVF_AQC_WRITE_TYPE_LAA_WOL\t0x4000\n-#define IAVF_AQC_WRITE_TYPE_PORT\t0x8000\n-#define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG\t0xC000\n-#define IAVF_AQC_WRITE_TYPE_MASK\t0xC000\n-\n-\t__le16\tmac_sah;\n-\t__le32\tmac_sal;\n-\tu8\treserved[8];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);\n-\n-/* PXE commands (0x011x) */\n-\n-/* Clear PXE Command and response  (direct 0x0110) */\n-struct iavf_aqc_clear_pxe {\n-\tu8\trx_cnt;\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);\n-\n-/* Set WoL Filter (0x0120) */\n-\n-struct iavf_aqc_set_wol_filter {\n-\t__le16 filter_index;\n-#define IAVF_AQC_MAX_NUM_WOL_FILTERS\t8\n-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT\t15\n-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK\t(0x1 << \\\n-\t\tIAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)\n-\n-#define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT\t\t0\n-#define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK\t(0x7 << \\\n-\t\tIAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)\n-\t__le16 cmd_flags;\n-#define IAVF_AQC_SET_WOL_FILTER\t\t\t\t0x8000\n-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL\t\t0x4000\n-#define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR\t0x2000\n-#define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR\t\t0\n-#define IAVF_AQC_SET_WOL_FILTER_ACTION_SET\t\t1\n-\t__le16 valid_flags;\n-#define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID\t\t0x8000\n-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID\t0x4000\n-\tu8 reserved[2];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);\n-\n-struct iavf_aqc_set_wol_filter_data {\n-\tu8 filter[128];\n-\tu8 mask[16];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);\n-\n-/* Get Wake Reason (0x0121) */\n-\n-struct iavf_aqc_get_wake_reason_completion {\n-\tu8 reserved_1[2];\n-\t__le16 wake_reason;\n-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT\t0\n-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \\\n-\t\tIAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)\n-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT\t8\n-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK\t(0xFF << \\\n-\t\tIAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)\n-\tu8 reserved_2[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);\n-\n-/* Switch configuration commands (0x02xx) */\n-\n-/* Used by many indirect commands that only pass an seid and a buffer in the\n- * command\n- */\n-struct iavf_aqc_switch_seid {\n-\t__le16\tseid;\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);\n-\n-/* Get Switch Configuration command (indirect 0x0200)\n- * uses iavf_aqc_switch_seid for the descriptor\n- */\n-struct iavf_aqc_get_switch_config_header_resp {\n-\t__le16\tnum_reported;\n-\t__le16\tnum_total;\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);\n-\n-struct iavf_aqc_switch_config_element_resp {\n-\tu8\telement_type;\n-#define IAVF_AQ_SW_ELEM_TYPE_MAC\t1\n-#define IAVF_AQ_SW_ELEM_TYPE_PF\t\t2\n-#define IAVF_AQ_SW_ELEM_TYPE_VF\t\t3\n-#define IAVF_AQ_SW_ELEM_TYPE_EMP\t4\n-#define IAVF_AQ_SW_ELEM_TYPE_BMC\t5\n-#define IAVF_AQ_SW_ELEM_TYPE_PV\t\t16\n-#define IAVF_AQ_SW_ELEM_TYPE_VEB\t17\n-#define IAVF_AQ_SW_ELEM_TYPE_PA\t\t18\n-#define IAVF_AQ_SW_ELEM_TYPE_VSI\t19\n-\tu8\trevision;\n-#define IAVF_AQ_SW_ELEM_REV_1\t\t1\n-\t__le16\tseid;\n-\t__le16\tuplink_seid;\n-\t__le16\tdownlink_seid;\n-\tu8\treserved[3];\n-\tu8\tconnection_type;\n-#define IAVF_AQ_CONN_TYPE_REGULAR\t0x1\n-#define IAVF_AQ_CONN_TYPE_DEFAULT\t0x2\n-#define IAVF_AQ_CONN_TYPE_CASCADED\t0x3\n-\t__le16\tscheduler_id;\n-\t__le16\telement_info;\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);\n-\n-/* Get Switch Configuration (indirect 0x0200)\n- *    an array of elements are returned in the response buffer\n- *    the first in the array is the header, remainder are elements\n- */\n-struct iavf_aqc_get_switch_config_resp {\n-\tstruct iavf_aqc_get_switch_config_header_resp\theader;\n-\tstruct iavf_aqc_switch_config_element_resp\telement[1];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);\n-\n-/* Add Statistics (direct 0x0201)\n- * Remove Statistics (direct 0x0202)\n- */\n-struct iavf_aqc_add_remove_statistics {\n-\t__le16\tseid;\n-\t__le16\tvlan;\n-\t__le16\tstat_index;\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);\n-\n-/* Set Port Parameters command (direct 0x0203) */\n-struct iavf_aqc_set_port_parameters {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS\t1\n-#define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS\t2 /* must set! */\n-#define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA\t4\n-\t__le16\tbad_frame_vsi;\n-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT\t0x0\n-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK\t0x3FF\n-\t__le16\tdefault_seid;        /* reserved for command */\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);\n-\n-/* Get Switch Resource Allocation (indirect 0x0204) */\n-struct iavf_aqc_get_switch_resource_alloc {\n-\tu8\tnum_entries;         /* reserved for command */\n-\tu8\treserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);\n-\n-/* expect an array of these structs in the response buffer */\n-struct iavf_aqc_switch_resource_alloc_element_resp {\n-\tu8\tresource_type;\n-#define IAVF_AQ_RESOURCE_TYPE_VEB\t\t0x0\n-#define IAVF_AQ_RESOURCE_TYPE_VSI\t\t0x1\n-#define IAVF_AQ_RESOURCE_TYPE_MACADDR\t\t0x2\n-#define IAVF_AQ_RESOURCE_TYPE_STAG\t\t0x3\n-#define IAVF_AQ_RESOURCE_TYPE_ETAG\t\t0x4\n-#define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH\t0x5\n-#define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH\t0x6\n-#define IAVF_AQ_RESOURCE_TYPE_VLAN\t\t0x7\n-#define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY\t0x8\n-#define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY\t0x9\n-#define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL\t0xA\n-#define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE\t0xB\n-#define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS\t0xC\n-#define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS\t0xD\n-#define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS\t0xF\n-#define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS\t0x10\n-#define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS\t0x11\n-#define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS\t\t0x12\n-#define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS\t0x13\n-\tu8\treserved1;\n-\t__le16\tguaranteed;\n-\t__le16\ttotal;\n-\t__le16\tused;\n-\t__le16\ttotal_unalloced;\n-\tu8\treserved2[6];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);\n-\n-/* Set Switch Configuration (direct 0x0205) */\n-struct iavf_aqc_set_switch_config {\n-\t__le16\tflags;\n-/* flags used for both fields below */\n-#define IAVF_AQ_SET_SWITCH_CFG_PROMISC\t\t0x0001\n-#define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER\t0x0002\n-#define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT\t0x0004\n-\t__le16\tvalid_flags;\n-\t/* The ethertype in switch_tag is dropped on ingress and used\n-\t * internally by the switch. Set this to zero for the default\n-\t * of 0x88a8 (802.1ad). Should be zero for firmware API\n-\t * versions lower than 1.7.\n-\t */\n-\t__le16\tswitch_tag;\n-\t/* The ethertypes in first_tag and second_tag are used to\n-\t * match the outer and inner VLAN tags (respectively) when HW\n-\t * double VLAN tagging is enabled via the set port parameters\n-\t * AQ command. Otherwise these are both ignored. Set them to\n-\t * zero for their defaults of 0x8100 (802.1Q). Should be zero\n-\t * for firmware API versions lower than 1.7.\n-\t */\n-\t__le16\tfirst_tag;\n-\t__le16\tsecond_tag;\n-\tu8\treserved[6];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);\n-\n-/* Read Receive control registers  (direct 0x0206)\n- * Write Receive control registers (direct 0x0207)\n- *     used for accessing Rx control registers that can be\n- *     slow and need special handling when under high Rx load\n- */\n-struct iavf_aqc_rx_ctl_reg_read_write {\n-\t__le32 reserved1;\n-\t__le32 address;\n-\t__le32 reserved2;\n-\t__le32 value;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);\n-\n-/* Add VSI (indirect 0x0210)\n- *    this indirect command uses struct iavf_aqc_vsi_properties_data\n- *    as the indirect buffer (128 bytes)\n- *\n- * Update VSI (indirect 0x211)\n- *     uses the same data structure as Add VSI\n- *\n- * Get VSI (indirect 0x0212)\n- *     uses the same completion and data structure as Add VSI\n- */\n-struct iavf_aqc_add_get_update_vsi {\n-\t__le16\tuplink_seid;\n-\tu8\tconnection_type;\n-#define IAVF_AQ_VSI_CONN_TYPE_NORMAL\t0x1\n-#define IAVF_AQ_VSI_CONN_TYPE_DEFAULT\t0x2\n-#define IAVF_AQ_VSI_CONN_TYPE_CASCADED\t0x3\n-\tu8\treserved1;\n-\tu8\tvf_id;\n-\tu8\treserved2;\n-\t__le16\tvsi_flags;\n-#define IAVF_AQ_VSI_TYPE_SHIFT\t\t0x0\n-#define IAVF_AQ_VSI_TYPE_MASK\t\t(0x3 << IAVF_AQ_VSI_TYPE_SHIFT)\n-#define IAVF_AQ_VSI_TYPE_VF\t\t0x0\n-#define IAVF_AQ_VSI_TYPE_VMDQ2\t\t0x1\n-#define IAVF_AQ_VSI_TYPE_PF\t\t0x2\n-#define IAVF_AQ_VSI_TYPE_EMP_MNG\t0x3\n-#define IAVF_AQ_VSI_FLAG_CASCADED_PV\t0x4\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);\n-\n-struct iavf_aqc_add_get_update_vsi_completion {\n-\t__le16 seid;\n-\t__le16 vsi_number;\n-\t__le16 vsi_used;\n-\t__le16 vsi_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);\n \n struct iavf_aqc_vsi_properties_data {\n \t/* first 96 byte are written by SW */\n@@ -966,87 +454,6 @@ struct iavf_aqc_vsi_properties_data {\n \n IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);\n \n-/* Add Port Virtualizer (direct 0x0220)\n- * also used for update PV (direct 0x0221) but only flags are used\n- * (IS_CTRL_PORT only works on add PV)\n- */\n-struct iavf_aqc_add_update_pv {\n-\t__le16\tcommand_flags;\n-#define IAVF_AQC_PV_FLAG_PV_TYPE\t\t0x1\n-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN\t0x2\n-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN\t0x4\n-#define IAVF_AQC_PV_FLAG_IS_CTRL_PORT\t\t0x8\n-\t__le16\tuplink_seid;\n-\t__le16\tconnected_seid;\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);\n-\n-struct iavf_aqc_add_update_pv_completion {\n-\t/* reserved for update; for add also encodes error if rc == ENOSPC */\n-\t__le16\tpv_seid;\n-#define IAVF_AQC_PV_ERR_FLAG_NO_PV\t0x1\n-#define IAVF_AQC_PV_ERR_FLAG_NO_SCHED\t0x2\n-#define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER\t0x4\n-#define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY\t0x8\n-\tu8\treserved[14];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);\n-\n-/* Get PV Params (direct 0x0222)\n- * uses iavf_aqc_switch_seid for the descriptor\n- */\n-\n-struct iavf_aqc_get_pv_params_completion {\n-\t__le16\tseid;\n-\t__le16\tdefault_stag;\n-\t__le16\tpv_flags; /* same flags as add_pv */\n-#define IAVF_AQC_GET_PV_PV_TYPE\t\t\t0x1\n-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG\t0x2\n-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG\t0x4\n-\tu8\treserved[8];\n-\t__le16\tdefault_port_seid;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);\n-\n-/* Add VEB (direct 0x0230) */\n-struct iavf_aqc_add_veb {\n-\t__le16\tuplink_seid;\n-\t__le16\tdownlink_seid;\n-\t__le16\tveb_flags;\n-#define IAVF_AQC_ADD_VEB_FLOATING\t\t0x1\n-#define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT\t1\n-#define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK\t\t(0x3 << \\\n-\t\t\t\t\tIAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)\n-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT\t0x2\n-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA\t\t0x4\n-#define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER\t0x8     /* deprecated */\n-#define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS\t0x10\n-\tu8\tenable_tcs;\n-\tu8\treserved[9];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);\n-\n-struct iavf_aqc_add_veb_completion {\n-\tu8\treserved[6];\n-\t__le16\tswitch_seid;\n-\t/* also encodes error if rc == ENOSPC; codes are the same as add_pv */\n-\t__le16\tveb_seid;\n-#define IAVF_AQC_VEB_ERR_FLAG_NO_VEB\t\t0x1\n-#define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED\t\t0x2\n-#define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER\t0x4\n-#define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY\t\t0x8\n-\t__le16\tstatistic_index;\n-\t__le16\tvebs_used;\n-\t__le16\tvebs_free;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);\n-\n /* Get VEB Parameters (direct 0x0232)\n  * uses iavf_aqc_switch_seid for the descriptor\n  */\n@@ -1062,1486 +469,116 @@ struct iavf_aqc_get_veb_parameters_completion {\n \n IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);\n \n-/* Delete Element (direct 0x0243)\n- * uses the generic iavf_aqc_switch_seid\n- */\n-\n-/* Add MAC-VLAN (indirect 0x0250) */\n-\n-/* used for the command for most vlan commands */\n-struct iavf_aqc_macvlan {\n-\t__le16\tnum_addresses;\n-\t__le16\tseid[3];\n-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tIAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n-#define IAVF_AQC_MACVLAN_CMD_SEID_VALID\t\t0x8000\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);\n-\n-/* indirect data for command and response */\n-struct iavf_aqc_add_macvlan_element_data {\n-\tu8\tmac_addr[6];\n-\t__le16\tvlan_tag;\n-\t__le16\tflags;\n-#define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH\t0x0001\n-#define IAVF_AQC_MACVLAN_ADD_HASH_MATCH\t\t0x0002\n-#define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN\t0x0004\n-#define IAVF_AQC_MACVLAN_ADD_TO_QUEUE\t\t0x0008\n-#define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC\t0x0010\n-\t__le16\tqueue_number;\n-#define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT\t0\n-#define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK\t\t(0x7FF << \\\n-\t\t\t\t\tIAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n-\t/* response section */\n-\tu8\tmatch_method;\n-#define IAVF_AQC_MM_PERFECT_MATCH\t0x01\n-#define IAVF_AQC_MM_HASH_MATCH\t\t0x02\n-#define IAVF_AQC_MM_ERR_NO_RES\t\t0xFF\n-\tu8\treserved1[3];\n-};\n+#define IAVF_LINK_SPEED_100MB_SHIFT\t0x1\n+#define IAVF_LINK_SPEED_1000MB_SHIFT\t0x2\n+#define IAVF_LINK_SPEED_10GB_SHIFT\t0x3\n+#define IAVF_LINK_SPEED_40GB_SHIFT\t0x4\n+#define IAVF_LINK_SPEED_20GB_SHIFT\t0x5\n+#define IAVF_LINK_SPEED_25GB_SHIFT\t0x6\n \n-struct iavf_aqc_add_remove_macvlan_completion {\n-\t__le16 perfect_mac_used;\n-\t__le16 perfect_mac_free;\n-\t__le16 unicast_hash_free;\n-\t__le16 multicast_hash_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n+enum iavf_aq_link_speed {\n+\tIAVF_LINK_SPEED_UNKNOWN\t= 0,\n+\tIAVF_LINK_SPEED_100MB\t= (1 << IAVF_LINK_SPEED_100MB_SHIFT),\n+\tIAVF_LINK_SPEED_1GB\t= (1 << IAVF_LINK_SPEED_1000MB_SHIFT),\n+\tIAVF_LINK_SPEED_10GB\t= (1 << IAVF_LINK_SPEED_10GB_SHIFT),\n+\tIAVF_LINK_SPEED_40GB\t= (1 << IAVF_LINK_SPEED_40GB_SHIFT),\n+\tIAVF_LINK_SPEED_20GB\t= (1 << IAVF_LINK_SPEED_20GB_SHIFT),\n+\tIAVF_LINK_SPEED_25GB\t= (1 << IAVF_LINK_SPEED_25GB_SHIFT),\n };\n \n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);\n-\n-/* Remove MAC-VLAN (indirect 0x0251)\n- * uses iavf_aqc_macvlan for the descriptor\n- * data points to an array of num_addresses of elements\n- */\n-\n-struct iavf_aqc_remove_macvlan_element_data {\n-\tu8\tmac_addr[6];\n-\t__le16\tvlan_tag;\n-\tu8\tflags;\n-#define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH\t0x01\n-#define IAVF_AQC_MACVLAN_DEL_HASH_MATCH\t\t0x02\n-#define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN\t0x08\n-#define IAVF_AQC_MACVLAN_DEL_ALL_VSIS\t\t0x10\n-\tu8\treserved[3];\n-\t/* reply section */\n-\tu8\terror_code;\n-#define IAVF_AQC_REMOVE_MACVLAN_SUCCESS\t\t0x0\n-#define IAVF_AQC_REMOVE_MACVLAN_FAIL\t\t0xFF\n-\tu8\treply_reserved[3];\n-};\n+#define IAVF_AQ_LINK_UP_FUNCTION\t0x01\n \n-/* Add VLAN (indirect 0x0252)\n- * Remove VLAN (indirect 0x0253)\n- * use the generic iavf_aqc_macvlan for the command\n+/* Send to PF command (indirect 0x0801) id is only used by PF\n+ * Send to VF command (indirect 0x0802) id is only used by PF\n+ * Send to Peer PF command (indirect 0x0803)\n  */\n-struct iavf_aqc_add_remove_vlan_element_data {\n-\t__le16\tvlan_tag;\n-\tu8\tvlan_flags;\n-/* flags for add VLAN */\n-#define IAVF_AQC_ADD_VLAN_LOCAL\t\t\t0x1\n-#define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT\t\t1\n-#define IAVF_AQC_ADD_PVLAN_TYPE_MASK\t(0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)\n-#define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR\t\t0x0\n-#define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY\t\t0x2\n-#define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY\t0x4\n-#define IAVF_AQC_VLAN_PTYPE_SHIFT\t\t3\n-#define IAVF_AQC_VLAN_PTYPE_MASK\t(0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)\n-#define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI\t\t0x0\n-#define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI\t\t0x8\n-#define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI\t0x10\n-#define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI\t0x18\n-/* flags for remove VLAN */\n-#define IAVF_AQC_REMOVE_VLAN_ALL\t0x1\n-\tu8\treserved;\n-\tu8\tresult;\n-/* flags for add VLAN */\n-#define IAVF_AQC_ADD_VLAN_SUCCESS\t0x0\n-#define IAVF_AQC_ADD_VLAN_FAIL_REQUEST\t0xFE\n-#define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE\t0xFF\n-/* flags for remove VLAN */\n-#define IAVF_AQC_REMOVE_VLAN_SUCCESS\t0x0\n-#define IAVF_AQC_REMOVE_VLAN_FAIL\t0xFF\n-\tu8\treserved1[3];\n-};\n-\n-struct iavf_aqc_add_remove_vlan_completion {\n+struct iavf_aqc_pf_vf_message {\n+\t__le32\tid;\n \tu8\treserved[4];\n-\t__le16\tvlans_used;\n-\t__le16\tvlans_free;\n \t__le32\taddr_high;\n \t__le32\taddr_low;\n };\n \n-/* Set VSI Promiscuous Modes (direct 0x0254) */\n-struct iavf_aqc_set_vsi_promiscuous_modes {\n-\t__le16\tpromiscuous_flags;\n-\t__le16\tvalid_flags;\n-/* flags used for both fields above */\n-#define IAVF_AQC_SET_VSI_PROMISC_UNICAST\t0x01\n-#define IAVF_AQC_SET_VSI_PROMISC_MULTICAST\t0x02\n-#define IAVF_AQC_SET_VSI_PROMISC_BROADCAST\t0x04\n-#define IAVF_AQC_SET_VSI_DEFAULT\t\t0x08\n-#define IAVF_AQC_SET_VSI_PROMISC_VLAN\t\t0x10\n-#define IAVF_AQC_SET_VSI_PROMISC_TX\t\t0x8000\n-\t__le16\tseid;\n-#define IAVF_AQC_VSI_PROM_CMD_SEID_MASK\t\t0x3FF\n-\t__le16\tvlan_tag;\n-#define IAVF_AQC_SET_VSI_VLAN_MASK\t\t0x0FFF\n-#define IAVF_AQC_SET_VSI_VLAN_VALID\t\t0x8000\n-\tu8\treserved[8];\n-};\n+IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);\n+\n+/* Get CEE DCBX Oper Config (0x0A07)\n+ * uses the generic descriptor struct\n+ * returns below as indirect response\n+ */\n+\n+#define IAVF_AQC_CEE_APP_FCOE_SHIFT\t0x0\n+#define IAVF_AQC_CEE_APP_FCOE_MASK\t(0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)\n+#define IAVF_AQC_CEE_APP_ISCSI_SHIFT\t0x3\n+#define IAVF_AQC_CEE_APP_ISCSI_MASK\t(0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)\n+#define IAVF_AQC_CEE_APP_FIP_SHIFT\t0x8\n+#define IAVF_AQC_CEE_APP_FIP_MASK\t(0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)\n \n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);\n+#define IAVF_AQC_CEE_PG_STATUS_SHIFT\t0x0\n+#define IAVF_AQC_CEE_PG_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)\n+#define IAVF_AQC_CEE_PFC_STATUS_SHIFT\t0x3\n+#define IAVF_AQC_CEE_PFC_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)\n+#define IAVF_AQC_CEE_APP_STATUS_SHIFT\t0x8\n+#define IAVF_AQC_CEE_APP_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)\n+#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT\t0x8\n+#define IAVF_AQC_CEE_FCOE_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)\n+#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT\t0xB\n+#define IAVF_AQC_CEE_ISCSI_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)\n+#define IAVF_AQC_CEE_FIP_STATUS_SHIFT\t0x10\n+#define IAVF_AQC_CEE_FIP_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)\n \n-/* Add S/E-tag command (direct 0x0255)\n- * Uses generic iavf_aqc_add_remove_tag_completion for completion\n+/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with\n+ * word boundary layout issues, which the Linux compilers silently deal\n+ * with by adding padding, making the actual struct larger than designed.\n+ * However, the FW compiler for the NIC is less lenient and complains\n+ * about the struct.  Hence, the struct defined here has an extra byte in\n+ * fields reserved3 and reserved4 to directly acknowledge that padding,\n+ * and the new length is used in the length check macro.\n  */\n-struct iavf_aqc_add_tag {\n-\t__le16\tflags;\n-#define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE\t\t0x0001\n-\t__le16\tseid;\n-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tIAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\ttag;\n-\t__le16\tqueue_number;\n-\tu8\treserved[8];\n+struct iavf_aqc_get_cee_dcb_cfg_v1_resp {\n+\tu8\treserved1;\n+\tu8\toper_num_tc;\n+\tu8\toper_prio_tc[4];\n+\tu8\treserved2;\n+\tu8\toper_tc_bw[8];\n+\tu8\toper_pfc_en;\n+\tu8\treserved3[2];\n+\t__le16\toper_app_prio;\n+\tu8\treserved4[2];\n+\t__le16\ttlv_status;\n };\n \n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);\n+IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);\n \n-struct iavf_aqc_add_remove_tag_completion {\n+struct iavf_aqc_get_cee_dcb_cfg_resp {\n+\tu8\toper_num_tc;\n+\tu8\toper_prio_tc[4];\n+\tu8\toper_tc_bw[8];\n+\tu8\toper_pfc_en;\n+\t__le16\toper_app_prio;\n+\t__le32\ttlv_status;\n \tu8\treserved[12];\n-\t__le16\ttags_used;\n-\t__le16\ttags_free;\n };\n \n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);\n+IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);\n \n-/* Remove S/E-tag command (direct 0x0256)\n- * Uses generic iavf_aqc_add_remove_tag_completion for completion\n+/*\tSet Local LLDP MIB (indirect 0x0A08)\n+ *\tUsed to replace the local MIB of a given LLDP agent. e.g. DCBx\n  */\n-struct iavf_aqc_remove_tag {\n-\t__le16\tseid;\n-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tIAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\ttag;\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);\n-\n-/* Add multicast E-Tag (direct 0x0257)\n- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields\n- * and no external data\n- */\n-struct iavf_aqc_add_remove_mcast_etag {\n-\t__le16\tpv_seid;\n-\t__le16\tetag;\n-\tu8\tnum_unicast_etags;\n-\tu8\treserved[3];\n-\t__le32\taddr_high;          /* address of array of 2-byte s-tags */\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);\n-\n-struct iavf_aqc_add_remove_mcast_etag_completion {\n-\tu8\treserved[4];\n-\t__le16\tmcast_etags_used;\n-\t__le16\tmcast_etags_free;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);\n-\n-/* Update S/E-Tag (direct 0x0259) */\n-struct iavf_aqc_update_tag {\n-\t__le16\tseid;\n-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tIAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)\n-\t__le16\told_tag;\n-\t__le16\tnew_tag;\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);\n-\n-struct iavf_aqc_update_tag_completion {\n-\tu8\treserved[12];\n-\t__le16\ttags_used;\n-\t__le16\ttags_free;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);\n-\n-/* Add Control Packet filter (direct 0x025A)\n- * Remove Control Packet filter (direct 0x025B)\n- * uses the iavf_aqc_add_oveb_cloud,\n- * and the generic direct completion structure\n- */\n-struct iavf_aqc_add_remove_control_packet_filter {\n-\tu8\tmac[6];\n-\t__le16\tetype;\n-\t__le16\tflags;\n-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC\t0x0001\n-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP\t\t0x0002\n-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE\t0x0004\n-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX\t\t0x0008\n-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX\t\t0x0000\n-\t__le16\tseid;\n-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\tIAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)\n-\t__le16\tqueue;\n-\tu8\treserved[2];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);\n-\n-struct iavf_aqc_add_remove_control_packet_filter_completion {\n-\t__le16\tmac_etype_used;\n-\t__le16\tetype_used;\n-\t__le16\tmac_etype_free;\n-\t__le16\tetype_free;\n-\tu8\treserved[8];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);\n-\n-/* Add Cloud filters (indirect 0x025C)\n- * Remove Cloud filters (indirect 0x025D)\n- * uses the iavf_aqc_add_remove_cloud_filters,\n- * and the generic indirect completion structure\n- */\n-struct iavf_aqc_add_remove_cloud_filters {\n-\tu8\tnum_filters;\n-\tu8\treserved;\n-\t__le16\tseid;\n-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT\t0\n-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK\t(0x3FF << \\\n-\t\t\t\t\tIAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)\n-\tu8\tbig_buffer_flag;\n-#define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER\t1\n-\tu8\treserved2[3];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);\n-\n-struct iavf_aqc_add_remove_cloud_filters_element_data {\n-\tu8\touter_mac[6];\n-\tu8\tinner_mac[6];\n-\t__le16\tinner_vlan;\n-\tunion {\n-\t\tstruct {\n-\t\t\tu8 reserved[12];\n-\t\t\tu8 data[4];\n-\t\t} v4;\n-\t\tstruct {\n-\t\t\tu8 data[16];\n-\t\t} v6;\n-\t} ipaddr;\n-\t__le16\tflags;\n-#define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT\t\t\t0\n-#define IAVF_AQC_ADD_CLOUD_FILTER_MASK\t(0x3F << \\\n-\t\t\t\t\tIAVF_AQC_ADD_CLOUD_FILTER_SHIFT)\n-/* 0x0000 reserved */\n-#define IAVF_AQC_ADD_CLOUD_FILTER_OIP\t\t\t0x0001\n-/* 0x0002 reserved */\n-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN\t\t0x0003\n-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID\t0x0004\n-/* 0x0005 reserved */\n-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID\t\t0x0006\n-/* 0x0007 reserved */\n-/* 0x0008 reserved */\n-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC\t\t\t0x0009\n-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC\t\t\t0x000A\n-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC\t0x000B\n-#define IAVF_AQC_ADD_CLOUD_FILTER_IIP\t\t\t0x000C\n-/* 0x0010 to 0x0017 is for custom filters */\n-\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE\t\t0x0080\n-#define IAVF_AQC_ADD_CLOUD_VNK_SHIFT\t\t\t6\n-#define IAVF_AQC_ADD_CLOUD_VNK_MASK\t\t\t0x00C0\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4\t\t\t0\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6\t\t\t0x0100\n-\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT\t\t9\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK\t\t0x1E00\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN\t\t0\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC\t\t1\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE\t\t2\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP\t\t\t3\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED\t\t4\n-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE\t\t5\n-\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC\t0x2000\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC\t0x4000\n-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP\t0x8000\n-\n-\t__le32\ttenant_id;\n-\tu8\treserved[4];\n-\t__le16\tqueue_number;\n-#define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT\t\t0\n-#define IAVF_AQC_ADD_CLOUD_QUEUE_MASK\t\t(0x7FF << \\\n-\t\t\t\t\t\t IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)\n-\tu8\treserved2[14];\n-\t/* response section */\n-\tu8\tallocation_result;\n-#define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS\t0x0\n-#define IAVF_AQC_ADD_CLOUD_FILTER_FAIL\t\t0xFF\n-\tu8\tresponse_reserved[7];\n-};\n-\n-/* iavf_aqc_add_rm_cloud_filt_elem_ext is used when\n- * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.\n- */\n-struct iavf_aqc_add_rm_cloud_filt_elem_ext {\n-\tstruct iavf_aqc_add_remove_cloud_filters_element_data element;\n-\tu16     general_fields[32];\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0\t0\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1\t1\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2\t2\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0\t3\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1\t4\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2\t5\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0\t6\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1\t7\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2\t8\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0\t9\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1\t10\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2\t11\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0\t12\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1\t13\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2\t14\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0\t15\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1\t16\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2\t17\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3\t18\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4\t19\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5\t20\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6\t21\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7\t22\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0\t23\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1\t24\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2\t25\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3\t26\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4\t27\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5\t28\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6\t29\n-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7\t30\n-};\n-\n-struct iavf_aqc_remove_cloud_filters_completion {\n-\t__le16 perfect_ovlan_used;\n-\t__le16 perfect_ovlan_free;\n-\t__le16 vlan_used;\n-\t__le16 vlan_free;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);\n-\n-/* Replace filter Command 0x025F\n- * uses the iavf_aqc_replace_cloud_filters,\n- * and the generic indirect completion structure\n- */\n-struct iavf_filter_data {\n-\tu8 filter_type;\n-\tu8 input[3];\n-};\n-\n-struct iavf_aqc_replace_cloud_filters_cmd {\n-\tu8\tvalid_flags;\n-#define IAVF_AQC_REPLACE_L1_FILTER\t\t0x0\n-#define IAVF_AQC_REPLACE_CLOUD_FILTER\t\t0x1\n-#define IAVF_AQC_GET_CLOUD_FILTERS\t\t0x2\n-#define IAVF_AQC_MIRROR_CLOUD_FILTER\t\t0x4\n-#define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER\t0x8\n-\tu8\told_filter_type;\n-\tu8\tnew_filter_type;\n-\tu8\ttr_bit;\n-\tu8\treserved[4];\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-struct iavf_aqc_replace_cloud_filters_cmd_buf {\n-\tu8\tdata[32];\n-/* Filter type INPUT codes*/\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX\t3\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED\t(1 << 7UL)\n-\n-/* Field Vector offsets */\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA\t\t0\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH\t\t6\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG\t\t7\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN\t\t8\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN\t\t9\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN\t\t10\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY\t\t11\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC\t\t12\n-/* big FLU */\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA\t\t14\n-/* big FLU */\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA\t\t15\n-\n-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN\t\t37\n-\tstruct iavf_filter_data\tfilters[8];\n-};\n-\n-/* Add Mirror Rule (indirect or direct 0x0260)\n- * Delete Mirror Rule (indirect or direct 0x0261)\n- * note: some rule types (4,5) do not use an external buffer.\n- *       take care to set the flags correctly.\n- */\n-struct iavf_aqc_add_delete_mirror_rule {\n-\t__le16 seid;\n-\t__le16 rule_type;\n-#define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT\t\t0\n-#define IAVF_AQC_MIRROR_RULE_TYPE_MASK\t\t(0x7 << \\\n-\t\t\t\t\t\tIAVF_AQC_MIRROR_RULE_TYPE_SHIFT)\n-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS\t1\n-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS\t2\n-#define IAVF_AQC_MIRROR_RULE_TYPE_VLAN\t\t3\n-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS\t4\n-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS\t5\n-\t__le16 num_entries;\n-\t__le16 destination;  /* VSI for add, rule id for delete */\n-\t__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */\n-\t__le32 addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);\n-\n-struct iavf_aqc_add_delete_mirror_rule_completion {\n-\tu8\treserved[2];\n-\t__le16\trule_id;  /* only used on add */\n-\t__le16\tmirror_rules_used;\n-\t__le16\tmirror_rules_free;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);\n-\n-/* Dynamic Device Personalization */\n-struct iavf_aqc_write_personalization_profile {\n-\tu8      flags;\n-\tu8      reserved[3];\n-\t__le32  profile_track_id;\n-\t__le32  addr_high;\n-\t__le32  addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);\n-\n-struct iavf_aqc_write_ddp_resp {\n-\t__le32 error_offset;\n-\t__le32 error_info;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-struct iavf_aqc_get_applied_profiles {\n-\tu8      flags;\n-#define IAVF_AQC_GET_DDP_GET_CONF\t0x1\n-#define IAVF_AQC_GET_DDP_GET_RDPU_CONF\t0x2\n-\tu8      rsv[3];\n-\t__le32  reserved;\n-\t__le32  addr_high;\n-\t__le32  addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);\n-\n-/* DCB 0x03xx*/\n-\n-/* PFC Ignore (direct 0x0301)\n- *    the command and response use the same descriptor structure\n- */\n-struct iavf_aqc_pfc_ignore {\n-\tu8\ttc_bitmap;\n-\tu8\tcommand_flags; /* unused on response */\n-#define IAVF_AQC_PFC_IGNORE_SET\t\t0x80\n-#define IAVF_AQC_PFC_IGNORE_CLEAR\t0x0\n-\tu8\treserved[14];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);\n-\n-/* DCB Update (direct 0x0302) uses the iavf_aq_desc structure\n- * with no parameters\n- */\n-\n-/* TX scheduler 0x04xx */\n-\n-/* Almost all the indirect commands use\n- * this generic struct to pass the SEID in param0\n- */\n-struct iavf_aqc_tx_sched_ind {\n-\t__le16\tvsi_seid;\n-\tu8\treserved[6];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);\n-\n-/* Several commands respond with a set of queue set handles */\n-struct iavf_aqc_qs_handles_resp {\n-\t__le16 qs_handles[8];\n-};\n-\n-/* Configure VSI BW limits (direct 0x0400) */\n-struct iavf_aqc_configure_vsi_bw_limit {\n-\t__le16\tvsi_seid;\n-\tu8\treserved[2];\n-\t__le16\tcredit;\n-\tu8\treserved1[2];\n-\tu8\tmax_credit; /* 0-3, limit = 2^max */\n-\tu8\treserved2[7];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);\n-\n-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)\n- *    responds with iavf_aqc_qs_handles_resp\n- */\n-struct iavf_aqc_configure_vsi_ets_sla_bw_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[15];\n-\t__le16\ttc_bw_credits[8]; /* FW writesback QS handles here */\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved1[28];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);\n-\n-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)\n- *    responds with iavf_aqc_qs_handles_resp\n- */\n-struct iavf_aqc_configure_vsi_tc_bw_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[3];\n-\tu8\ttc_bw_credits[8];\n-\tu8\treserved1[4];\n-\t__le16\tqs_handles[8];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);\n-\n-/* Query vsi bw configuration (indirect 0x0408) */\n-struct iavf_aqc_query_vsi_bw_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\ttc_suspended_bits;\n-\tu8\treserved[14];\n-\t__le16\tqs_handles[8];\n-\tu8\treserved1[4];\n-\t__le16\tport_bw_limit;\n-\tu8\treserved2[2];\n-\tu8\tmax_bw; /* 0-3, limit = 2^max */\n-\tu8\treserved3[23];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);\n-\n-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */\n-struct iavf_aqc_query_vsi_ets_sla_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[3];\n-\tu8\tshare_credits[8];\n-\t__le16\tcredits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);\n-\n-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */\n-struct iavf_aqc_configure_switching_comp_bw_limit {\n-\t__le16\tseid;\n-\tu8\treserved[2];\n-\t__le16\tcredit;\n-\tu8\treserved1[2];\n-\tu8\tmax_bw; /* 0-3, limit = 2^max */\n-\tu8\treserved2[7];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);\n-\n-/* Enable  Physical Port ETS (indirect 0x0413)\n- * Modify  Physical Port ETS (indirect 0x0414)\n- * Disable Physical Port ETS (indirect 0x0415)\n- */\n-struct iavf_aqc_configure_switching_comp_ets_data {\n-\tu8\treserved[4];\n-\tu8\ttc_valid_bits;\n-\tu8\tseepage;\n-#define IAVF_AQ_ETS_SEEPAGE_EN_MASK\t0x1\n-\tu8\ttc_strict_priority_flags;\n-\tu8\treserved1[17];\n-\tu8\ttc_bw_share_credits[8];\n-\tu8\treserved2[96];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);\n-\n-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */\n-struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[15];\n-\t__le16\ttc_bw_credit[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved1[28];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x40,\n-\t\t      iavf_aqc_configure_switching_comp_ets_bw_limit_data);\n-\n-/* Configure Switching Component Bandwidth Allocation per Tc\n- * (indirect 0x0417)\n- */\n-struct iavf_aqc_configure_switching_comp_bw_config_data {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[2];\n-\tu8\tabsolute_credits; /* bool */\n-\tu8\ttc_bw_share_credits[8];\n-\tu8\treserved1[20];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);\n-\n-/* Query Switching Component Configuration (indirect 0x0418) */\n-struct iavf_aqc_query_switching_comp_ets_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[35];\n-\t__le16\tport_bw_limit;\n-\tu8\treserved1[2];\n-\tu8\ttc_bw_max; /* 0-3, limit = 2^max */\n-\tu8\treserved2[23];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);\n-\n-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */\n-struct iavf_aqc_query_port_ets_config_resp {\n-\tu8\treserved[4];\n-\tu8\ttc_valid_bits;\n-\tu8\treserved1;\n-\tu8\ttc_strict_priority_bits;\n-\tu8\treserved2;\n-\tu8\ttc_bw_share_credits[8];\n-\t__le16\ttc_bw_limits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-\tu8\treserved3[32];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);\n-\n-/* Query Switching Component Bandwidth Allocation per Traffic Type\n- * (indirect 0x041A)\n- */\n-struct iavf_aqc_query_switching_comp_bw_config_resp {\n-\tu8\ttc_valid_bits;\n-\tu8\treserved[2];\n-\tu8\tabsolute_credits_enable; /* bool */\n-\tu8\ttc_bw_share_credits[8];\n-\t__le16\ttc_bw_limits[8];\n-\n-\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n-\t__le16\ttc_bw_max[2];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);\n-\n-/* Suspend/resume port TX traffic\n- * (direct 0x041B and 0x041C) uses the generic SEID struct\n- */\n-\n-/* Configure partition BW\n- * (indirect 0x041D)\n- */\n-struct iavf_aqc_configure_partition_bw_data {\n-\t__le16\tpf_valid_bits;\n-\tu8\tmin_bw[16];      /* guaranteed bandwidth */\n-\tu8\tmax_bw[16];      /* bandwidth limit */\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);\n-\n-/* Get and set the active HMC resource profile and status.\n- * (direct 0x0500) and (direct 0x0501)\n- */\n-struct iavf_aq_get_set_hmc_resource_profile {\n-\tu8\tpm_profile;\n-\tu8\tpe_vf_enabled;\n-\tu8\treserved[14];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);\n-\n-enum iavf_aq_hmc_profile {\n-\t/* IAVF_HMC_PROFILE_NO_CHANGE\t= 0, reserved */\n-\tIAVF_HMC_PROFILE_DEFAULT\t= 1,\n-\tIAVF_HMC_PROFILE_FAVOR_VF\t= 2,\n-\tIAVF_HMC_PROFILE_EQUAL\t\t= 3,\n-};\n-\n-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */\n-\n-/* set in param0 for get phy abilities to report qualified modules */\n-#define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES\t0x0001\n-#define IAVF_AQ_PHY_REPORT_INITIAL_VALUES\t0x0002\n-\n-enum iavf_aq_phy_type {\n-\tIAVF_PHY_TYPE_SGMII\t\t\t= 0x0,\n-\tIAVF_PHY_TYPE_1000BASE_KX\t\t= 0x1,\n-\tIAVF_PHY_TYPE_10GBASE_KX4\t\t= 0x2,\n-\tIAVF_PHY_TYPE_10GBASE_KR\t\t= 0x3,\n-\tIAVF_PHY_TYPE_40GBASE_KR4\t\t= 0x4,\n-\tIAVF_PHY_TYPE_XAUI\t\t\t= 0x5,\n-\tIAVF_PHY_TYPE_XFI\t\t\t= 0x6,\n-\tIAVF_PHY_TYPE_SFI\t\t\t= 0x7,\n-\tIAVF_PHY_TYPE_XLAUI\t\t\t= 0x8,\n-\tIAVF_PHY_TYPE_XLPPI\t\t\t= 0x9,\n-\tIAVF_PHY_TYPE_40GBASE_CR4_CU\t\t= 0xA,\n-\tIAVF_PHY_TYPE_10GBASE_CR1_CU\t\t= 0xB,\n-\tIAVF_PHY_TYPE_10GBASE_AOC\t\t= 0xC,\n-\tIAVF_PHY_TYPE_40GBASE_AOC\t\t= 0xD,\n-\tIAVF_PHY_TYPE_UNRECOGNIZED\t\t= 0xE,\n-\tIAVF_PHY_TYPE_UNSUPPORTED\t\t= 0xF,\n-\tIAVF_PHY_TYPE_100BASE_TX\t\t= 0x11,\n-\tIAVF_PHY_TYPE_1000BASE_T\t\t= 0x12,\n-\tIAVF_PHY_TYPE_10GBASE_T\t\t\t= 0x13,\n-\tIAVF_PHY_TYPE_10GBASE_SR\t\t= 0x14,\n-\tIAVF_PHY_TYPE_10GBASE_LR\t\t= 0x15,\n-\tIAVF_PHY_TYPE_10GBASE_SFPP_CU\t\t= 0x16,\n-\tIAVF_PHY_TYPE_10GBASE_CR1\t\t= 0x17,\n-\tIAVF_PHY_TYPE_40GBASE_CR4\t\t= 0x18,\n-\tIAVF_PHY_TYPE_40GBASE_SR4\t\t= 0x19,\n-\tIAVF_PHY_TYPE_40GBASE_LR4\t\t= 0x1A,\n-\tIAVF_PHY_TYPE_1000BASE_SX\t\t= 0x1B,\n-\tIAVF_PHY_TYPE_1000BASE_LX\t\t= 0x1C,\n-\tIAVF_PHY_TYPE_1000BASE_T_OPTICAL\t= 0x1D,\n-\tIAVF_PHY_TYPE_20GBASE_KR2\t\t= 0x1E,\n-\tIAVF_PHY_TYPE_25GBASE_KR\t\t= 0x1F,\n-\tIAVF_PHY_TYPE_25GBASE_CR\t\t= 0x20,\n-\tIAVF_PHY_TYPE_25GBASE_SR\t\t= 0x21,\n-\tIAVF_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n-\tIAVF_PHY_TYPE_25GBASE_AOC\t\t= 0x23,\n-\tIAVF_PHY_TYPE_25GBASE_ACC\t\t= 0x24,\n-\tIAVF_PHY_TYPE_MAX,\n-\tIAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP\t= 0xFD,\n-\tIAVF_PHY_TYPE_EMPTY\t\t\t= 0xFE,\n-\tIAVF_PHY_TYPE_DEFAULT\t\t\t= 0xFF,\n-};\n-\n-#define IAVF_LINK_SPEED_100MB_SHIFT\t0x1\n-#define IAVF_LINK_SPEED_1000MB_SHIFT\t0x2\n-#define IAVF_LINK_SPEED_10GB_SHIFT\t0x3\n-#define IAVF_LINK_SPEED_40GB_SHIFT\t0x4\n-#define IAVF_LINK_SPEED_20GB_SHIFT\t0x5\n-#define IAVF_LINK_SPEED_25GB_SHIFT\t0x6\n-\n-enum iavf_aq_link_speed {\n-\tIAVF_LINK_SPEED_UNKNOWN\t= 0,\n-\tIAVF_LINK_SPEED_100MB\t= (1 << IAVF_LINK_SPEED_100MB_SHIFT),\n-\tIAVF_LINK_SPEED_1GB\t= (1 << IAVF_LINK_SPEED_1000MB_SHIFT),\n-\tIAVF_LINK_SPEED_10GB\t= (1 << IAVF_LINK_SPEED_10GB_SHIFT),\n-\tIAVF_LINK_SPEED_40GB\t= (1 << IAVF_LINK_SPEED_40GB_SHIFT),\n-\tIAVF_LINK_SPEED_20GB\t= (1 << IAVF_LINK_SPEED_20GB_SHIFT),\n-\tIAVF_LINK_SPEED_25GB\t= (1 << IAVF_LINK_SPEED_25GB_SHIFT),\n-};\n-\n-struct iavf_aqc_module_desc {\n-\tu8 oui[3];\n-\tu8 reserved1;\n-\tu8 part_number[16];\n-\tu8 revision[4];\n-\tu8 reserved2[8];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);\n-\n-struct iavf_aq_get_phy_abilities_resp {\n-\t__le32\tphy_type;       /* bitmap using the above enum for offsets */\n-\tu8\tlink_speed;     /* bitmap using the above enum bit patterns */\n-\tu8\tabilities;\n-#define IAVF_AQ_PHY_FLAG_PAUSE_TX\t0x01\n-#define IAVF_AQ_PHY_FLAG_PAUSE_RX\t0x02\n-#define IAVF_AQ_PHY_FLAG_LOW_POWER\t0x04\n-#define IAVF_AQ_PHY_LINK_ENABLED\t0x08\n-#define IAVF_AQ_PHY_AN_ENABLED\t\t0x10\n-#define IAVF_AQ_PHY_FLAG_MODULE_QUAL\t0x20\n-#define IAVF_AQ_PHY_FEC_ABILITY_KR\t0x40\n-#define IAVF_AQ_PHY_FEC_ABILITY_RS\t0x80\n-\t__le16\teee_capability;\n-#define IAVF_AQ_EEE_100BASE_TX\t\t0x0002\n-#define IAVF_AQ_EEE_1000BASE_T\t\t0x0004\n-#define IAVF_AQ_EEE_10GBASE_T\t\t0x0008\n-#define IAVF_AQ_EEE_1000BASE_KX\t\t0x0010\n-#define IAVF_AQ_EEE_10GBASE_KX4\t\t0x0020\n-#define IAVF_AQ_EEE_10GBASE_KR\t\t0x0040\n-\t__le32\teeer_val;\n-\tu8\td3_lpan;\n-#define IAVF_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n-\tu8\tphy_type_ext;\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_KR\t0x01\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_CR\t0x02\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_SR\t0x04\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_AOC\t0x10\n-#define IAVF_AQ_PHY_TYPE_EXT_25G_ACC\t0x20\n-\tu8\tfec_cfg_curr_mod_ext_info;\n-#define IAVF_AQ_ENABLE_FEC_KR\t\t0x01\n-#define IAVF_AQ_ENABLE_FEC_RS\t\t0x02\n-#define IAVF_AQ_REQUEST_FEC_KR\t\t0x04\n-#define IAVF_AQ_REQUEST_FEC_RS\t\t0x08\n-#define IAVF_AQ_ENABLE_FEC_AUTO\t\t0x10\n-#define IAVF_AQ_FEC\n-#define IAVF_AQ_MODULE_TYPE_EXT_MASK\t0xE0\n-#define IAVF_AQ_MODULE_TYPE_EXT_SHIFT\t5\n-\n-\tu8\text_comp_code;\n-\tu8\tphy_id[4];\n-\tu8\tmodule_type[3];\n-\tu8\tqualified_module_count;\n-#define IAVF_AQ_PHY_MAX_QMS\t\t16\n-\tstruct iavf_aqc_module_desc\tqualified_module[IAVF_AQ_PHY_MAX_QMS];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);\n-\n-/* Set PHY Config (direct 0x0601) */\n-struct iavf_aq_set_phy_config { /* same bits as above in all */\n-\t__le32\tphy_type;\n-\tu8\tlink_speed;\n-\tu8\tabilities;\n-/* bits 0-2 use the values from get_phy_abilities_resp */\n-#define IAVF_AQ_PHY_ENABLE_LINK\t\t0x08\n-#define IAVF_AQ_PHY_ENABLE_AN\t\t0x10\n-#define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK\t0x20\n-\t__le16\teee_capability;\n-\t__le32\teeer;\n-\tu8\tlow_power_ctrl;\n-\tu8\tphy_type_ext;\n-\tu8\tfec_config;\n-#define IAVF_AQ_SET_FEC_ABILITY_KR\tBIT(0)\n-#define IAVF_AQ_SET_FEC_ABILITY_RS\tBIT(1)\n-#define IAVF_AQ_SET_FEC_REQUEST_KR\tBIT(2)\n-#define IAVF_AQ_SET_FEC_REQUEST_RS\tBIT(3)\n-#define IAVF_AQ_SET_FEC_AUTO\t\tBIT(4)\n-#define IAVF_AQ_PHY_FEC_CONFIG_SHIFT\t0x0\n-#define IAVF_AQ_PHY_FEC_CONFIG_MASK\t(0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)\n-\tu8\treserved;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);\n-\n-/* Set MAC Config command data structure (direct 0x0603) */\n-struct iavf_aq_set_mac_config {\n-\t__le16\tmax_frame_size;\n-\tu8\tparams;\n-#define IAVF_AQ_SET_MAC_CONFIG_CRC_EN\t\t0x04\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK\t0x78\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT\t3\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE\t0x0\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX\t0xF\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX\t0x9\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX\t0x8\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX\t0x7\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX\t0x6\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX\t0x5\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX\t0x4\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX\t0x3\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX\t0x2\n-#define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX\t0x1\n-\tu8\ttx_timer_priority; /* bitmap */\n-\t__le16\ttx_timer_value;\n-\t__le16\tfc_refresh_threshold;\n-\tu8\treserved[8];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);\n-\n-/* Restart Auto-Negotiation (direct 0x605) */\n-struct iavf_aqc_set_link_restart_an {\n-\tu8\tcommand;\n-#define IAVF_AQ_PHY_RESTART_AN\t0x02\n-#define IAVF_AQ_PHY_LINK_ENABLE\t0x04\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);\n-\n-/* Get Link Status cmd & response data structure (direct 0x0607) */\n-struct iavf_aqc_get_link_status {\n-\t__le16\tcommand_flags; /* only field set on command */\n-#define IAVF_AQ_LSE_MASK\t\t0x3\n-#define IAVF_AQ_LSE_NOP\t\t\t0x0\n-#define IAVF_AQ_LSE_DISABLE\t\t0x2\n-#define IAVF_AQ_LSE_ENABLE\t\t0x3\n-/* only response uses this flag */\n-#define IAVF_AQ_LSE_IS_ENABLED\t\t0x1\n-\tu8\tphy_type;    /* iavf_aq_phy_type   */\n-\tu8\tlink_speed;  /* iavf_aq_link_speed */\n-\tu8\tlink_info;\n-#define IAVF_AQ_LINK_UP\t\t\t0x01    /* obsolete */\n-#define IAVF_AQ_LINK_UP_FUNCTION\t0x01\n-#define IAVF_AQ_LINK_FAULT\t\t0x02\n-#define IAVF_AQ_LINK_FAULT_TX\t\t0x04\n-#define IAVF_AQ_LINK_FAULT_RX\t\t0x08\n-#define IAVF_AQ_LINK_FAULT_REMOTE\t0x10\n-#define IAVF_AQ_LINK_UP_PORT\t\t0x20\n-#define IAVF_AQ_MEDIA_AVAILABLE\t\t0x40\n-#define IAVF_AQ_SIGNAL_DETECT\t\t0x80\n-\tu8\tan_info;\n-#define IAVF_AQ_AN_COMPLETED\t\t0x01\n-#define IAVF_AQ_LP_AN_ABILITY\t\t0x02\n-#define IAVF_AQ_PD_FAULT\t\t0x04\n-#define IAVF_AQ_FEC_EN\t\t\t0x08\n-#define IAVF_AQ_PHY_LOW_POWER\t\t0x10\n-#define IAVF_AQ_LINK_PAUSE_TX\t\t0x20\n-#define IAVF_AQ_LINK_PAUSE_RX\t\t0x40\n-#define IAVF_AQ_QUALIFIED_MODULE\t0x80\n-\tu8\text_info;\n-#define IAVF_AQ_LINK_PHY_TEMP_ALARM\t0x01\n-#define IAVF_AQ_LINK_XCESSIVE_ERRORS\t0x02\n-#define IAVF_AQ_LINK_TX_SHIFT\t\t0x02\n-#define IAVF_AQ_LINK_TX_MASK\t\t(0x03 << IAVF_AQ_LINK_TX_SHIFT)\n-#define IAVF_AQ_LINK_TX_ACTIVE\t\t0x00\n-#define IAVF_AQ_LINK_TX_DRAINED\t\t0x01\n-#define IAVF_AQ_LINK_TX_FLUSHED\t\t0x03\n-#define IAVF_AQ_LINK_FORCED_40G\t\t0x10\n-/* 25G Error Codes */\n-#define IAVF_AQ_25G_NO_ERR\t\t0X00\n-#define IAVF_AQ_25G_NOT_PRESENT\t\t0X01\n-#define IAVF_AQ_25G_NVM_CRC_ERR\t\t0X02\n-#define IAVF_AQ_25G_SBUS_UCODE_ERR\t0X03\n-#define IAVF_AQ_25G_SERDES_UCODE_ERR\t0X04\n-#define IAVF_AQ_25G_NIMB_UCODE_ERR\t0X05\n-\tu8\tloopback; /* use defines from iavf_aqc_set_lb_mode */\n-/* Since firmware API 1.7 loopback field keeps power class info as well */\n-#define IAVF_AQ_LOOPBACK_MASK\t\t0x07\n-#define IAVF_AQ_PWR_CLASS_SHIFT_LB\t6\n-#define IAVF_AQ_PWR_CLASS_MASK_LB\t(0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)\n-\t__le16\tmax_frame_size;\n-\tu8\tconfig;\n-#define IAVF_AQ_CONFIG_FEC_KR_ENA\t0x01\n-#define IAVF_AQ_CONFIG_FEC_RS_ENA\t0x02\n-#define IAVF_AQ_CONFIG_CRC_ENA\t\t0x04\n-#define IAVF_AQ_CONFIG_PACING_MASK\t0x78\n-\tunion {\n-\t\tstruct {\n-\t\t\tu8\tpower_desc;\n-#define IAVF_AQ_LINK_POWER_CLASS_1\t0x00\n-#define IAVF_AQ_LINK_POWER_CLASS_2\t0x01\n-#define IAVF_AQ_LINK_POWER_CLASS_3\t0x02\n-#define IAVF_AQ_LINK_POWER_CLASS_4\t0x03\n-#define IAVF_AQ_PWR_CLASS_MASK\t\t0x03\n-\t\t\tu8\treserved[4];\n-\t\t};\n-\t\tstruct {\n-\t\t\tu8\tlink_type[4];\n-\t\t\tu8\tlink_type_ext;\n-\t\t};\n-\t};\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);\n-\n-/* Set event mask command (direct 0x613) */\n-struct iavf_aqc_set_phy_int_mask {\n-\tu8\treserved[8];\n-\t__le16\tevent_mask;\n-#define IAVF_AQ_EVENT_LINK_UPDOWN\t0x0002\n-#define IAVF_AQ_EVENT_MEDIA_NA\t\t0x0004\n-#define IAVF_AQ_EVENT_LINK_FAULT\t0x0008\n-#define IAVF_AQ_EVENT_PHY_TEMP_ALARM\t0x0010\n-#define IAVF_AQ_EVENT_EXCESSIVE_ERRORS\t0x0020\n-#define IAVF_AQ_EVENT_SIGNAL_DETECT\t0x0040\n-#define IAVF_AQ_EVENT_AN_COMPLETED\t0x0080\n-#define IAVF_AQ_EVENT_MODULE_QUAL_FAIL\t0x0100\n-#define IAVF_AQ_EVENT_PORT_TX_SUSPENDED\t0x0200\n-\tu8\treserved1[6];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);\n-\n-/* Get Local AN advt register (direct 0x0614)\n- * Set Local AN advt register (direct 0x0615)\n- * Get Link Partner AN advt register (direct 0x0616)\n- */\n-struct iavf_aqc_an_advt_reg {\n-\t__le32\tlocal_an_reg0;\n-\t__le16\tlocal_an_reg1;\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);\n-\n-/* Set Loopback mode (0x0618) */\n-struct iavf_aqc_set_lb_mode {\n-\tu8\tlb_level;\n-#define IAVF_AQ_LB_NONE\t0\n-#define IAVF_AQ_LB_MAC\t1\n-#define IAVF_AQ_LB_SERDES\t2\n-#define IAVF_AQ_LB_PHY_INT\t3\n-#define IAVF_AQ_LB_PHY_EXT\t4\n-#define IAVF_AQ_LB_CPVL_PCS\t5\n-#define IAVF_AQ_LB_CPVL_EXT\t6\n-#define IAVF_AQ_LB_PHY_LOCAL\t0x01\n-#define IAVF_AQ_LB_PHY_REMOTE\t0x02\n-#define IAVF_AQ_LB_MAC_LOCAL\t0x04\n-\tu8\tlb_type;\n-#define IAVF_AQ_LB_LOCAL\t0\n-#define IAVF_AQ_LB_FAR\t0x01\n-\tu8\tspeed;\n-#define IAVF_AQ_LB_SPEED_NONE\t0\n-#define IAVF_AQ_LB_SPEED_1G\t1\n-#define IAVF_AQ_LB_SPEED_10G\t2\n-#define IAVF_AQ_LB_SPEED_40G\t3\n-#define IAVF_AQ_LB_SPEED_20G\t4\n-\tu8\tforce_speed;\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);\n-\n-/* Set PHY Debug command (0x0622) */\n-struct iavf_aqc_set_phy_debug {\n-\tu8\tcommand_flags;\n-#define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL\t0x02\n-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT\t2\n-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK\t(0x03 << \\\n-\t\t\t\t\tIAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)\n-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE\t0x00\n-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD\t0x01\n-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT\t0x02\n-/* Disable link manageability on a single port */\n-#define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW\t0x10\n-/* Disable link manageability on all ports needs both bits 4 and 5 */\n-#define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW\t0x20\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);\n-\n-enum iavf_aq_phy_reg_type {\n-\tIAVF_AQC_PHY_REG_INTERNAL\t= 0x1,\n-\tIAVF_AQC_PHY_REG_EXERNAL_BASET\t= 0x2,\n-\tIAVF_AQC_PHY_REG_EXERNAL_MODULE\t= 0x3\n-};\n-\n-/* Run PHY Activity (0x0626) */\n-struct iavf_aqc_run_phy_activity {\n-\t__le16  activity_id;\n-\tu8      flags;\n-\tu8      reserved1;\n-\t__le32  control;\n-\t__le32  data;\n-\tu8      reserved2[4];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);\n-\n-/* Set PHY Register command (0x0628) */\n-/* Get PHY Register command (0x0629) */\n-struct iavf_aqc_phy_register_access {\n-\tu8\tphy_interface;\n-#define IAVF_AQ_PHY_REG_ACCESS_INTERNAL\t0\n-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL\t1\n-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE\t2\n-\tu8\tdev_addres;\n-\tu8\treserved1[2];\n-\t__le32\treg_address;\n-\t__le32\treg_value;\n-\tu8\treserved2[4];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);\n-\n-/* NVM Read command (indirect 0x0701)\n- * NVM Erase commands (direct 0x0702)\n- * NVM Update commands (indirect 0x0703)\n- */\n-struct iavf_aqc_nvm_update {\n-\tu8\tcommand_flags;\n-#define IAVF_AQ_NVM_LAST_CMD\t\t\t0x01\n-#define IAVF_AQ_NVM_FLASH_ONLY\t\t\t0x80\n-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT\t1\n-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK\t0x03\n-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED\t0x03\n-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL\t0x01\n-\tu8\tmodule_pointer;\n-\t__le16\tlength;\n-\t__le32\toffset;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);\n-\n-/* NVM Config Read (indirect 0x0704) */\n-struct iavf_aqc_nvm_config_read {\n-\t__le16\tcmd_flags;\n-#define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n-#define IAVF_AQ_ANVM_READ_SINGLE_FEATURE\t\t0\n-#define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES\t\t1\n-\t__le16\telement_count;\n-\t__le16\telement_id;\t/* Feature/field ID */\n-\t__le16\telement_id_msw;\t/* MSWord of field ID */\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);\n-\n-/* NVM Config Write (indirect 0x0705) */\n-struct iavf_aqc_nvm_config_write {\n-\t__le16\tcmd_flags;\n-\t__le16\telement_count;\n-\tu8\treserved[4];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);\n-\n-/* Used for 0x0704 as well as for 0x0705 commands */\n-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT\t\t1\n-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \\\n-\t\t\t\t(1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)\n-#define IAVF_AQ_ANVM_FEATURE\t\t0\n-#define IAVF_AQ_ANVM_IMMEDIATE_FIELD\t(1 << FEATURE_OR_IMMEDIATE_SHIFT)\n-struct iavf_aqc_nvm_config_data_feature {\n-\t__le16 feature_id;\n-#define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY\t\t0x01\n-#define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP\t\t0x08\n-#define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR\t\t0x10\n-\t__le16 feature_options;\n-\t__le16 feature_selection;\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);\n-\n-struct iavf_aqc_nvm_config_data_immediate_field {\n-\t__le32 field_id;\n-\t__le32 field_value;\n-\t__le16 field_options;\n-\t__le16 reserved;\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);\n-\n-/* OEM Post Update (indirect 0x0720)\n- * no command data struct used\n- */\n-struct iavf_aqc_nvm_oem_post_update {\n-#define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA\t0x01\n-\tu8 sel_data;\n-\tu8 reserved[7];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);\n-\n-struct iavf_aqc_nvm_oem_post_update_buffer {\n-\tu8 str_len;\n-\tu8 dev_addr;\n-\t__le16 eeprom_addr;\n-\tu8 data[36];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);\n-\n-/* Thermal Sensor (indirect 0x0721)\n- *     read or set thermal sensor configs and values\n- *     takes a sensor and command specific data buffer, not detailed here\n- */\n-struct iavf_aqc_thermal_sensor {\n-\tu8 sensor_action;\n-#define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG\t0\n-#define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG\t1\n-#define IAVF_AQ_THERMAL_SENSOR_READ_TEMP\t2\n-\tu8 reserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);\n-\n-/* Send to PF command (indirect 0x0801) id is only used by PF\n- * Send to VF command (indirect 0x0802) id is only used by PF\n- * Send to Peer PF command (indirect 0x0803)\n- */\n-struct iavf_aqc_pf_vf_message {\n-\t__le32\tid;\n-\tu8\treserved[4];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);\n-\n-/* Alternate structure */\n-\n-/* Direct write (direct 0x0900)\n- * Direct read (direct 0x0902)\n- */\n-struct iavf_aqc_alternate_write {\n-\t__le32 address0;\n-\t__le32 data0;\n-\t__le32 address1;\n-\t__le32 data1;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);\n-\n-/* Indirect write (indirect 0x0901)\n- * Indirect read (indirect 0x0903)\n- */\n-\n-struct iavf_aqc_alternate_ind_write {\n-\t__le32 address;\n-\t__le32 length;\n-\t__le32 addr_high;\n-\t__le32 addr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);\n-\n-/* Done alternate write (direct 0x0904)\n- * uses iavf_aq_desc\n- */\n-struct iavf_aqc_alternate_write_done {\n-\t__le16\tcmd_flags;\n-#define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK\t1\n-#define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY\t0\n-#define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI\t1\n-#define IAVF_AQ_ALTERNATE_RESET_NEEDED\t\t2\n-\tu8\treserved[14];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);\n-\n-/* Set OEM mode (direct 0x0905) */\n-struct iavf_aqc_alternate_set_mode {\n-\t__le32\tmode;\n-#define IAVF_AQ_ALTERNATE_MODE_NONE\t0\n-#define IAVF_AQ_ALTERNATE_MODE_OEM\t1\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);\n-\n-/* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */\n-\n-/* async events 0x10xx */\n-\n-/* Lan Queue Overflow Event (direct, 0x1001) */\n-struct iavf_aqc_lan_overflow {\n-\t__le32\tprtdcb_rupto;\n-\t__le32\totx_ctl;\n-\tu8\treserved[8];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);\n-\n-/* Get LLDP MIB (indirect 0x0A00) */\n-struct iavf_aqc_lldp_get_mib {\n-\tu8\ttype;\n-\tu8\treserved1;\n-#define IAVF_AQ_LLDP_MIB_TYPE_MASK\t\t0x3\n-#define IAVF_AQ_LLDP_MIB_LOCAL\t\t\t0x0\n-#define IAVF_AQ_LLDP_MIB_REMOTE\t\t\t0x1\n-#define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE\t0x2\n-#define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK\t\t0xC\n-#define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT\t\t0x2\n-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE\t0x0\n-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR\t0x1\n-#define IAVF_AQ_LLDP_TX_SHIFT\t\t\t0x4\n-#define IAVF_AQ_LLDP_TX_MASK\t\t\t(0x03 << IAVF_AQ_LLDP_TX_SHIFT)\n-/* TX pause flags use IAVF_AQ_LINK_TX_* above */\n-\t__le16\tlocal_len;\n-\t__le16\tremote_len;\n-\tu8\treserved2[2];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);\n-\n-/* Configure LLDP MIB Change Event (direct 0x0A01)\n- * also used for the event (with type in the command field)\n- */\n-struct iavf_aqc_lldp_update_mib {\n-\tu8\tcommand;\n-#define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE\t0x0\n-#define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE\t0x1\n-\tu8\treserved[7];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);\n-\n-/* Add LLDP TLV (indirect 0x0A02)\n- * Delete LLDP TLV (indirect 0x0A04)\n- */\n-struct iavf_aqc_lldp_add_tlv {\n-\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8\treserved1[1];\n-\t__le16\tlen;\n-\tu8\treserved2[4];\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);\n-\n-/* Update LLDP TLV (indirect 0x0A03) */\n-struct iavf_aqc_lldp_update_tlv {\n-\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n-\tu8\treserved;\n-\t__le16\told_len;\n-\t__le16\tnew_offset;\n-\t__le16\tnew_len;\n-\t__le32\taddr_high;\n-\t__le32\taddr_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);\n-\n-/* Stop LLDP (direct 0x0A05) */\n-struct iavf_aqc_lldp_stop {\n-\tu8\tcommand;\n-#define IAVF_AQ_LLDP_AGENT_STOP\t\t0x0\n-#define IAVF_AQ_LLDP_AGENT_SHUTDOWN\t0x1\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);\n-\n-/* Start LLDP (direct 0x0A06) */\n-\n-struct iavf_aqc_lldp_start {\n-\tu8\tcommand;\n-#define IAVF_AQ_LLDP_AGENT_START\t0x1\n-\tu8\treserved[15];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);\n-\n-/* Set DCB (direct 0x0303) */\n-struct iavf_aqc_set_dcb_parameters {\n-\tu8 command;\n-#define IAVF_AQ_DCB_SET_AGENT\t0x1\n-#define IAVF_DCB_VALID\t\t0x1\n-\tu8 valid_flags;\n-\tu8 reserved[14];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);\n-\n-/* Get CEE DCBX Oper Config (0x0A07)\n- * uses the generic descriptor struct\n- * returns below as indirect response\n- */\n-\n-#define IAVF_AQC_CEE_APP_FCOE_SHIFT\t0x0\n-#define IAVF_AQC_CEE_APP_FCOE_MASK\t(0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)\n-#define IAVF_AQC_CEE_APP_ISCSI_SHIFT\t0x3\n-#define IAVF_AQC_CEE_APP_ISCSI_MASK\t(0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)\n-#define IAVF_AQC_CEE_APP_FIP_SHIFT\t0x8\n-#define IAVF_AQC_CEE_APP_FIP_MASK\t(0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)\n-\n-#define IAVF_AQC_CEE_PG_STATUS_SHIFT\t0x0\n-#define IAVF_AQC_CEE_PG_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)\n-#define IAVF_AQC_CEE_PFC_STATUS_SHIFT\t0x3\n-#define IAVF_AQC_CEE_PFC_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)\n-#define IAVF_AQC_CEE_APP_STATUS_SHIFT\t0x8\n-#define IAVF_AQC_CEE_APP_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)\n-#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT\t0x8\n-#define IAVF_AQC_CEE_FCOE_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)\n-#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT\t0xB\n-#define IAVF_AQC_CEE_ISCSI_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)\n-#define IAVF_AQC_CEE_FIP_STATUS_SHIFT\t0x10\n-#define IAVF_AQC_CEE_FIP_STATUS_MASK\t(0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)\n-\n-/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with\n- * word boundary layout issues, which the Linux compilers silently deal\n- * with by adding padding, making the actual struct larger than designed.\n- * However, the FW compiler for the NIC is less lenient and complains\n- * about the struct.  Hence, the struct defined here has an extra byte in\n- * fields reserved3 and reserved4 to directly acknowledge that padding,\n- * and the new length is used in the length check macro.\n- */\n-struct iavf_aqc_get_cee_dcb_cfg_v1_resp {\n-\tu8\treserved1;\n-\tu8\toper_num_tc;\n-\tu8\toper_prio_tc[4];\n-\tu8\treserved2;\n-\tu8\toper_tc_bw[8];\n-\tu8\toper_pfc_en;\n-\tu8\treserved3[2];\n-\t__le16\toper_app_prio;\n-\tu8\treserved4[2];\n-\t__le16\ttlv_status;\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);\n-\n-struct iavf_aqc_get_cee_dcb_cfg_resp {\n-\tu8\toper_num_tc;\n-\tu8\toper_prio_tc[4];\n-\tu8\toper_tc_bw[8];\n-\tu8\toper_pfc_en;\n-\t__le16\toper_app_prio;\n-\t__le32\ttlv_status;\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);\n-\n-/*\tSet Local LLDP MIB (indirect 0x0A08)\n- *\tUsed to replace the local MIB of a given LLDP agent. e.g. DCBx\n- */\n-struct iavf_aqc_lldp_set_local_mib {\n-#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT\t0\n-#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK\t(1 << \\\n-\t\t\t\t\tSET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)\n-#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB\t0x0\n-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT\t(1)\n-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK\t(1 << \\\n-\t\t\t\tSET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)\n-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS\t\t0x1\n-\tu8\ttype;\n-\tu8\treserved0;\n-\t__le16\tlength;\n-\tu8\treserved1[4];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n+struct iavf_aqc_lldp_set_local_mib {\n+#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT\t0\n+#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK\t(1 << \\\n+\t\t\t\t\tSET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)\n+#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB\t0x0\n+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT\t(1)\n+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK\t(1 << \\\n+\t\t\t\tSET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)\n+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS\t\t0x1\n+\tu8\ttype;\n+\tu8\treserved0;\n+\t__le16\tlength;\n+\tu8\treserved1[4];\n+\t__le32\taddress_high;\n+\t__le32\taddress_low;\n };\n \n IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);\n@@ -2567,51 +604,6 @@ struct iavf_aqc_lldp_stop_start_specific_agent {\n \n IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);\n \n-/* Add Udp Tunnel command and completion (direct 0x0B00) */\n-struct iavf_aqc_add_udp_tunnel {\n-\t__le16\tudp_port;\n-\tu8\treserved0[3];\n-\tu8\tprotocol_type;\n-#define IAVF_AQC_TUNNEL_TYPE_VXLAN\t0x00\n-#define IAVF_AQC_TUNNEL_TYPE_NGE\t0x01\n-#define IAVF_AQC_TUNNEL_TYPE_TEREDO\t0x10\n-#define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE\t0x11\n-\tu8\treserved1[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);\n-\n-struct iavf_aqc_add_udp_tunnel_completion {\n-\t__le16\tudp_port;\n-\tu8\tfilter_entry_index;\n-\tu8\tmultiple_pfs;\n-#define IAVF_AQC_SINGLE_PF\t\t0x0\n-#define IAVF_AQC_MULTIPLE_PFS\t\t0x1\n-\tu8\ttotal_filters;\n-\tu8\treserved[11];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);\n-\n-/* remove UDP Tunnel command (0x0B01) */\n-struct iavf_aqc_remove_udp_tunnel {\n-\tu8\treserved[2];\n-\tu8\tindex; /* 0 to 15 */\n-\tu8\treserved2[13];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);\n-\n-struct iavf_aqc_del_udp_tunnel_completion {\n-\t__le16\tudp_port;\n-\tu8\tindex; /* 0 to 15 */\n-\tu8\tmultiple_pfs;\n-\tu8\ttotal_filters_used;\n-\tu8\treserved1[11];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);\n-\n struct iavf_aqc_get_set_rss_key {\n #define IAVF_AQC_SET_RSS_KEY_VSI_VALID\t\t(0x1 << 15)\n #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n@@ -2651,162 +643,4 @@ struct  iavf_aqc_get_set_rss_lut {\n };\n \n IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);\n-\n-/* tunnel key structure 0x0B10 */\n-\n-struct iavf_aqc_tunnel_key_structure {\n-\tu8\tkey1_off;\n-\tu8\tkey2_off;\n-\tu8\tkey1_len;  /* 0 to 15 */\n-\tu8\tkey2_len;  /* 0 to 15 */\n-\tu8\tflags;\n-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE\t0x01\n-/* response flags */\n-#define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS\t0x01\n-#define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED\t0x02\n-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN\t0x03\n-\tu8\tnetwork_key_index;\n-#define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN\t\t0x0\n-#define IAVF_AQC_NETWORK_KEY_INDEX_NGE\t\t\t0x1\n-#define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP\t0x2\n-#define IAVF_AQC_NETWORK_KEY_INDEX_GRE\t\t\t0x3\n-\tu8\treserved[10];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);\n-\n-/* OEM mode commands (direct 0xFE0x) */\n-struct iavf_aqc_oem_param_change {\n-\t__le32\tparam_type;\n-#define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL\t0\n-#define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL\t1\n-#define IAVF_AQ_OEM_PARAM_MAC\t\t2\n-\t__le32\tparam_value1;\n-\t__le16\tparam_value2;\n-\tu8\treserved[6];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);\n-\n-struct iavf_aqc_oem_state_change {\n-\t__le32\tstate;\n-#define IAVF_AQ_OEM_STATE_LINK_DOWN\t0x0\n-#define IAVF_AQ_OEM_STATE_LINK_UP\t0x1\n-\tu8\treserved[12];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);\n-\n-/* Initialize OCSD (0xFE02, direct) */\n-struct iavf_aqc_opc_oem_ocsd_initialize {\n-\tu8 type_status;\n-\tu8 reserved1[3];\n-\t__le32 ocsd_memory_block_addr_high;\n-\t__le32 ocsd_memory_block_addr_low;\n-\t__le32 requested_update_interval;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);\n-\n-/* Initialize OCBB  (0xFE03, direct) */\n-struct iavf_aqc_opc_oem_ocbb_initialize {\n-\tu8 type_status;\n-\tu8 reserved1[3];\n-\t__le32 ocbb_memory_block_addr_high;\n-\t__le32 ocbb_memory_block_addr_low;\n-\tu8 reserved2[4];\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);\n-\n-/* debug commands */\n-\n-/* get device id (0xFF00) uses the generic structure */\n-\n-/* set test more (0xFF01, internal) */\n-\n-struct iavf_acq_set_test_mode {\n-\tu8\tmode;\n-#define IAVF_AQ_TEST_PARTIAL\t0\n-#define IAVF_AQ_TEST_FULL\t1\n-#define IAVF_AQ_TEST_NVM\t2\n-\tu8\treserved[3];\n-\tu8\tcommand;\n-#define IAVF_AQ_TEST_OPEN\t0\n-#define IAVF_AQ_TEST_CLOSE\t1\n-#define IAVF_AQ_TEST_INC\t2\n-\tu8\treserved2[3];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);\n-\n-/* Debug Read Register command (0xFF03)\n- * Debug Write Register command (0xFF04)\n- */\n-struct iavf_aqc_debug_reg_read_write {\n-\t__le32 reserved;\n-\t__le32 address;\n-\t__le32 value_high;\n-\t__le32 value_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);\n-\n-/* Scatter/gather Reg Read  (indirect 0xFF05)\n- * Scatter/gather Reg Write (indirect 0xFF06)\n- */\n-\n-/* iavf_aq_desc is used for the command */\n-struct iavf_aqc_debug_reg_sg_element_data {\n-\t__le32 address;\n-\t__le32 value;\n-};\n-\n-/* Debug Modify register (direct 0xFF07) */\n-struct iavf_aqc_debug_modify_reg {\n-\t__le32 address;\n-\t__le32 value;\n-\t__le32 clear_mask;\n-\t__le32 set_mask;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);\n-\n-/* dump internal data (0xFF08, indirect) */\n-\n-#define IAVF_AQ_CLUSTER_ID_AUX\t\t0\n-#define IAVF_AQ_CLUSTER_ID_SWITCH_FLU\t1\n-#define IAVF_AQ_CLUSTER_ID_TXSCHED\t2\n-#define IAVF_AQ_CLUSTER_ID_HMC\t\t3\n-#define IAVF_AQ_CLUSTER_ID_MAC0\t\t4\n-#define IAVF_AQ_CLUSTER_ID_MAC1\t\t5\n-#define IAVF_AQ_CLUSTER_ID_MAC2\t\t6\n-#define IAVF_AQ_CLUSTER_ID_MAC3\t\t7\n-#define IAVF_AQ_CLUSTER_ID_DCB\t\t8\n-#define IAVF_AQ_CLUSTER_ID_EMP_MEM\t9\n-#define IAVF_AQ_CLUSTER_ID_PKT_BUF\t10\n-#define IAVF_AQ_CLUSTER_ID_ALTRAM\t11\n-\n-struct iavf_aqc_debug_dump_internals {\n-\tu8\tcluster_id;\n-\tu8\ttable_id;\n-\t__le16\tdata_size;\n-\t__le32\tidx;\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);\n-\n-struct iavf_aqc_debug_modify_internals {\n-\tu8\tcluster_id;\n-\tu8\tcluster_specific_params[7];\n-\t__le32\taddress_high;\n-\t__le32\taddress_low;\n-};\n-\n-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);\n-\n #endif /* _IAVF_ADMINQ_CMD_H_ */\ndiff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c\nindex 026dc4756..926081e87 100644\n--- a/drivers/net/iavf/base/iavf_common.c\n+++ b/drivers/net/iavf/base/iavf_common.c\n@@ -891,7 +891,6 @@ struct iavf_rx_ptype_decoded iavf_ptype_lookup[] = {\n \tIAVF_PTT_UNUSED_ENTRY(255)\n };\n \n-\n /**\n  * iavf_validate_mac_addr - Validate unicast MAC address\n  * @mac_addr: pointer to MAC address\n@@ -917,202 +916,6 @@ enum iavf_status iavf_validate_mac_addr(u8 *mac_addr)\n }\n \n /**\n- * iavf_aq_rx_ctl_read_register - use FW to read from an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: ptr to register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Use the firmware to read the Rx control register,\n- * especially useful if the Rx unit is under heavy pressure\n- **/\n-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_rx_ctl_reg_read_write *cmd_resp =\n-\t\t(struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tif (reg_val == NULL)\n-\t\treturn IAVF_ERR_PARAM;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_read);\n-\n-\tcmd_resp->address = CPU_TO_LE32(reg_addr);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\tif (status == IAVF_SUCCESS)\n-\t\t*reg_val = LE32_TO_CPU(cmd_resp->value);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_read_rx_ctl - read from an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- **/\n-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr)\n-{\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tbool use_register;\n-\tint retry = 5;\n-\tu32 val = 0;\n-\n-\tuse_register = (((hw->aq.api_maj_ver == 1) &&\n-\t\t\t(hw->aq.api_min_ver < 5)) ||\n-\t\t\t(hw->mac.type == IAVF_MAC_X722));\n-\tif (!use_register) {\n-do_retry:\n-\t\tstatus = iavf_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);\n-\t\tif (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {\n-\t\t\tiavf_msec_delay(1);\n-\t\t\tretry--;\n-\t\t\tgoto do_retry;\n-\t\t}\n-\t}\n-\n-\t/* if the AQ access failed, try the old-fashioned way */\n-\tif (status || use_register)\n-\t\tval = rd32(hw, reg_addr);\n-\n-\treturn val;\n-}\n-\n-/**\n- * iavf_aq_rx_ctl_write_register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Use the firmware to write to an Rx control register,\n- * especially useful if the Rx unit is under heavy pressure\n- **/\n-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_rx_ctl_reg_read_write *cmd =\n-\t\t(struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_write);\n-\n-\tcmd->address = CPU_TO_LE32(reg_addr);\n-\tcmd->value = CPU_TO_LE32(reg_val);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_write_rx_ctl - write to an Rx control register\n- * @hw: pointer to the hw struct\n- * @reg_addr: register address\n- * @reg_val: register value\n- **/\n-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val)\n-{\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tbool use_register;\n-\tint retry = 5;\n-\n-\tuse_register = (((hw->aq.api_maj_ver == 1) &&\n-\t\t\t(hw->aq.api_min_ver < 5)) ||\n-\t\t\t(hw->mac.type == IAVF_MAC_X722));\n-\tif (!use_register) {\n-do_retry:\n-\t\tstatus = iavf_aq_rx_ctl_write_register(hw, reg_addr,\n-\t\t\t\t\t\t       reg_val, NULL);\n-\t\tif (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {\n-\t\t\tiavf_msec_delay(1);\n-\t\t\tretry--;\n-\t\t\tgoto do_retry;\n-\t\t}\n-\t}\n-\n-\t/* if the AQ access failed, try the old-fashioned way */\n-\tif (status || use_register)\n-\t\twr32(hw, reg_addr, reg_val);\n-}\n-\n-/**\n- * iavf_aq_set_phy_register\n- * @hw: pointer to the hw struct\n- * @phy_select: select which phy should be accessed\n- * @dev_addr: PHY device address\n- * @reg_addr: PHY register address\n- * @reg_val: new register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Write the external PHY register.\n- **/\n-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 phy_select, u8 dev_addr,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_phy_register_access *cmd =\n-\t\t(struct iavf_aqc_phy_register_access *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t  iavf_aqc_opc_set_phy_register);\n-\n-\tcmd->phy_interface = phy_select;\n-\tcmd->dev_addres = dev_addr;\n-\tcmd->reg_address = CPU_TO_LE32(reg_addr);\n-\tcmd->reg_value = CPU_TO_LE32(reg_val);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_aq_get_phy_register\n- * @hw: pointer to the hw struct\n- * @phy_select: select which phy should be accessed\n- * @dev_addr: PHY device address\n- * @reg_addr: PHY register address\n- * @reg_val: read register value\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Read the external PHY register.\n- **/\n-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 phy_select, u8 dev_addr,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_phy_register_access *cmd =\n-\t\t(struct iavf_aqc_phy_register_access *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t\t  iavf_aqc_opc_get_phy_register);\n-\n-\tcmd->phy_interface = phy_select;\n-\tcmd->dev_addres = dev_addr;\n-\tcmd->reg_address = CPU_TO_LE32(reg_addr);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\tif (!status)\n-\t\t*reg_val = LE32_TO_CPU(cmd->reg_value);\n-\n-\treturn status;\n-}\n-\n-\n-/**\n  * iavf_aq_send_msg_to_pf\n  * @hw: pointer to the hardware structure\n  * @v_opcode: opcodes for VF-PF communication\n@@ -1178,8 +981,6 @@ void iavf_parse_hw_config(struct iavf_hw *hw,\n \thw->dev_caps.num_msix_vectors_vf = msg->max_vectors;\n \thw->dev_caps.dcb = msg->vf_cap_flags &\n \t\t\t   VIRTCHNL_VF_OFFLOAD_L2;\n-\thw->dev_caps.iwarp = (msg->vf_cap_flags &\n-\t\t\t      VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;\n \tfor (i = 0; i < msg->num_vsis; i++) {\n \t\tif (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {\n \t\t\tiavf_memcpy(hw->mac.perm_addr,\n@@ -1209,174 +1010,6 @@ enum iavf_status iavf_reset(struct iavf_hw *hw)\n }\n \n /**\n- * iavf_aq_set_arp_proxy_config\n- * @hw: pointer to the HW structure\n- * @proxy_config: pointer to proxy config command table struct\n- * @cmd_details: pointer to command details\n- *\n- * Set ARP offload parameters from pre-populated\n- * iavf_aqc_arp_proxy_data struct\n- **/\n-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,\n-\t\t\t\tstruct iavf_aqc_arp_proxy_data *proxy_config,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tenum iavf_status status;\n-\n-\tif (!proxy_config)\n-\t\treturn IAVF_ERR_PARAM;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_proxy_config);\n-\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);\n-\tdesc.params.external.addr_high =\n-\t\t\t\t  CPU_TO_LE32(IAVF_HI_DWORD((u64)proxy_config));\n-\tdesc.params.external.addr_low =\n-\t\t\t\t  CPU_TO_LE32(IAVF_LO_DWORD((u64)proxy_config));\n-\tdesc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_arp_proxy_data));\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, proxy_config,\n-\t\t\t\t       sizeof(struct iavf_aqc_arp_proxy_data),\n-\t\t\t\t       cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_aq_opc_set_ns_proxy_table_entry\n- * @hw: pointer to the HW structure\n- * @ns_proxy_table_entry: pointer to NS table entry command struct\n- * @cmd_details: pointer to command details\n- *\n- * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters\n- * from pre-populated iavf_aqc_ns_proxy_data struct\n- **/\n-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,\n-\t\t\tstruct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,\n-\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tenum iavf_status status;\n-\n-\tif (!ns_proxy_table_entry)\n-\t\treturn IAVF_ERR_PARAM;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\tiavf_aqc_opc_set_ns_proxy_table_entry);\n-\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);\n-\tdesc.params.external.addr_high =\n-\t\tCPU_TO_LE32(IAVF_HI_DWORD((u64)ns_proxy_table_entry));\n-\tdesc.params.external.addr_low =\n-\t\tCPU_TO_LE32(IAVF_LO_DWORD((u64)ns_proxy_table_entry));\n-\tdesc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_ns_proxy_data));\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, ns_proxy_table_entry,\n-\t\t\t\t       sizeof(struct iavf_aqc_ns_proxy_data),\n-\t\t\t\t       cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_aq_set_clear_wol_filter\n- * @hw: pointer to the hw struct\n- * @filter_index: index of filter to modify (0-7)\n- * @filter: buffer containing filter to be set\n- * @set_filter: true to set filter, false to clear filter\n- * @no_wol_tco: if true, pass through packets cannot cause wake-up\n- *\t\tif false, pass through packets may cause wake-up\n- * @filter_valid: true if filter action is valid\n- * @no_wol_tco_valid: true if no WoL in TCO traffic action valid\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Set or clear WoL filter for port attached to the PF\n- **/\n-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,\n-\t\t\t\tu8 filter_index,\n-\t\t\t\tstruct iavf_aqc_set_wol_filter_data *filter,\n-\t\t\t\tbool set_filter, bool no_wol_tco,\n-\t\t\t\tbool filter_valid, bool no_wol_tco_valid,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_set_wol_filter *cmd =\n-\t\t(struct iavf_aqc_set_wol_filter *)&desc.params.raw;\n-\tenum iavf_status status;\n-\tu16 cmd_flags = 0;\n-\tu16 valid_flags = 0;\n-\tu16 buff_len = 0;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_wol_filter);\n-\n-\tif (filter_index >= IAVF_AQC_MAX_NUM_WOL_FILTERS)\n-\t\treturn  IAVF_ERR_PARAM;\n-\tcmd->filter_index = CPU_TO_LE16(filter_index);\n-\n-\tif (set_filter) {\n-\t\tif (!filter)\n-\t\t\treturn  IAVF_ERR_PARAM;\n-\n-\t\tcmd_flags |= IAVF_AQC_SET_WOL_FILTER;\n-\t\tcmd_flags |= IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;\n-\t}\n-\n-\tif (no_wol_tco)\n-\t\tcmd_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL;\n-\tcmd->cmd_flags = CPU_TO_LE16(cmd_flags);\n-\n-\tif (filter_valid)\n-\t\tvalid_flags |= IAVF_AQC_SET_WOL_FILTER_ACTION_VALID;\n-\tif (no_wol_tco_valid)\n-\t\tvalid_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;\n-\tcmd->valid_flags = CPU_TO_LE16(valid_flags);\n-\n-\tbuff_len = sizeof(*filter);\n-\tdesc.datalen = CPU_TO_LE16(buff_len);\n-\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);\n-\n-\tcmd->address_high = CPU_TO_LE32(IAVF_HI_DWORD((u64)filter));\n-\tcmd->address_low = CPU_TO_LE32(IAVF_LO_DWORD((u64)filter));\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, filter,\n-\t\t\t\t       buff_len, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_aq_get_wake_event_reason\n- * @hw: pointer to the hw struct\n- * @wake_reason: return value, index of matching filter\n- * @cmd_details: pointer to command details structure or NULL\n- *\n- * Get information for the reason of a Wake Up event\n- **/\n-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,\n-\t\t\t\tu16 *wake_reason,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_get_wake_reason_completion *resp =\n-\t\t(struct iavf_aqc_get_wake_reason_completion *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_get_wake_reason);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n-\n-\tif (status == IAVF_SUCCESS)\n-\t\t*wake_reason = LE16_TO_CPU(resp->wake_reason);\n-\n-\treturn status;\n-}\n-\n-/**\n * iavf_aq_clear_all_wol_filters\n * @hw: pointer to the hw struct\n * @cmd_details: pointer to command details structure or NULL\n@@ -1396,423 +1029,3 @@ enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,\n \n \treturn status;\n }\n-\n-/**\n- * iavf_aq_write_ddp - Write dynamic device personalization (ddp)\n- * @hw: pointer to the hw struct\n- * @buff: command buffer (size in bytes = buff_size)\n- * @buff_size: buffer size in bytes\n- * @track_id: package tracking id\n- * @error_offset: returns error offset\n- * @error_info: returns error information\n- * @cmd_details: pointer to command details structure or NULL\n- **/\n-enum\n-iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,\n-\t\t\t\t   u16 buff_size, u32 track_id,\n-\t\t\t\t   u32 *error_offset, u32 *error_info,\n-\t\t\t\t   struct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_write_personalization_profile *cmd =\n-\t\t(struct iavf_aqc_write_personalization_profile *)\n-\t\t&desc.params.raw;\n-\tstruct iavf_aqc_write_ddp_resp *resp;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t\t  iavf_aqc_opc_write_personalization_profile);\n-\n-\tdesc.flags |= CPU_TO_LE16(IAVF_AQ_FLAG_BUF | IAVF_AQ_FLAG_RD);\n-\tif (buff_size > IAVF_AQ_LARGE_BUF)\n-\t\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);\n-\n-\tdesc.datalen = CPU_TO_LE16(buff_size);\n-\n-\tcmd->profile_track_id = CPU_TO_LE32(track_id);\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n-\tif (!status) {\n-\t\tresp = (struct iavf_aqc_write_ddp_resp *)&desc.params.raw;\n-\t\tif (error_offset)\n-\t\t\t*error_offset = LE32_TO_CPU(resp->error_offset);\n-\t\tif (error_info)\n-\t\t\t*error_info = LE32_TO_CPU(resp->error_info);\n-\t}\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_aq_get_ddp_list - Read dynamic device personalization (ddp)\n- * @hw: pointer to the hw struct\n- * @buff: command buffer (size in bytes = buff_size)\n- * @buff_size: buffer size in bytes\n- * @flags: AdminQ command flags\n- * @cmd_details: pointer to command details structure or NULL\n- **/\n-enum\n-iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,\n-\t\t\t\t      u16 buff_size, u8 flags,\n-\t\t\t\t      struct iavf_asq_cmd_details *cmd_details)\n-{\n-\tstruct iavf_aq_desc desc;\n-\tstruct iavf_aqc_get_applied_profiles *cmd =\n-\t\t(struct iavf_aqc_get_applied_profiles *)&desc.params.raw;\n-\tenum iavf_status status;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc,\n-\t\t\t  iavf_aqc_opc_get_personalization_profile_list);\n-\n-\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);\n-\tif (buff_size > IAVF_AQ_LARGE_BUF)\n-\t\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);\n-\tdesc.datalen = CPU_TO_LE16(buff_size);\n-\n-\tcmd->flags = flags;\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_find_segment_in_package\n- * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_IAVF)\n- * @pkg_hdr: pointer to the package header to be searched\n- *\n- * This function searches a package file for a particular segment type. On\n- * success it returns a pointer to the segment header, otherwise it will\n- * return NULL.\n- **/\n-struct iavf_generic_seg_header *\n-iavf_find_segment_in_package(u32 segment_type,\n-\t\t\t     struct iavf_package_header *pkg_hdr)\n-{\n-\tstruct iavf_generic_seg_header *segment;\n-\tu32 i;\n-\n-\t/* Search all package segments for the requested segment type */\n-\tfor (i = 0; i < pkg_hdr->segment_count; i++) {\n-\t\tsegment =\n-\t\t\t(struct iavf_generic_seg_header *)((u8 *)pkg_hdr +\n-\t\t\t pkg_hdr->segment_offset[i]);\n-\n-\t\tif (segment->type == segment_type)\n-\t\t\treturn segment;\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-/* Get section table in profile */\n-#define IAVF_SECTION_TABLE(profile, sec_tbl)\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\t\\\n-\t\tstruct iavf_profile_segment *p = (profile);\t\t\\\n-\t\tu32 count;\t\t\t\t\t\t\\\n-\t\tu32 *nvm;\t\t\t\t\t\t\\\n-\t\tcount = p->device_table_count;\t\t\t\t\\\n-\t\tnvm = (u32 *)&p->device_table[count];\t\t\t\\\n-\t\tsec_tbl = (struct iavf_section_table *)&nvm[nvm[0] + 1]; \\\n-\t} while (0)\n-\n-/* Get section header in profile */\n-#define IAVF_SECTION_HEADER(profile, offset)\t\t\t\t\\\n-\t(struct iavf_profile_section_header *)((u8 *)(profile) + (offset))\n-\n-/**\n- * iavf_find_section_in_profile\n- * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)\n- * @profile: pointer to the iavf segment header to be searched\n- *\n- * This function searches iavf segment for a particular section type. On\n- * success it returns a pointer to the section header, otherwise it will\n- * return NULL.\n- **/\n-struct iavf_profile_section_header *\n-iavf_find_section_in_profile(u32 section_type,\n-\t\t\t     struct iavf_profile_segment *profile)\n-{\n-\tstruct iavf_profile_section_header *sec;\n-\tstruct iavf_section_table *sec_tbl;\n-\tu32 sec_off;\n-\tu32 i;\n-\n-\tif (profile->header.type != SEGMENT_TYPE_IAVF)\n-\t\treturn NULL;\n-\n-\tIAVF_SECTION_TABLE(profile, sec_tbl);\n-\n-\tfor (i = 0; i < sec_tbl->section_count; i++) {\n-\t\tsec_off = sec_tbl->section_offset[i];\n-\t\tsec = IAVF_SECTION_HEADER(profile, sec_off);\n-\t\tif (sec->section.type == section_type)\n-\t\t\treturn sec;\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-/**\n- * iavf_ddp_exec_aq_section - Execute generic AQ for DDP\n- * @hw: pointer to the hw struct\n- * @aq: command buffer containing all data to execute AQ\n- **/\n-STATIC enum\n-iavf_status iavf_ddp_exec_aq_section(struct iavf_hw *hw,\n-\t\t\t\t\t  struct iavf_profile_aq_section *aq)\n-{\n-\tenum iavf_status status;\n-\tstruct iavf_aq_desc desc;\n-\tu8 *msg = NULL;\n-\tu16 msglen;\n-\n-\tiavf_fill_default_direct_cmd_desc(&desc, aq->opcode);\n-\tdesc.flags |= CPU_TO_LE16(aq->flags);\n-\tiavf_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),\n-\t\t    IAVF_NONDMA_TO_NONDMA);\n-\n-\tmsglen = aq->datalen;\n-\tif (msglen) {\n-\t\tdesc.flags |= CPU_TO_LE16((u16)(IAVF_AQ_FLAG_BUF |\n-\t\t\t\t\t\tIAVF_AQ_FLAG_RD));\n-\t\tif (msglen > IAVF_AQ_LARGE_BUF)\n-\t\t\tdesc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);\n-\t\tdesc.datalen = CPU_TO_LE16(msglen);\n-\t\tmsg = &aq->data[0];\n-\t}\n-\n-\tstatus = iavf_asq_send_command(hw, &desc, msg, msglen, NULL);\n-\n-\tif (status != IAVF_SUCCESS) {\n-\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t   \"unable to exec DDP AQ opcode %u, error %d\\n\",\n-\t\t\t   aq->opcode, status);\n-\t\treturn status;\n-\t}\n-\n-\t/* copy returned desc to aq_buf */\n-\tiavf_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),\n-\t\t    IAVF_NONDMA_TO_NONDMA);\n-\n-\treturn IAVF_SUCCESS;\n-}\n-\n-/**\n- * iavf_validate_profile\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package to be validated\n- * @track_id: package tracking id\n- * @rollback: flag if the profile is for rollback.\n- *\n- * Validates supported devices and profile's sections.\n- */\n-STATIC enum iavf_status\n-iavf_validate_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,\n-\t\t      u32 track_id, bool rollback)\n-{\n-\tstruct iavf_profile_section_header *sec = NULL;\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tstruct iavf_section_table *sec_tbl;\n-\tu32 vendor_dev_id;\n-\tu32 dev_cnt;\n-\tu32 sec_off;\n-\tu32 i;\n-\n-\tif (track_id == IAVF_DDP_TRACKID_INVALID) {\n-\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE, \"Invalid track_id\\n\");\n-\t\treturn IAVF_NOT_SUPPORTED;\n-\t}\n-\n-\tdev_cnt = profile->device_table_count;\n-\tfor (i = 0; i < dev_cnt; i++) {\n-\t\tvendor_dev_id = profile->device_table[i].vendor_dev_id;\n-\t\tif ((vendor_dev_id >> 16) == IAVF_INTEL_VENDOR_ID &&\n-\t\t    hw->device_id == (vendor_dev_id & 0xFFFF))\n-\t\t\tbreak;\n-\t}\n-\tif (dev_cnt && (i == dev_cnt)) {\n-\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t   \"Device doesn't support DDP\\n\");\n-\t\treturn IAVF_ERR_DEVICE_NOT_SUPPORTED;\n-\t}\n-\n-\tIAVF_SECTION_TABLE(profile, sec_tbl);\n-\n-\t/* Validate sections types */\n-\tfor (i = 0; i < sec_tbl->section_count; i++) {\n-\t\tsec_off = sec_tbl->section_offset[i];\n-\t\tsec = IAVF_SECTION_HEADER(profile, sec_off);\n-\t\tif (rollback) {\n-\t\t\tif (sec->section.type == SECTION_TYPE_MMIO ||\n-\t\t\t    sec->section.type == SECTION_TYPE_AQ ||\n-\t\t\t    sec->section.type == SECTION_TYPE_RB_AQ) {\n-\t\t\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t\t\t   \"Not a roll-back package\\n\");\n-\t\t\t\treturn IAVF_NOT_SUPPORTED;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tif (sec->section.type == SECTION_TYPE_RB_AQ ||\n-\t\t\t    sec->section.type == SECTION_TYPE_RB_MMIO) {\n-\t\t\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t\t\t   \"Not an original package\\n\");\n-\t\t\t\treturn IAVF_NOT_SUPPORTED;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\treturn status;\n-}\n-\n-/**\n- * iavf_write_profile\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package to be downloaded\n- * @track_id: package tracking id\n- *\n- * Handles the download of a complete package.\n- */\n-enum iavf_status\n-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,\n-\t\t   u32 track_id)\n-{\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tstruct iavf_section_table *sec_tbl;\n-\tstruct iavf_profile_section_header *sec = NULL;\n-\tstruct iavf_profile_aq_section *ddp_aq;\n-\tu32 section_size = 0;\n-\tu32 offset = 0, info = 0;\n-\tu32 sec_off;\n-\tu32 i;\n-\n-\tstatus = iavf_validate_profile(hw, profile, track_id, false);\n-\tif (status)\n-\t\treturn status;\n-\n-\tIAVF_SECTION_TABLE(profile, sec_tbl);\n-\n-\tfor (i = 0; i < sec_tbl->section_count; i++) {\n-\t\tsec_off = sec_tbl->section_offset[i];\n-\t\tsec = IAVF_SECTION_HEADER(profile, sec_off);\n-\t\t/* Process generic admin command */\n-\t\tif (sec->section.type == SECTION_TYPE_AQ) {\n-\t\t\tddp_aq = (struct iavf_profile_aq_section *)&sec[1];\n-\t\t\tstatus = iavf_ddp_exec_aq_section(hw, ddp_aq);\n-\t\t\tif (status) {\n-\t\t\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t\t\t   \"Failed to execute aq: section %d, opcode %u\\n\",\n-\t\t\t\t\t   i, ddp_aq->opcode);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tsec->section.type = SECTION_TYPE_RB_AQ;\n-\t\t}\n-\n-\t\t/* Skip any non-mmio sections */\n-\t\tif (sec->section.type != SECTION_TYPE_MMIO)\n-\t\t\tcontinue;\n-\n-\t\tsection_size = sec->section.size +\n-\t\t\tsizeof(struct iavf_profile_section_header);\n-\n-\t\t/* Write MMIO section */\n-\t\tstatus = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,\n-\t\t\t\t\t   track_id, &offset, &info, NULL);\n-\t\tif (status) {\n-\t\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t\t   \"Failed to write profile: section %d, offset %d, info %d\\n\",\n-\t\t\t\t   i, offset, info);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn status;\n-}\n-\n-/**\n- * iavf_rollback_profile\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package to be removed\n- * @track_id: package tracking id\n- *\n- * Rolls back previously loaded package.\n- */\n-enum iavf_status\n-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,\n-\t\t      u32 track_id)\n-{\n-\tstruct iavf_profile_section_header *sec = NULL;\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tstruct iavf_section_table *sec_tbl;\n-\tu32 offset = 0, info = 0;\n-\tu32 section_size = 0;\n-\tu32 sec_off;\n-\tint i;\n-\n-\tstatus = iavf_validate_profile(hw, profile, track_id, true);\n-\tif (status)\n-\t\treturn status;\n-\n-\tIAVF_SECTION_TABLE(profile, sec_tbl);\n-\n-\t/* For rollback write sections in reverse */\n-\tfor (i = sec_tbl->section_count - 1; i >= 0; i--) {\n-\t\tsec_off = sec_tbl->section_offset[i];\n-\t\tsec = IAVF_SECTION_HEADER(profile, sec_off);\n-\n-\t\t/* Skip any non-rollback sections */\n-\t\tif (sec->section.type != SECTION_TYPE_RB_MMIO)\n-\t\t\tcontinue;\n-\n-\t\tsection_size = sec->section.size +\n-\t\t\tsizeof(struct iavf_profile_section_header);\n-\n-\t\t/* Write roll-back MMIO section */\n-\t\tstatus = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,\n-\t\t\t\t\t   track_id, &offset, &info, NULL);\n-\t\tif (status) {\n-\t\t\tiavf_debug(hw, IAVF_DEBUG_PACKAGE,\n-\t\t\t\t   \"Failed to write profile: section %d, offset %d, info %d\\n\",\n-\t\t\t\t   i, offset, info);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn status;\n-}\n-\n-/**\n- * iavf_add_pinfo_to_list\n- * @hw: pointer to the hardware structure\n- * @profile: pointer to the profile segment of the package\n- * @profile_info_sec: buffer for information section\n- * @track_id: package tracking id\n- *\n- * Register a profile to the list of loaded profiles.\n- */\n-enum iavf_status\n-iavf_add_pinfo_to_list(struct iavf_hw *hw,\n-\t\t       struct iavf_profile_segment *profile,\n-\t\t       u8 *profile_info_sec, u32 track_id)\n-{\n-\tenum iavf_status status = IAVF_SUCCESS;\n-\tstruct iavf_profile_section_header *sec = NULL;\n-\tstruct iavf_profile_info *pinfo;\n-\tu32 offset = 0, info = 0;\n-\n-\tsec = (struct iavf_profile_section_header *)profile_info_sec;\n-\tsec->tbl_size = 1;\n-\tsec->data_end = sizeof(struct iavf_profile_section_header) +\n-\t\t\tsizeof(struct iavf_profile_info);\n-\tsec->section.type = SECTION_TYPE_INFO;\n-\tsec->section.offset = sizeof(struct iavf_profile_section_header);\n-\tsec->section.size = sizeof(struct iavf_profile_info);\n-\tpinfo = (struct iavf_profile_info *)(profile_info_sec +\n-\t\t\t\t\t     sec->section.offset);\n-\tpinfo->track_id = track_id;\n-\tpinfo->version = profile->version;\n-\tpinfo->op = IAVF_DDP_ADD_TRACKID;\n-\tiavf_memcpy(pinfo->name, profile->name, IAVF_DDP_NAME_SIZE,\n-\t\t    IAVF_NONDMA_TO_NONDMA);\n-\n-\tstatus = iavf_aq_write_ddp(hw, (void *)sec, sec->data_end,\n-\t\t\t\t   track_id, &offset, &info, NULL);\n-\treturn status;\n-}\ndiff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h\nindex 4b428b8d9..5b61b43d9 100644\n--- a/drivers/net/iavf/base/iavf_prototype.h\n+++ b/drivers/net/iavf/base/iavf_prototype.h\n@@ -61,7 +61,6 @@ enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw,\n const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);\n const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);\n \n-\n enum iavf_status iavf_set_mac_type(struct iavf_hw *hw);\n \n extern struct iavf_rx_ptype_decoded iavf_ptype_lookup[];\n@@ -77,7 +76,6 @@ void iavf_acquire_spinlock(struct iavf_spinlock *sp);\n void iavf_release_spinlock(struct iavf_spinlock *sp);\n void iavf_destroy_spinlock(struct iavf_spinlock *sp);\n \n-/* iavf_common for VF drivers*/\n void iavf_parse_hw_config(struct iavf_hw *hw,\n \t\t\t     struct virtchnl_vf_resource *msg);\n enum iavf_status iavf_reset(struct iavf_hw *hw);\n@@ -86,92 +84,11 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,\n \t\t\t\tenum iavf_status v_retval,\n \t\t\t\tu8 *msg, u16 msglen,\n \t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_set_filter_control(struct iavf_hw *hw,\n-\t\t\t\tstruct iavf_filter_control_settings *settings);\n-enum iavf_status iavf_aq_add_rem_control_packet_filter(struct iavf_hw *hw,\n-\t\t\t\tu8 *mac_addr, u16 ethtype, u16 flags,\n-\t\t\t\tu16 vsi_seid, u16 queue, bool is_add,\n-\t\t\t\tstruct iavf_control_filter_stats *stats,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n enum iavf_status iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,\n \t\t\t\tu8 table_id, u32 start_index, u16 buff_size,\n \t\t\t\tvoid *buff, u16 *ret_buff_size,\n \t\t\t\tu8 *ret_next_table, u32 *ret_next_index,\n \t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-void iavf_add_filter_to_drop_tx_flow_control_frames(struct iavf_hw *hw,\n-\t\t\t\t\t\t    u16 vsi_seid);\n-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr);\n-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val);\n-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 phy_select, u8 dev_addr,\n-\t\t\t\tu32 reg_addr, u32 reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 phy_select, u8 dev_addr,\n-\t\t\t\tu32 reg_addr, u32 *reg_val,\n-\t\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-\n-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,\n-\t\t\tstruct iavf_aqc_arp_proxy_data *proxy_config,\n-\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,\n-\t\t\tstruct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,\n-\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,\n-\t\t\tu8 filter_index,\n-\t\t\tstruct iavf_aqc_set_wol_filter_data *filter,\n-\t\t\tbool set_filter, bool no_wol_tco,\n-\t\t\tbool filter_valid, bool no_wol_tco_valid,\n-\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,\n-\t\t\tu16 *wake_reason,\n-\t\t\tstruct iavf_asq_cmd_details *cmd_details);\n enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,\n \t\t\tstruct iavf_asq_cmd_details *cmd_details);\n-enum iavf_status iavf_read_phy_register_clause22(struct iavf_hw *hw,\n-\t\t\t\t\tu16 reg, u8 phy_addr, u16 *value);\n-enum iavf_status iavf_write_phy_register_clause22(struct iavf_hw *hw,\n-\t\t\t\t\tu16 reg, u8 phy_addr, u16 value);\n-enum iavf_status iavf_read_phy_register_clause45(struct iavf_hw *hw,\n-\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n-enum iavf_status iavf_write_phy_register_clause45(struct iavf_hw *hw,\n-\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n-enum iavf_status iavf_read_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 *value);\n-enum iavf_status iavf_write_phy_register(struct iavf_hw *hw,\n-\t\t\t\tu8 page, u16 reg, u8 phy_addr, u16 value);\n-u8 iavf_get_phy_address(struct iavf_hw *hw, u8 dev_num);\n-enum iavf_status iavf_blink_phy_link_led(struct iavf_hw *hw,\n-\t\t\t\t\t      u32 time, u32 interval);\n-enum iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,\n-\t\t\t\t\tu16 buff_size, u32 track_id,\n-\t\t\t\t\tu32 *error_offset, u32 *error_info,\n-\t\t\t\t\tstruct iavf_asq_cmd_details *\n-\t\t\t\t\tcmd_details);\n-enum iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,\n-\t\t\t\t\t   u16 buff_size, u8 flags,\n-\t\t\t\t\t   struct iavf_asq_cmd_details *\n-\t\t\t\t\t   cmd_details);\n-struct iavf_generic_seg_header *\n-iavf_find_segment_in_package(u32 segment_type,\n-\t\t\t     struct iavf_package_header *pkg_header);\n-struct iavf_profile_section_header *\n-iavf_find_section_in_profile(u32 section_type,\n-\t\t\t     struct iavf_profile_segment *profile);\n-enum iavf_status\n-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,\n-\t\t   u32 track_id);\n-enum iavf_status\n-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,\n-\t\t      u32 track_id);\n-enum iavf_status\n-iavf_add_pinfo_to_list(struct iavf_hw *hw,\n-\t\t       struct iavf_profile_segment *profile,\n-\t\t       u8 *profile_info_sec, u32 track_id);\n #endif /* _IAVF_PROTOTYPE_H_ */\ndiff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h\nindex 4ccde31a2..487352f51 100644\n--- a/drivers/net/iavf/base/iavf_type.h\n+++ b/drivers/net/iavf/base/iavf_type.h\n@@ -29,10 +29,8 @@\n #endif /* BIT_ULL */\n #endif /* LINUX_MACROS */\n \n-#ifndef IAVF_MASK\n /* IAVF_MASK is a macro used on 32 bit registers */\n #define IAVF_MASK(mask, shift) (mask << shift)\n-#endif\n \n #define IAVF_MAX_PF\t\t\t16\n #define IAVF_MAX_PF_VSI\t\t\t64\n@@ -40,16 +38,10 @@\n #define IAVF_MAX_VSI_QP\t\t\t16\n #define IAVF_MAX_VF_VSI\t\t\t3\n #define IAVF_MAX_CHAINED_RX_BUFFERS\t5\n-#define IAVF_MAX_PF_UDP_OFFLOAD_PORTS\t16\n \n /* something less than 1 minute */\n #define IAVF_HEARTBEAT_TIMEOUT\t\t(HZ * 50)\n \n-/* Max default timeout in ms, */\n-#define IAVF_MAX_NVM_TIMEOUT\t\t18000\n-\n-/* Max timeout in ms for the phy to respond */\n-#define IAVF_MAX_PHY_TIMEOUT\t\t500\n \n /* Check whether address is multicast. */\n #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))\n@@ -59,8 +51,6 @@\n \t((((u8 *)(address))[0] == ((u8)0xff)) && \\\n \t(((u8 *)(address))[1] == ((u8)0xff)))\n \n-/* Switch from ms to the 1usec global time (this is the GTIME resolution) */\n-#define IAVF_MS_TO_GTIME(time)\t\t((time) * 1000)\n \n /* forward declaration */\n struct iavf_hw;\n@@ -190,33 +180,6 @@ enum iavf_mac_type {\n \tIAVF_MAC_GENERIC,\n };\n \n-enum iavf_media_type {\n-\tIAVF_MEDIA_TYPE_UNKNOWN = 0,\n-\tIAVF_MEDIA_TYPE_FIBER,\n-\tIAVF_MEDIA_TYPE_BASET,\n-\tIAVF_MEDIA_TYPE_BACKPLANE,\n-\tIAVF_MEDIA_TYPE_CX4,\n-\tIAVF_MEDIA_TYPE_DA,\n-\tIAVF_MEDIA_TYPE_VIRTUAL\n-};\n-\n-enum iavf_fc_mode {\n-\tIAVF_FC_NONE = 0,\n-\tIAVF_FC_RX_PAUSE,\n-\tIAVF_FC_TX_PAUSE,\n-\tIAVF_FC_FULL,\n-\tIAVF_FC_PFC,\n-\tIAVF_FC_DEFAULT\n-};\n-\n-enum iavf_set_fc_aq_failures {\n-\tIAVF_SET_FC_AQ_FAIL_NONE = 0,\n-\tIAVF_SET_FC_AQ_FAIL_GET = 1,\n-\tIAVF_SET_FC_AQ_FAIL_SET = 2,\n-\tIAVF_SET_FC_AQ_FAIL_UPDATE = 4,\n-\tIAVF_SET_FC_AQ_FAIL_SET_UPDATE = 6\n-};\n-\n enum iavf_vsi_type {\n \tIAVF_VSI_MAIN\t= 0,\n \tIAVF_VSI_VMDQ1\t= 1,\n@@ -236,99 +199,6 @@ enum iavf_queue_type {\n \tIAVF_QUEUE_TYPE_UNKNOWN\n };\n \n-struct iavf_link_status {\n-\tenum iavf_aq_phy_type phy_type;\n-\tenum iavf_aq_link_speed link_speed;\n-\tu8 link_info;\n-\tu8 an_info;\n-\tu8 req_fec_info;\n-\tu8 fec_info;\n-\tu8 ext_info;\n-\tu8 loopback;\n-\t/* is Link Status Event notification to SW enabled */\n-\tbool lse_enable;\n-\tu16 max_frame_size;\n-\tbool crc_enable;\n-\tu8 pacing;\n-\tu8 requested_speeds;\n-\tu8 module_type[3];\n-\t/* 1st byte: module identifier */\n-#define IAVF_MODULE_TYPE_SFP\t\t0x03\n-#define IAVF_MODULE_TYPE_QSFP\t\t0x0D\n-\t/* 2nd byte: ethernet compliance codes for 10/40G */\n-#define IAVF_MODULE_TYPE_40G_ACTIVE\t0x01\n-#define IAVF_MODULE_TYPE_40G_LR4\t0x02\n-#define IAVF_MODULE_TYPE_40G_SR4\t0x04\n-#define IAVF_MODULE_TYPE_40G_CR4\t0x08\n-#define IAVF_MODULE_TYPE_10G_BASE_SR\t0x10\n-#define IAVF_MODULE_TYPE_10G_BASE_LR\t0x20\n-#define IAVF_MODULE_TYPE_10G_BASE_LRM\t0x40\n-#define IAVF_MODULE_TYPE_10G_BASE_ER\t0x80\n-\t/* 3rd byte: ethernet compliance codes for 1G */\n-#define IAVF_MODULE_TYPE_1000BASE_SX\t0x01\n-#define IAVF_MODULE_TYPE_1000BASE_LX\t0x02\n-#define IAVF_MODULE_TYPE_1000BASE_CX\t0x04\n-#define IAVF_MODULE_TYPE_1000BASE_T\t0x08\n-};\n-\n-struct iavf_phy_info {\n-\tstruct iavf_link_status link_info;\n-\tstruct iavf_link_status link_info_old;\n-\tbool get_link_info;\n-\tenum iavf_media_type media_type;\n-\t/* all the phy types the NVM is capable of */\n-\tu64 phy_types;\n-};\n-\n-#define IAVF_CAP_PHY_TYPE_SGMII BIT_ULL(IAVF_PHY_TYPE_SGMII)\n-#define IAVF_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(IAVF_PHY_TYPE_1000BASE_KX)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(IAVF_PHY_TYPE_10GBASE_KX4)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(IAVF_PHY_TYPE_10GBASE_KR)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_KR4)\n-#define IAVF_CAP_PHY_TYPE_XAUI BIT_ULL(IAVF_PHY_TYPE_XAUI)\n-#define IAVF_CAP_PHY_TYPE_XFI BIT_ULL(IAVF_PHY_TYPE_XFI)\n-#define IAVF_CAP_PHY_TYPE_SFI BIT_ULL(IAVF_PHY_TYPE_SFI)\n-#define IAVF_CAP_PHY_TYPE_XLAUI BIT_ULL(IAVF_PHY_TYPE_XLAUI)\n-#define IAVF_CAP_PHY_TYPE_XLPPI BIT_ULL(IAVF_PHY_TYPE_XLPPI)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4_CU)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1_CU)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_10GBASE_AOC)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_40GBASE_AOC)\n-#define IAVF_CAP_PHY_TYPE_100BASE_TX BIT_ULL(IAVF_PHY_TYPE_100BASE_TX)\n-#define IAVF_CAP_PHY_TYPE_1000BASE_T BIT_ULL(IAVF_PHY_TYPE_1000BASE_T)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_T BIT_ULL(IAVF_PHY_TYPE_10GBASE_T)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(IAVF_PHY_TYPE_10GBASE_SR)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(IAVF_PHY_TYPE_10GBASE_LR)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_SFPP_CU)\n-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_SR4)\n-#define IAVF_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_LR4)\n-#define IAVF_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(IAVF_PHY_TYPE_1000BASE_SX)\n-#define IAVF_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(IAVF_PHY_TYPE_1000BASE_LX)\n-#define IAVF_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n-\t\t\t\tBIT_ULL(IAVF_PHY_TYPE_1000BASE_T_OPTICAL)\n-#define IAVF_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(IAVF_PHY_TYPE_20GBASE_KR2)\n-/*\n- * Defining the macro IAVF_TYPE_OFFSET to implement a bit shift for some\n- * PHY types. There is an unused bit (31) in the IAVF_CAP_PHY_TYPE_* bit\n- * fields but no corresponding gap in the iavf_aq_phy_type enumeration. So,\n- * a shift is needed to adjust for this with values larger than 31. The\n- * only affected values are IAVF_PHY_TYPE_25GBASE_*.\n- */\n-#define IAVF_PHY_TYPE_OFFSET 1\n-#define IAVF_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(IAVF_PHY_TYPE_25GBASE_KR + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n-#define IAVF_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(IAVF_PHY_TYPE_25GBASE_CR + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n-#define IAVF_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(IAVF_PHY_TYPE_25GBASE_SR + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n-#define IAVF_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(IAVF_PHY_TYPE_25GBASE_LR + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n-#define IAVF_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_25GBASE_AOC + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n-#define IAVF_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(IAVF_PHY_TYPE_25GBASE_ACC + \\\n-\t\t\t\t\t     IAVF_PHY_TYPE_OFFSET)\n #define IAVF_HW_CAP_MAX_GPIO\t\t\t30\n #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO\t\t0\n #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C\t\t1\n@@ -344,71 +214,24 @@ enum iavf_acpi_programming_method {\n \n /* Capabilities of a PF or a VF or the whole device */\n struct iavf_hw_capabilities {\n-\tu32  switch_mode;\n-#define IAVF_NVM_IMAGE_TYPE_EVB\t\t0x0\n-#define IAVF_NVM_IMAGE_TYPE_CLOUD\t0x2\n-#define IAVF_NVM_IMAGE_TYPE_UDP_CLOUD\t0x3\n-\n-\tu32  management_mode;\n-\tu32  mng_protocols_over_mctp;\n-#define IAVF_MNG_PROTOCOL_PLDM\t\t0x2\n-#define IAVF_MNG_PROTOCOL_OEM_COMMANDS\t0x4\n-#define IAVF_MNG_PROTOCOL_NCSI\t\t0x8\n-\tu32  npar_enable;\n-\tu32  os2bmc;\n-\tu32  valid_functions;\n-\tbool sr_iov_1_1;\n-\tbool vmdq;\n-\tbool evb_802_1_qbg; /* Edge Virtual Bridging */\n-\tbool evb_802_1_qbh; /* Bridge Port Extension */\n+\t/* Cloud filter modes:\n+\t * Mode1: Filter on L4 port only\n+\t * Mode2: Filter for non-tunneled traffic\n+\t * Mode3: Filter for tunnel traffic\n+\t */\n+#define IAVF_CLOUD_FILTER_MODE1\t0x6\n+#define IAVF_CLOUD_FILTER_MODE2\t0x7\n+#define IAVF_CLOUD_FILTER_MODE3\t0x8\n+#define IAVF_SWITCH_MODE_MASK\t0xF\n+\n \tbool dcb;\n \tbool fcoe;\n-\tbool iscsi; /* Indicates iSCSI enabled */\n-\tbool flex10_enable;\n-\tbool flex10_capable;\n-\tu32  flex10_mode;\n-#define IAVF_FLEX10_MODE_UNKNOWN\t0x0\n-#define IAVF_FLEX10_MODE_DCC\t\t0x1\n-#define IAVF_FLEX10_MODE_DCI\t\t0x2\n-\n-\tu32 flex10_status;\n-#define IAVF_FLEX10_STATUS_DCC_ERROR\t0x1\n-#define IAVF_FLEX10_STATUS_VC_MODE\t0x2\n-\n-\tbool sec_rev_disabled;\n-\tbool update_disabled;\n-#define IAVF_NVM_MGMT_SEC_REV_DISABLED\t0x1\n-#define IAVF_NVM_MGMT_UPDATE_DISABLED\t0x2\n-\n-\tbool mgmt_cem;\n-\tbool ieee_1588;\n \tbool iwarp;\n-\tbool fd;\n-\tu32 fd_filters_guaranteed;\n-\tu32 fd_filters_best_effort;\n-\tbool rss;\n-\tu32 rss_table_size;\n-\tu32 rss_table_entry_width;\n-\tbool led[IAVF_HW_CAP_MAX_GPIO];\n-\tbool sdp[IAVF_HW_CAP_MAX_GPIO];\n-\tu32 nvm_image_type;\n-\tu32 num_flow_director_filters;\n-\tu32 num_vfs;\n-\tu32 vf_base_id;\n \tu32 num_vsis;\n \tu32 num_rx_qp;\n \tu32 num_tx_qp;\n \tu32 base_queue;\n-\tu32 num_msix_vectors;\n \tu32 num_msix_vectors_vf;\n-\tu32 led_pin_num;\n-\tu32 sdp_pin_num;\n-\tu32 mdio_port_num;\n-\tu32 mdio_port_mode;\n-\tu8 rx_buf_chain_len;\n-\tu32 enabled_tcmap;\n-\tu32 maxtc;\n-\tu64 wr_csr_prot;\n \tbool apm_wol_support;\n \tenum iavf_acpi_programming_method acpi_prog_method;\n \tbool proxy_support;\n@@ -423,107 +246,25 @@ struct iavf_mac_info {\n \tu16 max_fcoeq;\n };\n \n-enum iavf_aq_resources_ids {\n-\tIAVF_NVM_RESOURCE_ID = 1\n-};\n-\n-enum iavf_aq_resource_access_type {\n-\tIAVF_RESOURCE_READ = 1,\n-\tIAVF_RESOURCE_WRITE\n-};\n+#define IAVF_NVM_EXEC_GET_AQ_RESULT\t\t0x0\n+#define IAVF_NVM_EXEC_FEATURES\t\t\t0xe\n+#define IAVF_NVM_EXEC_STATUS\t\t\t0xf\n \n-struct iavf_nvm_info {\n-\tu64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */\n-\tu32 timeout;              /* [ms] */\n-\tu16 sr_size;              /* Shadow RAM size in words */\n-\tbool blank_nvm_mode;      /* is NVM empty (no FW present)*/\n-\tu16 version;              /* NVM package version */\n-\tu32 eetrack;              /* NVM data version */\n-\tu32 oem_ver;              /* OEM version info */\n-};\n+/* NVMUpdate features API */\n+#define IAVF_NVMUPD_FEATURES_API_VER_MAJOR\t\t0\n+#define IAVF_NVMUPD_FEATURES_API_VER_MINOR\t\t14\n+#define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN\t12\n \n-/* definitions used in NVM update support */\n-\n-enum iavf_nvmupd_cmd {\n-\tIAVF_NVMUPD_INVALID,\n-\tIAVF_NVMUPD_READ_CON,\n-\tIAVF_NVMUPD_READ_SNT,\n-\tIAVF_NVMUPD_READ_LCB,\n-\tIAVF_NVMUPD_READ_SA,\n-\tIAVF_NVMUPD_WRITE_ERA,\n-\tIAVF_NVMUPD_WRITE_CON,\n-\tIAVF_NVMUPD_WRITE_SNT,\n-\tIAVF_NVMUPD_WRITE_LCB,\n-\tIAVF_NVMUPD_WRITE_SA,\n-\tIAVF_NVMUPD_CSUM_CON,\n-\tIAVF_NVMUPD_CSUM_SA,\n-\tIAVF_NVMUPD_CSUM_LCB,\n-\tIAVF_NVMUPD_STATUS,\n-\tIAVF_NVMUPD_EXEC_AQ,\n-\tIAVF_NVMUPD_GET_AQ_RESULT,\n-\tIAVF_NVMUPD_GET_AQ_EVENT,\n-};\n-\n-enum iavf_nvmupd_state {\n-\tIAVF_NVMUPD_STATE_INIT,\n-\tIAVF_NVMUPD_STATE_READING,\n-\tIAVF_NVMUPD_STATE_WRITING,\n-\tIAVF_NVMUPD_STATE_INIT_WAIT,\n-\tIAVF_NVMUPD_STATE_WRITE_WAIT,\n-\tIAVF_NVMUPD_STATE_ERROR\n-};\n+#define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT\t\tBIT(0)\n \n-/* nvm_access definition and its masks/shifts need to be accessible to\n- * application, core driver, and shared code.  Where is the right file?\n- */\n-#define IAVF_NVM_READ\t0xB\n-#define IAVF_NVM_WRITE\t0xC\n-\n-#define IAVF_NVM_MOD_PNT_MASK 0xFF\n-\n-#define IAVF_NVM_TRANS_SHIFT\t\t\t8\n-#define IAVF_NVM_TRANS_MASK\t\t\t(0xf << IAVF_NVM_TRANS_SHIFT)\n-#define IAVF_NVM_PRESERVATION_FLAGS_SHIFT\t12\n-#define IAVF_NVM_PRESERVATION_FLAGS_MASK \\\n-\t\t\t\t(0x3 << IAVF_NVM_PRESERVATION_FLAGS_SHIFT)\n-#define IAVF_NVM_PRESERVATION_FLAGS_SELECTED\t0x01\n-#define IAVF_NVM_PRESERVATION_FLAGS_ALL\t\t0x02\n-#define IAVF_NVM_CON\t\t\t\t0x0\n-#define IAVF_NVM_SNT\t\t\t\t0x1\n-#define IAVF_NVM_LCB\t\t\t\t0x2\n-#define IAVF_NVM_SA\t\t\t\t(IAVF_NVM_SNT | IAVF_NVM_LCB)\n-#define IAVF_NVM_ERA\t\t\t\t0x4\n-#define IAVF_NVM_CSUM\t\t\t\t0x8\n-#define IAVF_NVM_AQE\t\t\t\t0xe\n-#define IAVF_NVM_EXEC\t\t\t\t0xf\n-\n-#define IAVF_NVM_ADAPT_SHIFT\t16\n-#define IAVF_NVM_ADAPT_MASK\t(0xffffULL << IAVF_NVM_ADAPT_SHIFT)\n-\n-#define IAVF_NVMUPD_MAX_DATA\t4096\n-#define IAVF_NVMUPD_IFACE_TIMEOUT 2 /* seconds */\n-\n-struct iavf_nvm_access {\n-\tu32 command;\n-\tu32 config;\n-\tu32 offset;\t/* in bytes */\n-\tu32 data_size;\t/* in bytes */\n-\tu8 data[1];\n+struct iavf_nvmupd_features {\n+\tu8 major;\n+\tu8 minor;\n+\tu16 size;\n+\tu8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];\n };\n \n-/* (Q)SFP module access definitions */\n-#define IAVF_I2C_EEPROM_DEV_ADDR\t0xA0\n-#define IAVF_I2C_EEPROM_DEV_ADDR2\t0xA2\n-#define IAVF_MODULE_TYPE_ADDR\t\t0x00\n-#define IAVF_MODULE_REVISION_ADDR\t0x01\n-#define IAVF_MODULE_SFF_8472_COMP\t0x5E\n-#define IAVF_MODULE_SFF_8472_SWAP\t0x5C\n-#define IAVF_MODULE_SFF_ADDR_MODE\t0x04\n #define IAVF_MODULE_SFF_DIAG_CAPAB\t0x40\n-#define IAVF_MODULE_TYPE_QSFP_PLUS\t0x0D\n-#define IAVF_MODULE_TYPE_QSFP28\t\t0x11\n-#define IAVF_MODULE_QSFP_MAX_LEN\t640\n-\n /* PCI bus types */\n enum iavf_bus_type {\n \tiavf_bus_type_unknown = 0,\n@@ -571,16 +312,7 @@ struct iavf_bus_info {\n \tu16 bus_id;\n };\n \n-/* Flow control (FC) parameters */\n-struct iavf_fc_info {\n-\tenum iavf_fc_mode current_mode; /* FC mode in effect */\n-\tenum iavf_fc_mode requested_mode; /* FC mode requested by caller */\n-};\n-\n-#define IAVF_MAX_TRAFFIC_CLASS\t\t8\n #define IAVF_MAX_USER_PRIORITY\t\t8\n-#define IAVF_DCBX_MAX_APPS\t\t32\n-#define IAVF_LLDPDU_SIZE\t\t1500\n #define IAVF_TLV_STATUS_OPER\t\t0x1\n #define IAVF_TLV_STATUS_SYNC\t\t0x2\n #define IAVF_TLV_STATUS_ERR\t\t0x4\n@@ -593,56 +325,14 @@ struct iavf_fc_info {\n #define IAVF_CEE_APP_SEL_ETHTYPE\t0x0\n #define IAVF_CEE_APP_SEL_TCPIP\t\t0x1\n \n-/* CEE or IEEE 802.1Qaz ETS Configuration data */\n-struct iavf_dcb_ets_config {\n-\tu8 willing;\n-\tu8 cbs;\n-\tu8 maxtcs;\n-\tu8 prioritytable[IAVF_MAX_TRAFFIC_CLASS];\n-\tu8 tcbwtable[IAVF_MAX_TRAFFIC_CLASS];\n-\tu8 tsatable[IAVF_MAX_TRAFFIC_CLASS];\n-};\n-\n-/* CEE or IEEE 802.1Qaz PFC Configuration data */\n-struct iavf_dcb_pfc_config {\n-\tu8 willing;\n-\tu8 mbc;\n-\tu8 pfccap;\n-\tu8 pfcenable;\n-};\n-\n-/* CEE or IEEE 802.1Qaz Application Priority data */\n-struct iavf_dcb_app_priority_table {\n-\tu8  priority;\n-\tu8  selector;\n-\tu16 protocolid;\n-};\n-\n-struct iavf_dcbx_config {\n-\tu8  dcbx_mode;\n-#define IAVF_DCBX_MODE_CEE\t0x1\n-#define IAVF_DCBX_MODE_IEEE\t0x2\n-\tu8  app_mode;\n-#define IAVF_DCBX_APPS_NON_WILLING\t0x1\n-\tu32 numapps;\n-\tu32 tlv_status; /* CEE mode TLV status */\n-\tstruct iavf_dcb_ets_config etscfg;\n-\tstruct iavf_dcb_ets_config etsrec;\n-\tstruct iavf_dcb_pfc_config pfc;\n-\tstruct iavf_dcb_app_priority_table app[IAVF_DCBX_MAX_APPS];\n-};\n-\n /* Port hardware description */\n struct iavf_hw {\n \tu8 *hw_addr;\n \tvoid *back;\n \n \t/* subsystem structs */\n-\tstruct iavf_phy_info phy;\n \tstruct iavf_mac_info mac;\n \tstruct iavf_bus_info bus;\n-\tstruct iavf_nvm_info nvm;\n-\tstruct iavf_fc_info fc;\n \n \t/* pci info */\n \tu16 device_id;\n@@ -650,47 +340,14 @@ struct iavf_hw {\n \tu16 subsystem_device_id;\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n-\tu8 port;\n \tbool adapter_stopped;\n \n \t/* capabilities for entire device and PCI func */\n \tstruct iavf_hw_capabilities dev_caps;\n-\tstruct iavf_hw_capabilities func_caps;\n-\n-\t/* Flow Director shared filter space */\n-\tu16 fdir_shared_filter_count;\n-\n-\t/* device profile info */\n-\tu8  pf_id;\n-\tu16 main_vsi_seid;\n-\n-\t/* for multi-function MACs */\n-\tu16 partition_id;\n-\tu16 num_partitions;\n-\tu16 num_ports;\n-\n-\t/* Closest numa node to the device */\n-\tu16 numa_node;\n \n \t/* Admin Queue info */\n \tstruct iavf_adminq_info aq;\n \n-\t/* state of nvm update process */\n-\tenum iavf_nvmupd_state nvmupd_state;\n-\tstruct iavf_aq_desc nvm_wb_desc;\n-\tstruct iavf_aq_desc nvm_aq_event_desc;\n-\tstruct iavf_virt_mem nvm_buff;\n-\tbool nvm_release_on_done;\n-\tu16 nvm_wait_opcode;\n-\n-\t/* LLDP/DCBX Status */\n-\tu16 dcbx_status;\n-\n-\t/* DCBX info */\n-\tstruct iavf_dcbx_config local_dcbx_config; /* Oper/Local Cfg */\n-\tstruct iavf_dcbx_config remote_dcbx_config; /* Peer Cfg */\n-\tstruct iavf_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */\n-\n \t/* WoL and proxy support */\n \tu16 num_wol_proxy_filters;\n \tu16 wol_proxy_vsi_seid;\n@@ -699,24 +356,17 @@ struct iavf_hw {\n #define IAVF_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)\n #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)\n #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)\n+#define IAVF_HW_FLAG_FW_LLDP_STOPPABLE\t    BIT_ULL(4)\n \tu64 flags;\n \n-\t/* Used in set switch config AQ command */\n-\tu16 switch_tag;\n-\tu16 first_tag;\n-\tu16 second_tag;\n+\t/* NVMUpdate features */\n+\tstruct iavf_nvmupd_features nvmupd_features;\n \n \t/* debug mask */\n \tu32 debug_mask;\n \tchar err_str[16];\n };\n \n-STATIC INLINE bool iavf_is_vf(struct iavf_hw *hw)\n-{\n-\treturn (hw->mac.type == IAVF_MAC_VF ||\n-\t\thw->mac.type == IAVF_MAC_X722_VF);\n-}\n-\n struct iavf_driver_version {\n \tu8 major_version;\n \tu8 minor_version;\n@@ -1159,53 +809,6 @@ enum iavf_tx_ctx_desc_cmd_bits {\n \tIAVF_TX_CTX_DESC_SWPE\t\t= 0x40\n };\n \n-#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT\t30\n-#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK\t(0x3FFFFULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW1_MSS_SHIFT\t50\n-#define IAVF_TXD_CTX_QW1_MSS_MASK\t(0x3FFFULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW1_MSS_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW1_VSI_SHIFT\t50\n-#define IAVF_TXD_CTX_QW1_VSI_MASK\t(0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT\t0\n-#define IAVF_TXD_CTX_QW0_EXT_IP_MASK\t(0x3ULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)\n-\n-enum iavf_tx_ctx_desc_eipt_offload {\n-\tIAVF_TX_CTX_EXT_IP_NONE\t\t= 0x0,\n-\tIAVF_TX_CTX_EXT_IP_IPV6\t\t= 0x1,\n-\tIAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM\t= 0x2,\n-\tIAVF_TX_CTX_EXT_IP_IPV4\t\t= 0x3\n-};\n-\n-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT\t2\n-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK\t(0x3FULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW0_NATT_SHIFT\t9\n-#define IAVF_TXD_CTX_QW0_NATT_MASK\t(0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)\n-\n-#define IAVF_TXD_CTX_UDP_TUNNELING\tBIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)\n-#define IAVF_TXD_CTX_GRE_TUNNELING\t(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT\t11\n-#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK\tBIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n-\n-#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST\tIAVF_TXD_CTX_QW0_EIP_NOINC_MASK\n-\n-#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT\t12\n-#define IAVF_TXD_CTX_QW0_NATLEN_MASK\t(0X7FULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW0_NATLEN_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT\t19\n-#define IAVF_TXD_CTX_QW0_DECTTL_MASK\t(0xFULL << \\\n-\t\t\t\t\t IAVF_TXD_CTX_QW0_DECTTL_SHIFT)\n-\n-#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT\t23\n-#define IAVF_TXD_CTX_QW0_L4T_CS_MASK\tBIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)\n struct iavf_nop_desc {\n \t__le64 rsvd;\n \t__le64 dtype_cmd;\n@@ -1224,22 +827,6 @@ enum iavf_tx_nop_desc_cmd_bits {\n \tIAVF_TX_NOP_DESC_RSV_SHIFT\t= 2 /* 5 bits */\n };\n \n-struct iavf_filter_program_desc {\n-\t__le32 qindex_flex_ptype_vsi;\n-\t__le32 rsvd;\n-\t__le32 dtype_cmd_cntindex;\n-\t__le32 fd_id;\n-};\n-#define IAVF_TXD_FLTR_QW0_QINDEX_SHIFT\t0\n-#define IAVF_TXD_FLTR_QW0_QINDEX_MASK\t(0x7FFUL << \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW0_QINDEX_SHIFT)\n-#define IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT\t11\n-#define IAVF_TXD_FLTR_QW0_FLEXOFF_MASK\t(0x7UL << \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT)\n-#define IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT\t17\n-#define IAVF_TXD_FLTR_QW0_PCTYPE_MASK\t(0x3FUL << \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT)\n-\n /* Packet Classifier Types for filters */\n enum iavf_filter_pctype {\n \t/* Note: Values 0-28 are reserved for future use.\n@@ -1272,88 +859,61 @@ enum iavf_filter_pctype {\n \tIAVF_FILTER_PCTYPE_L2_PAYLOAD\t\t\t= 63,\n };\n \n-enum iavf_filter_program_desc_dest {\n-\tIAVF_FILTER_PROGRAM_DESC_DEST_DROP_PACKET\t\t= 0x0,\n-\tIAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX\t= 0x1,\n-\tIAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER\t= 0x2,\n-};\n-\n-enum iavf_filter_program_desc_fd_status {\n-\tIAVF_FILTER_PROGRAM_DESC_FD_STATUS_NONE\t\t\t= 0x0,\n-\tIAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID\t\t= 0x1,\n-\tIAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES\t= 0x2,\n-\tIAVF_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES\t\t= 0x3,\n-};\n-\n-#define IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT\t23\n-#define IAVF_TXD_FLTR_QW0_DEST_VSI_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n-\n #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT\t0\n #define IAVF_TXD_FLTR_QW1_DTYPE_MASK\t(0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_CMD_SHIFT\t4\n-#define IAVF_TXD_FLTR_QW1_CMD_MASK\t(0xFFFFULL << \\\n+#define IAVF_TXD_FLTR_QW1_ATR_SHIFT\t(0xEULL + \\\n \t\t\t\t\t IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n+#define IAVF_TXD_FLTR_QW1_ATR_MASK\tBIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_PCMD_SHIFT\t(0x0ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n-#define IAVF_TXD_FLTR_QW1_PCMD_MASK\t(0x7ULL << IAVF_TXD_FLTR_QW1_PCMD_SHIFT)\n \n-enum iavf_filter_program_desc_pcmd {\n-\tIAVF_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE\t= 0x1,\n-\tIAVF_FILTER_PROGRAM_DESC_PCMD_REMOVE\t\t= 0x2,\n+#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT\t30\n+#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK\t(0x3FFFFULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_MSS_SHIFT\t50\n+#define IAVF_TXD_CTX_QW1_MSS_MASK\t(0x3FFFULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW1_MSS_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW1_VSI_SHIFT\t50\n+#define IAVF_TXD_CTX_QW1_VSI_MASK\t(0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT\t0\n+#define IAVF_TXD_CTX_QW0_EXT_IP_MASK\t(0x3ULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)\n+\n+enum iavf_tx_ctx_desc_eipt_offload {\n+\tIAVF_TX_CTX_EXT_IP_NONE\t\t= 0x0,\n+\tIAVF_TX_CTX_EXT_IP_IPV6\t\t= 0x1,\n+\tIAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM\t= 0x2,\n+\tIAVF_TX_CTX_EXT_IP_IPV4\t\t= 0x3\n };\n \n-#define IAVF_TXD_FLTR_QW1_DEST_SHIFT\t(0x3ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n-#define IAVF_TXD_FLTR_QW1_DEST_MASK\t(0x3ULL << IAVF_TXD_FLTR_QW1_DEST_SHIFT)\n+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT\t2\n+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK\t(0x3FULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT\t(0x7ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n-#define IAVF_TXD_FLTR_QW1_CNT_ENA_MASK\tBIT_ULL(IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n+#define IAVF_TXD_CTX_QW0_NATT_SHIFT\t9\n+#define IAVF_TXD_CTX_QW0_NATT_MASK\t(0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT\t(0x9ULL + \\\n-\t\t\t\t\t\t IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n-#define IAVF_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \\\n-\t\t\t\t\t  IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT)\n+#define IAVF_TXD_CTX_UDP_TUNNELING\tBIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)\n+#define IAVF_TXD_CTX_GRE_TUNNELING\t(0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_ATR_SHIFT\t(0xEULL + \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW1_CMD_SHIFT)\n-#define IAVF_TXD_FLTR_QW1_ATR_MASK\tBIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)\n+#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT\t11\n+#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK\tBIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n \n-#define IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT 20\n-#define IAVF_TXD_FLTR_QW1_CNTINDEX_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT)\n-\n-enum iavf_filter_type {\n-\tIAVF_FLOW_DIRECTOR_FLTR = 0,\n-\tIAVF_PE_QUAD_HASH_FLTR = 1,\n-\tIAVF_ETHERTYPE_FLTR,\n-\tIAVF_FCOE_CTX_FLTR,\n-\tIAVF_MAC_VLAN_FLTR,\n-\tIAVF_HASH_FLTR\n-};\n+#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST\tIAVF_TXD_CTX_QW0_EIP_NOINC_MASK\n \n-struct iavf_vsi_context {\n-\tu16 seid;\n-\tu16 uplink_seid;\n-\tu16 vsi_number;\n-\tu16 vsis_allocated;\n-\tu16 vsis_unallocated;\n-\tu16 flags;\n-\tu8 pf_num;\n-\tu8 vf_num;\n-\tu8 connection_type;\n-\tstruct iavf_aqc_vsi_properties_data info;\n-};\n+#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT\t12\n+#define IAVF_TXD_CTX_QW0_NATLEN_MASK\t(0X7FULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW0_NATLEN_SHIFT)\n \n-struct iavf_veb_context {\n-\tu16 seid;\n-\tu16 uplink_seid;\n-\tu16 veb_number;\n-\tu16 vebs_allocated;\n-\tu16 vebs_unallocated;\n-\tu16 flags;\n-\tstruct iavf_aqc_get_veb_parameters_completion info;\n-};\n+#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT\t19\n+#define IAVF_TXD_CTX_QW0_DECTTL_MASK\t(0xFULL << \\\n+\t\t\t\t\t IAVF_TXD_CTX_QW0_DECTTL_SHIFT)\n+\n+#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT\t23\n+#define IAVF_TXD_CTX_QW0_L4T_CS_MASK\tBIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)\n \n /* Statistics collected by each port, VSI, VEB, and S-channel */\n struct iavf_eth_stats {\n@@ -1370,89 +930,6 @@ struct iavf_eth_stats {\n \tu64 tx_discards;\t\t/* tdpc */\n \tu64 tx_errors;\t\t\t/* tepc */\n };\n-\n-/* Statistics collected per VEB per TC */\n-struct iavf_veb_tc_stats {\n-\tu64 tc_rx_packets[IAVF_MAX_TRAFFIC_CLASS];\n-\tu64 tc_rx_bytes[IAVF_MAX_TRAFFIC_CLASS];\n-\tu64 tc_tx_packets[IAVF_MAX_TRAFFIC_CLASS];\n-\tu64 tc_tx_bytes[IAVF_MAX_TRAFFIC_CLASS];\n-};\n-\n-/* Statistics collected per function for FCoE */\n-struct iavf_fcoe_stats {\n-\tu64 rx_fcoe_packets;\t\t/* fcoeprc */\n-\tu64 rx_fcoe_dwords;\t\t/* focedwrc */\n-\tu64 rx_fcoe_dropped;\t\t/* fcoerpdc */\n-\tu64 tx_fcoe_packets;\t\t/* fcoeptc */\n-\tu64 tx_fcoe_dwords;\t\t/* focedwtc */\n-\tu64 fcoe_bad_fccrc;\t\t/* fcoecrc */\n-\tu64 fcoe_last_error;\t\t/* fcoelast */\n-\tu64 fcoe_ddp_count;\t\t/* fcoeddpc */\n-};\n-\n-/* offset to per function FCoE statistics block */\n-#define IAVF_FCOE_VF_STAT_OFFSET\t0\n-#define IAVF_FCOE_PF_STAT_OFFSET\t128\n-#define IAVF_FCOE_STAT_MAX\t\t(IAVF_FCOE_PF_STAT_OFFSET + IAVF_MAX_PF)\n-\n-/* Statistics collected by the MAC */\n-struct iavf_hw_port_stats {\n-\t/* eth stats collected by the port */\n-\tstruct iavf_eth_stats eth;\n-\n-\t/* additional port specific stats */\n-\tu64 tx_dropped_link_down;\t/* tdold */\n-\tu64 crc_errors;\t\t\t/* crcerrs */\n-\tu64 illegal_bytes;\t\t/* illerrc */\n-\tu64 error_bytes;\t\t/* errbc */\n-\tu64 mac_local_faults;\t\t/* mlfc */\n-\tu64 mac_remote_faults;\t\t/* mrfc */\n-\tu64 rx_length_errors;\t\t/* rlec */\n-\tu64 link_xon_rx;\t\t/* lxonrxc */\n-\tu64 link_xoff_rx;\t\t/* lxoffrxc */\n-\tu64 priority_xon_rx[8];\t\t/* pxonrxc[8] */\n-\tu64 priority_xoff_rx[8];\t/* pxoffrxc[8] */\n-\tu64 link_xon_tx;\t\t/* lxontxc */\n-\tu64 link_xoff_tx;\t\t/* lxofftxc */\n-\tu64 priority_xon_tx[8];\t\t/* pxontxc[8] */\n-\tu64 priority_xoff_tx[8];\t/* pxofftxc[8] */\n-\tu64 priority_xon_2_xoff[8];\t/* pxon2offc[8] */\n-\tu64 rx_size_64;\t\t\t/* prc64 */\n-\tu64 rx_size_127;\t\t/* prc127 */\n-\tu64 rx_size_255;\t\t/* prc255 */\n-\tu64 rx_size_511;\t\t/* prc511 */\n-\tu64 rx_size_1023;\t\t/* prc1023 */\n-\tu64 rx_size_1522;\t\t/* prc1522 */\n-\tu64 rx_size_big;\t\t/* prc9522 */\n-\tu64 rx_undersize;\t\t/* ruc */\n-\tu64 rx_fragments;\t\t/* rfc */\n-\tu64 rx_oversize;\t\t/* roc */\n-\tu64 rx_jabber;\t\t\t/* rjc */\n-\tu64 tx_size_64;\t\t\t/* ptc64 */\n-\tu64 tx_size_127;\t\t/* ptc127 */\n-\tu64 tx_size_255;\t\t/* ptc255 */\n-\tu64 tx_size_511;\t\t/* ptc511 */\n-\tu64 tx_size_1023;\t\t/* ptc1023 */\n-\tu64 tx_size_1522;\t\t/* ptc1522 */\n-\tu64 tx_size_big;\t\t/* ptc9522 */\n-\tu64 mac_short_packet_dropped;\t/* mspdc */\n-\tu64 checksum_error;\t\t/* xec */\n-\t/* flow director stats */\n-\tu64 fd_atr_match;\n-\tu64 fd_sb_match;\n-\tu64 fd_atr_tunnel_match;\n-\tu32 fd_atr_status;\n-\tu32 fd_sb_status;\n-\t/* EEE LPI */\n-\tu32 tx_lpi_status;\n-\tu32 rx_lpi_status;\n-\tu64 tx_lpi_count;\t\t/* etlpic */\n-\tu64 rx_lpi_count;\t\t/* erlpic */\n-};\n-\n-/* Checksum and Shadow RAM pointers */\n-#define IAVF_SR_NVM_CONTROL_WORD\t\t0x00\n #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR\t\t0x03\n #define IAVF_SR_PHY_ANALOG_CONFIG_PTR\t\t0x04\n #define IAVF_SR_OPTION_ROM_PTR\t\t\t0x05\n@@ -1465,22 +942,13 @@ struct iavf_hw_port_stats {\n #define IAVF_SR_PE_IMAGE_PTR\t\t\t0x0C\n #define IAVF_SR_CSR_PROTECTED_LIST_PTR\t\t0x0D\n #define IAVF_SR_MNG_CONFIG_PTR\t\t\t0x0E\n-#define IAVF_EMP_MODULE_PTR\t\t\t0x0F\n-#define IAVF_SR_EMP_MODULE_PTR\t\t\t0x48\n #define IAVF_SR_PBA_FLAGS\t\t\t0x15\n #define IAVF_SR_PBA_BLOCK_PTR\t\t\t0x16\n #define IAVF_SR_BOOT_CONFIG_PTR\t\t\t0x17\n-#define IAVF_NVM_OEM_VER_OFF\t\t\t0x83\n-#define IAVF_SR_NVM_DEV_STARTER_VERSION\t\t0x18\n-#define IAVF_SR_NVM_WAKE_ON_LAN\t\t\t0x19\n-#define IAVF_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR\t0x27\n #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR\t0x28\n #define IAVF_SR_NVM_MAP_VERSION\t\t\t0x29\n #define IAVF_SR_NVM_IMAGE_VERSION\t\t0x2A\n #define IAVF_SR_NVM_STRUCTURE_VERSION\t\t0x2B\n-#define IAVF_SR_NVM_EETRACK_LO\t\t\t0x2D\n-#define IAVF_SR_NVM_EETRACK_HI\t\t\t0x2E\n-#define IAVF_SR_VPD_PTR\t\t\t\t0x2F\n #define IAVF_SR_PXE_SETUP_PTR\t\t\t0x30\n #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR\t0x31\n #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO\t\t0x34\n@@ -1491,8 +959,6 @@ struct iavf_hw_port_stats {\n #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR\t0x3B\n #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR\t0x3C\n #define IAVF_SR_PHY_ACTIVITY_LIST_PTR\t\t0x3D\n-#define IAVF_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n-#define IAVF_SR_SW_CHECKSUM_WORD\t\t0x3F\n #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR\t0x40\n #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR\t0x42\n #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR\t0x44\n@@ -1501,334 +967,11 @@ struct iavf_hw_port_stats {\n #define IAVF_SR_FEATURE_CONFIGURATION_PTR\t0x49\n #define IAVF_SR_CONFIGURATION_METADATA_PTR\t0x4D\n #define IAVF_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n-\n-/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n-#define IAVF_SR_VPD_MODULE_MAX_SIZE\t\t1024\n-#define IAVF_SR_PCIE_ALT_MODULE_MAX_SIZE\t1024\n-#define IAVF_SR_CONTROL_WORD_1_SHIFT\t\t0x06\n-#define IAVF_SR_CONTROL_WORD_1_MASK\t(0x03 << IAVF_SR_CONTROL_WORD_1_SHIFT)\n-#define IAVF_SR_CONTROL_WORD_1_NVM_BANK_VALID\tBIT(5)\n-#define IAVF_SR_NVM_MAP_STRUCTURE_TYPE\t\tBIT(12)\n-#define IAVF_PTR_TYPE                           BIT(15)\n-\n-/* Shadow RAM related */\n-#define IAVF_SR_SECTOR_SIZE_IN_WORDS\t0x800\n+#define IAVF_SR_OCP_CFG_WORD0\t\t\t0x2B\n+#define IAVF_SR_OCP_ENABLED\t\t\tBIT(15)\n #define IAVF_SR_BUF_ALIGNMENT\t\t4096\n-#define IAVF_SR_WORDS_IN_1KB\t\t512\n-/* Checksum should be calculated such that after adding all the words,\n- * including the checksum word itself, the sum should be 0xBABA.\n- */\n-#define IAVF_SR_SW_CHECKSUM_BASE\t0xBABA\n-\n-#define IAVF_SRRD_SRCTL_ATTEMPTS\t100000\n-\n-/* FCoE Tx context descriptor - Use the iavf_tx_context_desc struct */\n-\n-enum i40E_fcoe_tx_ctx_desc_cmd_bits {\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND\t= 0x00, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2\t= 0x01, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3\t= 0x05, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2\t= 0x02, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3\t= 0x06, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2\t= 0x03, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3\t= 0x07, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL\t= 0x08, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL\t= 0x09, /* 4 BITS */\n-\tIAVF_FCOE_TX_CTX_DESC_RELOFF\t\t\t= 0x10,\n-\tIAVF_FCOE_TX_CTX_DESC_CLRSEQ\t\t\t= 0x20,\n-\tIAVF_FCOE_TX_CTX_DESC_DIFENA\t\t\t= 0x40,\n-\tIAVF_FCOE_TX_CTX_DESC_IL2TAG2\t\t\t= 0x80\n-};\n \n-/* FCoE DIF/DIX Context descriptor */\n-struct iavf_fcoe_difdix_context_desc {\n-\t__le64 flags_buff0_buff1_ref;\n-\t__le64 difapp_msk_bias;\n-};\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT\t0\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK\t(0xFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)\n-\n-enum iavf_fcoe_difdix_ctx_desc_flags_bits {\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_RSVD\t\t\t\t= 0x0000,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK\t\t= 0x0000,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK\t\t= 0x0004,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE\t\t\t= 0x0000,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY\t\t= 0x0008,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG\t= 0x0010,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG\t= 0x0018,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST\t\t\t= 0x0000,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK\t\t= 0x0020,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG\t\t= 0x0040,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD\t\t\t= 0x0060,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM\t\t\t= 0x0000,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC\t\t\t= 0x0080,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG\t\t\t= 0x0000,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF\t\t\t= 0x0100,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD\t\t\t= 0x0200,\n-\t/* 2 BITS */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS\t\t= 0x0300,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG\t\t\t= 0x0000,\n-\t/* 1 BIT  */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG\t\t\t= 0x0400,\n-\t/* 1 BIT */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B\t\t\t= 0x0000,\n-\t/* 1 BIT */\n-\tIAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K\t\t\t= 0x0800\n-};\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT\t12\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK\t(0x3FFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT\t22\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK\t(0x3FFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT\t32\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_MASK\t(0xFFFFFFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT\t0\n-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MASK\t(0xFFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT\t16\n-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK\t(0xFFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)\n-\n-#define IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT\t32\n-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK\t(0xFFFFFFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)\n-\n-/* FCoE DIF/DIX Buffers descriptor */\n-struct iavf_fcoe_difdix_buffers_desc {\n-\t__le64 buff_addr0;\n-\t__le64 buff_addr1;\n-};\n-\n-/* FCoE DDP Context descriptor */\n-struct iavf_fcoe_ddp_context_desc {\n-\t__le64 rsvd;\n-\t__le64 type_cmd_foff_lsize;\n-};\n \n-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT\t0\n-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_MASK\t(0xFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)\n-\n-#define IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT\t4\n-#define IAVF_FCOE_DDP_CTX_QW1_CMD_MASK\t(0xFULL << \\\n-\t\t\t\t\t IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT)\n-\n-enum iavf_fcoe_ddp_ctx_desc_cmd_bits {\n-\tIAVF_FCOE_DDP_CTX_DESC_BSIZE_512B\t= 0x00, /* 2 BITS */\n-\tIAVF_FCOE_DDP_CTX_DESC_BSIZE_4K\t\t= 0x01, /* 2 BITS */\n-\tIAVF_FCOE_DDP_CTX_DESC_BSIZE_8K\t\t= 0x02, /* 2 BITS */\n-\tIAVF_FCOE_DDP_CTX_DESC_BSIZE_16K\t= 0x03, /* 2 BITS */\n-\tIAVF_FCOE_DDP_CTX_DESC_DIFENA\t\t= 0x04, /* 1 BIT  */\n-\tIAVF_FCOE_DDP_CTX_DESC_LASTSEQH\t\t= 0x08, /* 1 BIT  */\n-};\n-\n-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT\t16\n-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_MASK\t(0x3FFFULL << \\\n-\t\t\t\t\t IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT)\n-\n-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT\t32\n-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_MASK\t(0x3FFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)\n-\n-/* FCoE DDP/DWO Queue Context descriptor */\n-struct iavf_fcoe_queue_context_desc {\n-\t__le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */\n-\t__le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */\n-};\n-\n-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT\t0\n-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK\t(0xFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)\n-\n-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT\t12\n-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_MASK\t(0xFFFFFFFFFFFFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)\n-\n-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT\t0\n-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_MASK\t(0x1FFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)\n-\n-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_SHIFT\t13\n-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_MASK\t(0x7ULL << \\\n-\t\t\t\t\tIAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)\n-\n-enum iavf_fcoe_queue_ctx_desc_tph_bits {\n-\tIAVF_FCOE_QUEUE_CTX_DESC_TPHRDESC\t= 0x1,\n-\tIAVF_FCOE_QUEUE_CTX_DESC_TPHDATA\t= 0x2\n-};\n-\n-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT\t30\n-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_MASK\t(0x3ULL << \\\n-\t\t\t\t\tIAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)\n-\n-/* FCoE DDP/DWO Filter Context descriptor */\n-struct iavf_fcoe_filter_context_desc {\n-\t__le32 param;\n-\t__le16 seqn;\n-\n-\t/* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */\n-\t__le16 rsvd_dmaindx;\n-\n-\t/* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */\n-\t__le64 flags_rsvd_lanq;\n-};\n-\n-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT\t4\n-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_MASK\t(0xFFF << \\\n-\t\t\t\t\tIAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)\n-\n-enum iavf_fcoe_filter_ctx_desc_flags_bits {\n-\tIAVF_FCOE_FILTER_CTX_DESC_CTYP_DDP\t= 0x00,\n-\tIAVF_FCOE_FILTER_CTX_DESC_CTYP_DWO\t= 0x01,\n-\tIAVF_FCOE_FILTER_CTX_DESC_ENODE_INIT\t= 0x00,\n-\tIAVF_FCOE_FILTER_CTX_DESC_ENODE_RSP\t= 0x02,\n-\tIAVF_FCOE_FILTER_CTX_DESC_FC_CLASS2\t= 0x00,\n-\tIAVF_FCOE_FILTER_CTX_DESC_FC_CLASS3\t= 0x04\n-};\n-\n-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT\t0\n-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_MASK\t(0xFFULL << \\\n-\t\t\t\t\tIAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)\n-\n-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8\n-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \\\n-\t\t\tIAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)\n-\n-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53\n-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \\\n-\t\t\tIAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)\n-\n-enum iavf_switch_element_types {\n-\tIAVF_SWITCH_ELEMENT_TYPE_MAC\t= 1,\n-\tIAVF_SWITCH_ELEMENT_TYPE_PF\t= 2,\n-\tIAVF_SWITCH_ELEMENT_TYPE_VF\t= 3,\n-\tIAVF_SWITCH_ELEMENT_TYPE_EMP\t= 4,\n-\tIAVF_SWITCH_ELEMENT_TYPE_BMC\t= 6,\n-\tIAVF_SWITCH_ELEMENT_TYPE_PE\t= 16,\n-\tIAVF_SWITCH_ELEMENT_TYPE_VEB\t= 17,\n-\tIAVF_SWITCH_ELEMENT_TYPE_PA\t= 18,\n-\tIAVF_SWITCH_ELEMENT_TYPE_VSI\t= 19,\n-};\n-\n-/* Supported EtherType filters */\n-enum iavf_ether_type_index {\n-\tIAVF_ETHER_TYPE_1588\t\t= 0,\n-\tIAVF_ETHER_TYPE_FIP\t\t= 1,\n-\tIAVF_ETHER_TYPE_OUI_EXTENDED\t= 2,\n-\tIAVF_ETHER_TYPE_MAC_CONTROL\t= 3,\n-\tIAVF_ETHER_TYPE_LLDP\t\t= 4,\n-\tIAVF_ETHER_TYPE_EVB_PROTOCOL1\t= 5,\n-\tIAVF_ETHER_TYPE_EVB_PROTOCOL2\t= 6,\n-\tIAVF_ETHER_TYPE_QCN_CNM\t\t= 7,\n-\tIAVF_ETHER_TYPE_8021X\t\t= 8,\n-\tIAVF_ETHER_TYPE_ARP\t\t= 9,\n-\tIAVF_ETHER_TYPE_RSV1\t\t= 10,\n-\tIAVF_ETHER_TYPE_RSV2\t\t= 11,\n-};\n-\n-/* Filter context base size is 1K */\n-#define IAVF_HASH_FILTER_BASE_SIZE\t1024\n-/* Supported Hash filter values */\n-enum iavf_hash_filter_size {\n-\tIAVF_HASH_FILTER_SIZE_1K\t= 0,\n-\tIAVF_HASH_FILTER_SIZE_2K\t= 1,\n-\tIAVF_HASH_FILTER_SIZE_4K\t= 2,\n-\tIAVF_HASH_FILTER_SIZE_8K\t= 3,\n-\tIAVF_HASH_FILTER_SIZE_16K\t= 4,\n-\tIAVF_HASH_FILTER_SIZE_32K\t= 5,\n-\tIAVF_HASH_FILTER_SIZE_64K\t= 6,\n-\tIAVF_HASH_FILTER_SIZE_128K\t= 7,\n-\tIAVF_HASH_FILTER_SIZE_256K\t= 8,\n-\tIAVF_HASH_FILTER_SIZE_512K\t= 9,\n-\tIAVF_HASH_FILTER_SIZE_1M\t= 10,\n-};\n-\n-/* DMA context base size is 0.5K */\n-#define IAVF_DMA_CNTX_BASE_SIZE\t\t512\n-/* Supported DMA context values */\n-enum iavf_dma_cntx_size {\n-\tIAVF_DMA_CNTX_SIZE_512\t\t= 0,\n-\tIAVF_DMA_CNTX_SIZE_1K\t\t= 1,\n-\tIAVF_DMA_CNTX_SIZE_2K\t\t= 2,\n-\tIAVF_DMA_CNTX_SIZE_4K\t\t= 3,\n-\tIAVF_DMA_CNTX_SIZE_8K\t\t= 4,\n-\tIAVF_DMA_CNTX_SIZE_16K\t\t= 5,\n-\tIAVF_DMA_CNTX_SIZE_32K\t\t= 6,\n-\tIAVF_DMA_CNTX_SIZE_64K\t\t= 7,\n-\tIAVF_DMA_CNTX_SIZE_128K\t\t= 8,\n-\tIAVF_DMA_CNTX_SIZE_256K\t\t= 9,\n-};\n-\n-/* Supported Hash look up table (LUT) sizes */\n-enum iavf_hash_lut_size {\n-\tIAVF_HASH_LUT_SIZE_128\t\t= 0,\n-\tIAVF_HASH_LUT_SIZE_512\t\t= 1,\n-};\n-\n-/* Structure to hold a per PF filter control settings */\n-struct iavf_filter_control_settings {\n-\t/* number of PE Quad Hash filter buckets */\n-\tenum iavf_hash_filter_size pe_filt_num;\n-\t/* number of PE Quad Hash contexts */\n-\tenum iavf_dma_cntx_size pe_cntx_num;\n-\t/* number of FCoE filter buckets */\n-\tenum iavf_hash_filter_size fcoe_filt_num;\n-\t/* number of FCoE DDP contexts */\n-\tenum iavf_dma_cntx_size fcoe_cntx_num;\n-\t/* size of the Hash LUT */\n-\tenum iavf_hash_lut_size\thash_lut_size;\n-\t/* enable FDIR filters for PF and its VFs */\n-\tbool enable_fdir;\n-\t/* enable Ethertype filters for PF and its VFs */\n-\tbool enable_ethtype;\n-\t/* enable MAC/VLAN filters for PF and its VFs */\n-\tbool enable_macvlan;\n-};\n-\n-/* Structure to hold device level control filter counts */\n-struct iavf_control_filter_stats {\n-\tu16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */\n-\tu16 etype_used;       /* Used perfect EtherType filters */\n-\tu16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */\n-\tu16 etype_free;       /* Un-used perfect EtherType filters */\n-};\n-\n-enum iavf_reset_type {\n-\tIAVF_RESET_POR\t\t= 0,\n-\tIAVF_RESET_CORER\t= 1,\n-\tIAVF_RESET_GLOBR\t= 2,\n-\tIAVF_RESET_EMPR\t\t= 3,\n-};\n-\n-/* IEEE 802.1AB LLDP Agent Variables from NVM */\n-#define IAVF_NVM_LLDP_CFG_PTR   0x06\n-#define IAVF_SR_LLDP_CFG_PTR    0x31\n struct iavf_lldp_variables {\n \tu16 length;\n \tu16 adminstatus;\n@@ -1852,118 +995,13 @@ struct iavf_lldp_variables {\n #define IAVF_ALT_BW_RELATIVE_MASK\t0x40000000\n #define IAVF_ALT_BW_VALID_MASK\t\t0x80000000\n \n-/* RSS Hash Table Size */\n-#define IAVF_PFQF_CTL_0_HASHLUTSIZE_512\t0x00010000\n-\n-/* INPUT SET MASK for RSS, flow director, and flexible payload */\n-#define IAVF_L3_SRC_SHIFT\t\t47\n-#define IAVF_L3_SRC_MASK\t\t(0x3ULL << IAVF_L3_SRC_SHIFT)\n-#define IAVF_L3_V6_SRC_SHIFT\t\t43\n-#define IAVF_L3_V6_SRC_MASK\t\t(0xFFULL << IAVF_L3_V6_SRC_SHIFT)\n-#define IAVF_L3_DST_SHIFT\t\t35\n-#define IAVF_L3_DST_MASK\t\t(0x3ULL << IAVF_L3_DST_SHIFT)\n-#define IAVF_L3_V6_DST_SHIFT\t\t35\n-#define IAVF_L3_V6_DST_MASK\t\t(0xFFULL << IAVF_L3_V6_DST_SHIFT)\n-#define IAVF_L4_SRC_SHIFT\t\t34\n-#define IAVF_L4_SRC_MASK\t\t(0x1ULL << IAVF_L4_SRC_SHIFT)\n-#define IAVF_L4_DST_SHIFT\t\t33\n-#define IAVF_L4_DST_MASK\t\t(0x1ULL << IAVF_L4_DST_SHIFT)\n-#define IAVF_VERIFY_TAG_SHIFT\t\t31\n-#define IAVF_VERIFY_TAG_MASK\t\t(0x3ULL << IAVF_VERIFY_TAG_SHIFT)\n-\n-#define IAVF_FLEX_50_SHIFT\t\t13\n-#define IAVF_FLEX_50_MASK\t\t(0x1ULL << IAVF_FLEX_50_SHIFT)\n-#define IAVF_FLEX_51_SHIFT\t\t12\n-#define IAVF_FLEX_51_MASK\t\t(0x1ULL << IAVF_FLEX_51_SHIFT)\n-#define IAVF_FLEX_52_SHIFT\t\t11\n-#define IAVF_FLEX_52_MASK\t\t(0x1ULL << IAVF_FLEX_52_SHIFT)\n-#define IAVF_FLEX_53_SHIFT\t\t10\n-#define IAVF_FLEX_53_MASK\t\t(0x1ULL << IAVF_FLEX_53_SHIFT)\n-#define IAVF_FLEX_54_SHIFT\t\t9\n-#define IAVF_FLEX_54_MASK\t\t(0x1ULL << IAVF_FLEX_54_SHIFT)\n-#define IAVF_FLEX_55_SHIFT\t\t8\n-#define IAVF_FLEX_55_MASK\t\t(0x1ULL << IAVF_FLEX_55_SHIFT)\n-#define IAVF_FLEX_56_SHIFT\t\t7\n-#define IAVF_FLEX_56_MASK\t\t(0x1ULL << IAVF_FLEX_56_SHIFT)\n-#define IAVF_FLEX_57_SHIFT\t\t6\n-#define IAVF_FLEX_57_MASK\t\t(0x1ULL << IAVF_FLEX_57_SHIFT)\n-\n-/* Version format for Dynamic Device Personalization(DDP) */\n-struct iavf_ddp_version {\n-\tu8 major;\n-\tu8 minor;\n-\tu8 update;\n-\tu8 draft;\n-};\n-\n-#define IAVF_DDP_NAME_SIZE\t32\n-\n-/* Package header */\n-struct iavf_package_header {\n-\tstruct iavf_ddp_version version;\n-\tu32 segment_count;\n-\tu32 segment_offset[1];\n-};\n-\n-/* Generic segment header */\n-struct iavf_generic_seg_header {\n-#define SEGMENT_TYPE_METADATA\t0x00000001\n-#define SEGMENT_TYPE_NOTES\t0x00000002\n-#define SEGMENT_TYPE_IAVF\t0x00000011\n-#define SEGMENT_TYPE_X722\t0x00000012\n-\tu32 type;\n-\tstruct iavf_ddp_version version;\n-\tu32 size;\n-\tchar name[IAVF_DDP_NAME_SIZE];\n-};\n-\n-struct iavf_metadata_segment {\n-\tstruct iavf_generic_seg_header header;\n-\tstruct iavf_ddp_version version;\n #define IAVF_DDP_TRACKID_RDONLY\t\t0\n #define IAVF_DDP_TRACKID_INVALID\t0xFFFFFFFF\n-\tu32 track_id;\n-\tchar name[IAVF_DDP_NAME_SIZE];\n-};\n-\n-struct iavf_device_id_entry {\n-\tu32 vendor_dev_id;\n-\tu32 sub_vendor_dev_id;\n-};\n-\n-struct iavf_profile_segment {\n-\tstruct iavf_generic_seg_header header;\n-\tstruct iavf_ddp_version version;\n-\tchar name[IAVF_DDP_NAME_SIZE];\n-\tu32 device_table_count;\n-\tstruct iavf_device_id_entry device_table[1];\n-};\n-\n-struct iavf_section_table {\n-\tu32 section_count;\n-\tu32 section_offset[1];\n-};\n-\n-struct iavf_profile_section_header {\n-\tu16 tbl_size;\n-\tu16 data_end;\n-\tstruct {\n-#define SECTION_TYPE_INFO\t0x00000010\n-#define SECTION_TYPE_MMIO\t0x00000800\n #define SECTION_TYPE_RB_MMIO\t0x00001800\n-#define SECTION_TYPE_AQ\t\t0x00000801\n #define SECTION_TYPE_RB_AQ\t0x00001801\n-#define SECTION_TYPE_NOTE\t0x80000000\n-#define SECTION_TYPE_NAME\t0x80000001\n #define SECTION_TYPE_PROTO\t0x80000002\n #define SECTION_TYPE_PCTYPE\t0x80000003\n #define SECTION_TYPE_PTYPE\t0x80000004\n-\t\tu32 type;\n-\t\tu32 offset;\n-\t\tu32 size;\n-\t} section;\n-};\n-\n struct iavf_profile_tlv_section_record {\n \tu8 rtype;\n \tu8 type;\n@@ -1980,13 +1018,4 @@ struct iavf_profile_aq_section {\n \tu8  data[1];\n };\n \n-struct iavf_profile_info {\n-\tu32 track_id;\n-\tstruct iavf_ddp_version version;\n-\tu8 op;\n-#define IAVF_DDP_ADD_TRACKID\t\t0x01\n-#define IAVF_DDP_REMOVE_TRACKID\t0x02\n-\tu8 reserved[7];\n-\tu8 name[IAVF_DDP_NAME_SIZE];\n-};\n #endif /* _IAVF_TYPE_H_ */\n",
    "prefixes": [
        "05/17"
    ]
}