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GET /api/patches/63525/?format=api
{ "id": 63525, "url": "http://patches.dpdk.org/api/patches/63525/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191203070318.39620-4-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191203070318.39620-4-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191203070318.39620-4-qi.z.zhang@intel.com", "date": "2019-12-03T07:03:04", "name": "[03/17] net/iavf/base: rename register macro", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f7f038741f2f09cc835c612c5e8301b6e034c2bc", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191203070318.39620-4-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 7716, "url": "http://patches.dpdk.org/api/series/7716/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7716", "date": "2019-12-03T07:03:01", "name": "iavf base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/7716/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63525/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/63525/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3F1D9A04EF;\n\tTue, 3 Dec 2019 08:00:49 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9ADB71BF6E;\n\tTue, 3 Dec 2019 08:00:22 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id B01911B9B5\n for <dev@dpdk.org>; Tue, 3 Dec 2019 08:00:19 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 02 Dec 2019 23:00:19 -0800", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga005.fm.intel.com with ESMTP; 02 Dec 2019 23:00:17 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,272,1571727600\"; d=\"scan'208\";a=\"410729652\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "xiaolong.ye@intel.com", "Cc": "haiyue.wang@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Tue, 3 Dec 2019 15:03:04 +0800", "Message-Id": "<20191203070318.39620-4-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20191203070318.39620-1-qi.z.zhang@intel.com>", "References": "<20191203070318.39620-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 03/17] net/iavf/base: rename register macro", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rename all register macro to align with kernel driver's\nimplementation.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/iavf/base/iavf_adminq.c | 34 +--\n drivers/net/iavf/base/iavf_common.c | 4 +-\n drivers/net/iavf/base/iavf_osdep.h | 2 +-\n drivers/net/iavf/base/iavf_register.h | 388 +++++++---------------------------\n drivers/net/iavf/iavf_ethdev.c | 59 +++---\n 5 files changed, 134 insertions(+), 353 deletions(-)", "diff": "diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c\nindex ae8150e4f..193e2e7d1 100644\n--- a/drivers/net/iavf/base/iavf_adminq.c\n+++ b/drivers/net/iavf/base/iavf_adminq.c\n@@ -18,16 +18,16 @@ STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)\n {\n \t/* set head and tail registers in our local struct */\n \tif (iavf_is_vf(hw)) {\n-\t\thw->aq.asq.tail = IAVF_ATQT1;\n-\t\thw->aq.asq.head = IAVF_ATQH1;\n-\t\thw->aq.asq.len = IAVF_ATQLEN1;\n-\t\thw->aq.asq.bal = IAVF_ATQBAL1;\n-\t\thw->aq.asq.bah = IAVF_ATQBAH1;\n-\t\thw->aq.arq.tail = IAVF_ARQT1;\n-\t\thw->aq.arq.head = IAVF_ARQH1;\n-\t\thw->aq.arq.len = IAVF_ARQLEN1;\n-\t\thw->aq.arq.bal = IAVF_ARQBAL1;\n-\t\thw->aq.arq.bah = IAVF_ARQBAH1;\n+\t\thw->aq.asq.tail = IAVF_VF_ATQT1;\n+\t\thw->aq.asq.head = IAVF_VF_ATQH1;\n+\t\thw->aq.asq.len = IAVF_VF_ATQLEN1;\n+\t\thw->aq.asq.bal = IAVF_VF_ATQBAL1;\n+\t\thw->aq.asq.bah = IAVF_VF_ATQBAH1;\n+\t\thw->aq.arq.tail = IAVF_VF_ARQT1;\n+\t\thw->aq.arq.head = IAVF_VF_ARQH1;\n+\t\thw->aq.arq.len = IAVF_VF_ARQLEN1;\n+\t\thw->aq.arq.bal = IAVF_VF_ARQBAL1;\n+\t\thw->aq.arq.bah = IAVF_VF_ARQBAH1;\n \t}\n }\n \n@@ -267,10 +267,10 @@ STATIC enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)\n #ifdef INTEGRATED_VF\n \tif (iavf_is_vf(hw))\n \t\twr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |\n-\t\t\t\t\t IAVF_ATQLEN1_ATQENABLE_MASK));\n+\t\t\t\t\t IAVF_VF_ATQLEN1_ATQENABLE_MASK));\n #else\n \twr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |\n-\t\t\t\t IAVF_ATQLEN1_ATQENABLE_MASK));\n+\t\t\t\t IAVF_VF_ATQLEN1_ATQENABLE_MASK));\n #endif /* INTEGRATED_VF */\n \twr32(hw, hw->aq.asq.bal, IAVF_LO_DWORD(hw->aq.asq.desc_buf.pa));\n \twr32(hw, hw->aq.asq.bah, IAVF_HI_DWORD(hw->aq.asq.desc_buf.pa));\n@@ -302,10 +302,10 @@ STATIC enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)\n #ifdef INTEGRATED_VF\n \tif (iavf_is_vf(hw))\n \t\twr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |\n-\t\t\t\t\t IAVF_ARQLEN1_ARQENABLE_MASK));\n+\t\t\t\t\t IAVF_VF_ARQLEN1_ARQENABLE_MASK));\n #else\n \twr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |\n-\t\t\t\t IAVF_ARQLEN1_ARQENABLE_MASK));\n+\t\t\t\t IAVF_VF_ARQLEN1_ARQENABLE_MASK));\n #endif /* INTEGRATED_VF */\n \twr32(hw, hw->aq.arq.bal, IAVF_LO_DWORD(hw->aq.arq.desc_buf.pa));\n \twr32(hw, hw->aq.arq.bah, IAVF_HI_DWORD(hw->aq.arq.desc_buf.pa));\n@@ -834,7 +834,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,\n \t/* update the error if time out occurred */\n \tif ((!cmd_completed) &&\n \t (!details->async && !details->postpone)) {\n-\t\tif (rd32(hw, hw->aq.asq.len) & IAVF_ATQLEN1_ATQCRIT_MASK) {\n+\t\tif (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {\n \t\t\tiavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,\n \t\t\t\t \"AQTX: AQ Critical error.\\n\");\n \t\t\tstatus = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;\n@@ -908,9 +908,9 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,\n \tif (!iavf_is_vf(hw))\n \t\tntu = rd32(hw, hw->aq.arq.head) & IAVF_PF_ARQH_ARQH_MASK;\n \telse\n-\t\tntu = rd32(hw, hw->aq.arq.head) & IAVF_ARQH1_ARQH_MASK;\n+\t\tntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;\n #else\n-\tntu = rd32(hw, hw->aq.arq.head) & IAVF_ARQH1_ARQH_MASK;\n+\tntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;\n #endif /* INTEGRATED_VF */\n \tif (ntu == ntc) {\n \t\t/* nothing to do - shouldn't need to update ring's values */\ndiff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c\nindex 0b9f83415..5df4410e0 100644\n--- a/drivers/net/iavf/base/iavf_common.c\n+++ b/drivers/net/iavf/base/iavf_common.c\n@@ -332,10 +332,10 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)\n #ifdef INTEGRATED_VF\n \t\tif (iavf_is_vf(hw))\n \t\t\treturn !!(rd32(hw, hw->aq.asq.len) &\n-\t\t\t\tIAVF_ATQLEN1_ATQENABLE_MASK);\n+\t\t\t\tIAVF_VF_ATQLEN1_ATQENABLE_MASK);\n #else\n \t\treturn !!(rd32(hw, hw->aq.asq.len) &\n-\t\t\tIAVF_ATQLEN1_ATQENABLE_MASK);\n+\t\t\tIAVF_VF_ATQLEN1_ATQENABLE_MASK);\n #endif /* INTEGRATED_VF */\n \treturn false;\n }\ndiff --git a/drivers/net/iavf/base/iavf_osdep.h b/drivers/net/iavf/base/iavf_osdep.h\nindex 648026693..1b22f9fbc 100644\n--- a/drivers/net/iavf/base/iavf_osdep.h\n+++ b/drivers/net/iavf/base/iavf_osdep.h\n@@ -115,7 +115,7 @@ uint32_t iavf_read_addr(volatile void *addr)\n #define IAVF_WRITE_REG(hw, reg, value) \\\n \tIAVF_PCI_REG_WRITE(IAVF_PCI_REG_ADDR((hw), (reg)), (value))\n #define IAVF_WRITE_FLUSH(a) \\\n-\tIAVF_READ_REG(a, IAVFGEN_RSTAT)\n+\tIAVF_READ_REG(a, IAVF_VFGEN_RSTAT)\n \n #define rd32(a, reg) iavf_read_addr(IAVF_PCI_REG_ADDR((a), (reg)))\n #define wr32(a, reg, value) \\\ndiff --git a/drivers/net/iavf/base/iavf_register.h b/drivers/net/iavf/base/iavf_register.h\nindex b66d88c44..7d2b20710 100644\n--- a/drivers/net/iavf/base/iavf_register.h\n+++ b/drivers/net/iavf/base/iavf_register.h\n@@ -5,313 +5,89 @@\n #ifndef _IAVF_REGISTER_H_\n #define _IAVF_REGISTER_H_\n \n-\n-#define IAVFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */\n-#define IAVFMSIX_PBA1_MAX_INDEX 19\n-#define IAVFMSIX_PBA1_PENBIT_SHIFT 0\n-#define IAVFMSIX_PBA1_PENBIT_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA1_PENBIT_SHIFT)\n-#define IAVFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define IAVFMSIX_TADD1_MAX_INDEX 639\n-#define IAVFMSIX_TADD1_MSIXTADD10_SHIFT 0\n-#define IAVFMSIX_TADD1_MSIXTADD10_MASK IAVF_MASK(0x3, IAVFMSIX_TADD1_MSIXTADD10_SHIFT)\n-#define IAVFMSIX_TADD1_MSIXTADD_SHIFT 2\n-#define IAVFMSIX_TADD1_MSIXTADD_MASK IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD1_MSIXTADD_SHIFT)\n-#define IAVFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define IAVFMSIX_TMSG1_MAX_INDEX 639\n-#define IAVFMSIX_TMSG1_MSIXTMSG_SHIFT 0\n-#define IAVFMSIX_TMSG1_MSIXTMSG_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG1_MSIXTMSG_SHIFT)\n-#define IAVFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define IAVFMSIX_TUADD1_MAX_INDEX 639\n-#define IAVFMSIX_TUADD1_MSIXTUADD_SHIFT 0\n-#define IAVFMSIX_TUADD1_MSIXTUADD_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD1_MSIXTUADD_SHIFT)\n-#define IAVFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n-#define IAVFMSIX_TVCTRL1_MAX_INDEX 639\n-#define IAVFMSIX_TVCTRL1_MASK_SHIFT 0\n-#define IAVFMSIX_TVCTRL1_MASK_MASK IAVF_MASK(0x1, IAVFMSIX_TVCTRL1_MASK_SHIFT)\n-#define IAVF_ARQBAH1 0x00006000 /* Reset: EMPR */\n-#define IAVF_ARQBAH1_ARQBAH_SHIFT 0\n-#define IAVF_ARQBAH1_ARQBAH_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAH1_ARQBAH_SHIFT)\n-#define IAVF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n-#define IAVF_ARQBAL1_ARQBAL_SHIFT 0\n-#define IAVF_ARQBAL1_ARQBAL_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAL1_ARQBAL_SHIFT)\n-#define IAVF_ARQH1 0x00007400 /* Reset: EMPR */\n-#define IAVF_ARQH1_ARQH_SHIFT 0\n-#define IAVF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_ARQH1_ARQH_SHIFT)\n-#define IAVF_ARQLEN1 0x00008000 /* Reset: EMPR */\n-#define IAVF_ARQLEN1_ARQLEN_SHIFT 0\n-#define IAVF_ARQLEN1_ARQLEN_MASK IAVF_MASK(0x3FF, IAVF_ARQLEN1_ARQLEN_SHIFT)\n-#define IAVF_ARQLEN1_ARQVFE_SHIFT 28\n-#define IAVF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQVFE_SHIFT)\n-#define IAVF_ARQLEN1_ARQOVFL_SHIFT 29\n-#define IAVF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQOVFL_SHIFT)\n-#define IAVF_ARQLEN1_ARQCRIT_SHIFT 30\n-#define IAVF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQCRIT_SHIFT)\n-#define IAVF_ARQLEN1_ARQENABLE_SHIFT 31\n-#define IAVF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1U, IAVF_ARQLEN1_ARQENABLE_SHIFT)\n-#define IAVF_ARQT1 0x00007000 /* Reset: EMPR */\n-#define IAVF_ARQT1_ARQT_SHIFT 0\n-#define IAVF_ARQT1_ARQT_MASK IAVF_MASK(0x3FF, IAVF_ARQT1_ARQT_SHIFT)\n-#define IAVF_ATQBAH1 0x00007800 /* Reset: EMPR */\n-#define IAVF_ATQBAH1_ATQBAH_SHIFT 0\n-#define IAVF_ATQBAH1_ATQBAH_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAH1_ATQBAH_SHIFT)\n-#define IAVF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n-#define IAVF_ATQBAL1_ATQBAL_SHIFT 0\n-#define IAVF_ATQBAL1_ATQBAL_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAL1_ATQBAL_SHIFT)\n-#define IAVF_ATQH1 0x00006400 /* Reset: EMPR */\n-#define IAVF_ATQH1_ATQH_SHIFT 0\n-#define IAVF_ATQH1_ATQH_MASK IAVF_MASK(0x3FF, IAVF_ATQH1_ATQH_SHIFT)\n-#define IAVF_ATQLEN1 0x00006800 /* Reset: EMPR */\n-#define IAVF_ATQLEN1_ATQLEN_SHIFT 0\n-#define IAVF_ATQLEN1_ATQLEN_MASK IAVF_MASK(0x3FF, IAVF_ATQLEN1_ATQLEN_SHIFT)\n-#define IAVF_ATQLEN1_ATQVFE_SHIFT 28\n-#define IAVF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQVFE_SHIFT)\n-#define IAVF_ATQLEN1_ATQOVFL_SHIFT 29\n-#define IAVF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQOVFL_SHIFT)\n-#define IAVF_ATQLEN1_ATQCRIT_SHIFT 30\n-#define IAVF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQCRIT_SHIFT)\n-#define IAVF_ATQLEN1_ATQENABLE_SHIFT 31\n-#define IAVF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1U, IAVF_ATQLEN1_ATQENABLE_SHIFT)\n-#define IAVF_ATQT1 0x00008400 /* Reset: EMPR */\n-#define IAVF_ATQT1_ATQT_SHIFT 0\n-#define IAVF_ATQT1_ATQT_MASK IAVF_MASK(0x3FF, IAVF_ATQT1_ATQT_SHIFT)\n-#define IAVFGEN_RSTAT 0x00008800 /* Reset: VFR */\n-#define IAVFGEN_RSTAT_VFR_STATE_SHIFT 0\n-#define IAVFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVFGEN_RSTAT_VFR_STATE_SHIFT)\n-#define IAVFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n-#define IAVFINT_DYN_CTL01_INTENA_SHIFT 0\n-#define IAVFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_SHIFT)\n-#define IAVFINT_DYN_CTL01_CLEARPBA_SHIFT 1\n-#define IAVFINT_DYN_CTL01_CLEARPBA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_CLEARPBA_SHIFT)\n-#define IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2\n-#define IAVFINT_DYN_CTL01_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT)\n-#define IAVFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n-#define IAVFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTL01_ITR_INDX_SHIFT)\n-#define IAVFINT_DYN_CTL01_INTERVAL_SHIFT 5\n-#define IAVFINT_DYN_CTL01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_DYN_CTL01_INTERVAL_SHIFT)\n-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24\n-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)\n-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25\n-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)\n-#define IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT 31\n-#define IAVFINT_DYN_CTL01_INTENA_MSK_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT)\n-#define IAVFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n-#define IAVFINT_DYN_CTLN1_MAX_INDEX 15\n-#define IAVFINT_DYN_CTLN1_INTENA_SHIFT 0\n-#define IAVFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_SHIFT)\n-#define IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT 1\n-#define IAVFINT_DYN_CTLN1_CLEARPBA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT)\n-#define IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n-#define IAVFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n-#define IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n-#define IAVFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n-#define IAVFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n-#define IAVFINT_DYN_CTLN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_DYN_CTLN1_INTERVAL_SHIFT)\n-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25\n-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)\n-#define IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31\n-#define IAVFINT_DYN_CTLN1_INTENA_MSK_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT)\n-#define IAVFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n-#define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25\n-#define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)\n-#define IAVFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n-#define IAVFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_ADMINQ_SHIFT)\n-#define IAVFINT_ICR0_ENA1_RSVD_SHIFT 31\n-#define IAVFINT_ICR0_ENA1_RSVD_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_RSVD_SHIFT)\n-#define IAVFINT_ICR01 0x00004800 /* Reset: CORER */\n-#define IAVFINT_ICR01_INTEVENT_SHIFT 0\n-#define IAVFINT_ICR01_INTEVENT_MASK IAVF_MASK(0x1, IAVFINT_ICR01_INTEVENT_SHIFT)\n-#define IAVFINT_ICR01_QUEUE_0_SHIFT 1\n-#define IAVFINT_ICR01_QUEUE_0_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_0_SHIFT)\n-#define IAVFINT_ICR01_QUEUE_1_SHIFT 2\n-#define IAVFINT_ICR01_QUEUE_1_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_1_SHIFT)\n-#define IAVFINT_ICR01_QUEUE_2_SHIFT 3\n-#define IAVFINT_ICR01_QUEUE_2_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_2_SHIFT)\n-#define IAVFINT_ICR01_QUEUE_3_SHIFT 4\n-#define IAVFINT_ICR01_QUEUE_3_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_3_SHIFT)\n-#define IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25\n-#define IAVFINT_ICR01_LINK_STAT_CHANGE_MASK IAVF_MASK(0x1, IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT)\n-#define IAVFINT_ICR01_ADMINQ_SHIFT 30\n-#define IAVFINT_ICR01_ADMINQ_MASK IAVF_MASK(0x1, IAVFINT_ICR01_ADMINQ_SHIFT)\n-#define IAVFINT_ICR01_SWINT_SHIFT 31\n-#define IAVFINT_ICR01_SWINT_MASK IAVF_MASK(0x1, IAVFINT_ICR01_SWINT_SHIFT)\n-#define IAVFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */\n-#define IAVFINT_ITR01_MAX_INDEX 2\n-#define IAVFINT_ITR01_INTERVAL_SHIFT 0\n-#define IAVFINT_ITR01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_ITR01_INTERVAL_SHIFT)\n-#define IAVFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n-#define IAVFINT_ITRN1_MAX_INDEX 2\n-#define IAVFINT_ITRN1_INTERVAL_SHIFT 0\n-#define IAVFINT_ITRN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_ITRN1_INTERVAL_SHIFT)\n-#define IAVFINT_STAT_CTL01 0x00005400 /* Reset: CORER */\n-#define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2\n-#define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)\n+#define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */\n+#define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n+#define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */\n+#define IAVF_VF_ARQH1_ARQH_SHIFT 0\n+#define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)\n+#define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */\n+#define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28\n+#define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29\n+#define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30\n+#define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)\n+#define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31\n+#define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)\n+#define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */\n+#define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */\n+#define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n+#define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */\n+#define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */\n+#define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28\n+#define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29\n+#define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30\n+#define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)\n+#define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31\n+#define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)\n+#define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */\n+#define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */\n+#define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0\n+#define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n+#define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0\n+#define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1\n+#define IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2\n+#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT 5\n+#define IAVF_VFINT_DYN_CTL01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24\n+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25\n+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n+#define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0\n+#define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1\n+#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n+#define IAVF_VFINT_DYN_CTLN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25\n+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)\n+#define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)\n+#define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31\n+#define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */\n+#define IAVF_VFINT_ICR01_QUEUE_0_SHIFT 1\n+#define IAVF_VFINT_ICR01_QUEUE_0_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_QUEUE_0_SHIFT)\n+#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25\n+#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)\n+#define IAVF_VFINT_ICR01_ADMINQ_SHIFT 30\n+#define IAVF_VFINT_ICR01_ADMINQ_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_ADMINQ_SHIFT)\n+#define IAVF_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */\n+#define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n+#define IAVF_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */\n #define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n-#define IAVF_QRX_TAIL1_MAX_INDEX 15\n-#define IAVF_QRX_TAIL1_TAIL_SHIFT 0\n-#define IAVF_QRX_TAIL1_TAIL_MASK IAVF_MASK(0x1FFF, IAVF_QRX_TAIL1_TAIL_SHIFT)\n #define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */\n-#define IAVF_QTX_TAIL1_MAX_INDEX 15\n-#define IAVF_QTX_TAIL1_TAIL_SHIFT 0\n-#define IAVF_QTX_TAIL1_TAIL_MASK IAVF_MASK(0x1FFF, IAVF_QTX_TAIL1_TAIL_SHIFT)\n-#define IAVFMSIX_PBA 0x00002000 /* Reset: VFLR */\n-#define IAVFMSIX_PBA_PENBIT_SHIFT 0\n-#define IAVFMSIX_PBA_PENBIT_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA_PENBIT_SHIFT)\n-#define IAVFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define IAVFMSIX_TADD_MAX_INDEX 16\n-#define IAVFMSIX_TADD_MSIXTADD10_SHIFT 0\n-#define IAVFMSIX_TADD_MSIXTADD10_MASK IAVF_MASK(0x3, IAVFMSIX_TADD_MSIXTADD10_SHIFT)\n-#define IAVFMSIX_TADD_MSIXTADD_SHIFT 2\n-#define IAVFMSIX_TADD_MSIXTADD_MASK IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD_MSIXTADD_SHIFT)\n-#define IAVFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define IAVFMSIX_TMSG_MAX_INDEX 16\n-#define IAVFMSIX_TMSG_MSIXTMSG_SHIFT 0\n-#define IAVFMSIX_TMSG_MSIXTMSG_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG_MSIXTMSG_SHIFT)\n-#define IAVFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define IAVFMSIX_TUADD_MAX_INDEX 16\n-#define IAVFMSIX_TUADD_MSIXTUADD_SHIFT 0\n-#define IAVFMSIX_TUADD_MSIXTUADD_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD_MSIXTUADD_SHIFT)\n-#define IAVFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n-#define IAVFMSIX_TVCTRL_MAX_INDEX 16\n-#define IAVFMSIX_TVCTRL_MASK_SHIFT 0\n-#define IAVFMSIX_TVCTRL_MASK_MASK IAVF_MASK(0x1, IAVFMSIX_TVCTRL_MASK_SHIFT)\n-#define IAVFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */\n-#define IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0\n-#define IAVFCM_PE_ERRDATA_ERROR_CODE_MASK IAVF_MASK(0xF, IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT)\n-#define IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT 4\n-#define IAVFCM_PE_ERRDATA_Q_TYPE_MASK IAVF_MASK(0x7, IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT)\n-#define IAVFCM_PE_ERRDATA_Q_NUM_SHIFT 8\n-#define IAVFCM_PE_ERRDATA_Q_NUM_MASK IAVF_MASK(0x3FFFF, IAVFCM_PE_ERRDATA_Q_NUM_SHIFT)\n-#define IAVFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */\n-#define IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0\n-#define IAVFCM_PE_ERRINFO_ERROR_VALID_MASK IAVF_MASK(0x1, IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT)\n-#define IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT 4\n-#define IAVFCM_PE_ERRINFO_ERROR_INST_MASK IAVF_MASK(0x7, IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT)\n-#define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8\n-#define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)\n-#define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16\n-#define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)\n-#define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24\n-#define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)\n-#define IAVFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n-#define IAVFQF_HENA_MAX_INDEX 1\n-#define IAVFQF_HENA_PTYPE_ENA_SHIFT 0\n-#define IAVFQF_HENA_PTYPE_ENA_MASK IAVF_MASK(0xFFFFFFFF, IAVFQF_HENA_PTYPE_ENA_SHIFT)\n-#define IAVFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n-#define IAVFQF_HKEY_MAX_INDEX 12\n-#define IAVFQF_HKEY_KEY_0_SHIFT 0\n-#define IAVFQF_HKEY_KEY_0_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_0_SHIFT)\n-#define IAVFQF_HKEY_KEY_1_SHIFT 8\n-#define IAVFQF_HKEY_KEY_1_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_1_SHIFT)\n-#define IAVFQF_HKEY_KEY_2_SHIFT 16\n-#define IAVFQF_HKEY_KEY_2_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_2_SHIFT)\n-#define IAVFQF_HKEY_KEY_3_SHIFT 24\n-#define IAVFQF_HKEY_KEY_3_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_3_SHIFT)\n-#define IAVFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n-#define IAVFQF_HLUT_MAX_INDEX 15\n-#define IAVFQF_HLUT_LUT0_SHIFT 0\n-#define IAVFQF_HLUT_LUT0_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT0_SHIFT)\n-#define IAVFQF_HLUT_LUT1_SHIFT 8\n-#define IAVFQF_HLUT_LUT1_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT1_SHIFT)\n-#define IAVFQF_HLUT_LUT2_SHIFT 16\n-#define IAVFQF_HLUT_LUT2_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT2_SHIFT)\n-#define IAVFQF_HLUT_LUT3_SHIFT 24\n-#define IAVFQF_HLUT_LUT3_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT3_SHIFT)\n-#define IAVFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */\n-#define IAVFQF_HREGION_MAX_INDEX 7\n-#define IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0\n-#define IAVFQF_HREGION_OVERRIDE_ENA_0_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT)\n-#define IAVFQF_HREGION_REGION_0_SHIFT 1\n-#define IAVFQF_HREGION_REGION_0_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_0_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4\n-#define IAVFQF_HREGION_OVERRIDE_ENA_1_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT)\n-#define IAVFQF_HREGION_REGION_1_SHIFT 5\n-#define IAVFQF_HREGION_REGION_1_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_1_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8\n-#define IAVFQF_HREGION_OVERRIDE_ENA_2_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT)\n-#define IAVFQF_HREGION_REGION_2_SHIFT 9\n-#define IAVFQF_HREGION_REGION_2_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_2_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12\n-#define IAVFQF_HREGION_OVERRIDE_ENA_3_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT)\n-#define IAVFQF_HREGION_REGION_3_SHIFT 13\n-#define IAVFQF_HREGION_REGION_3_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_3_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16\n-#define IAVFQF_HREGION_OVERRIDE_ENA_4_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT)\n-#define IAVFQF_HREGION_REGION_4_SHIFT 17\n-#define IAVFQF_HREGION_REGION_4_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_4_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20\n-#define IAVFQF_HREGION_OVERRIDE_ENA_5_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT)\n-#define IAVFQF_HREGION_REGION_5_SHIFT 21\n-#define IAVFQF_HREGION_REGION_5_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_5_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24\n-#define IAVFQF_HREGION_OVERRIDE_ENA_6_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT)\n-#define IAVFQF_HREGION_REGION_6_SHIFT 25\n-#define IAVFQF_HREGION_REGION_6_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_6_SHIFT)\n-#define IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28\n-#define IAVFQF_HREGION_OVERRIDE_ENA_7_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT)\n-#define IAVFQF_HREGION_REGION_7_SHIFT 29\n-#define IAVFQF_HREGION_REGION_7_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_7_SHIFT)\n-\n-#define IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30\n-#define IAVFINT_DYN_CTL01_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT)\n-#define IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n-#define IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)\n-#define IAVFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */\n-#define IAVFPE_AEQALLOC1_AECOUNT_SHIFT 0\n-#define IAVFPE_AEQALLOC1_AECOUNT_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_AEQALLOC1_AECOUNT_SHIFT)\n-#define IAVFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */\n-#define IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0\n-#define IAVFPE_CCQPHIGH1_PECCQPHIGH_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)\n-#define IAVFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */\n-#define IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT 0\n-#define IAVFPE_CCQPLOW1_PECCQPLOW_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT)\n-#define IAVFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */\n-#define IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0\n-#define IAVFPE_CCQPSTATUS1_CCQP_DONE_MASK IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)\n-#define IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4\n-#define IAVFPE_CCQPSTATUS1_HMC_PROFILE_MASK IAVF_MASK(0x7, IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)\n-#define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16\n-#define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK IAVF_MASK(0x3F, IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)\n-#define IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31\n-#define IAVFPE_CCQPSTATUS1_CCQP_ERR_MASK IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)\n-#define IAVFPE_CQACK1 0x0000B000 /* Reset: VFR */\n-#define IAVFPE_CQACK1_PECQID_SHIFT 0\n-#define IAVFPE_CQACK1_PECQID_MASK IAVF_MASK(0x1FFFF, IAVFPE_CQACK1_PECQID_SHIFT)\n-#define IAVFPE_CQARM1 0x0000B400 /* Reset: VFR */\n-#define IAVFPE_CQARM1_PECQID_SHIFT 0\n-#define IAVFPE_CQARM1_PECQID_MASK IAVF_MASK(0x1FFFF, IAVFPE_CQARM1_PECQID_SHIFT)\n-#define IAVFPE_CQPDB1 0x0000BC00 /* Reset: VFR */\n-#define IAVFPE_CQPDB1_WQHEAD_SHIFT 0\n-#define IAVFPE_CQPDB1_WQHEAD_MASK IAVF_MASK(0x7FF, IAVFPE_CQPDB1_WQHEAD_SHIFT)\n-#define IAVFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */\n-#define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0\n-#define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)\n-#define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16\n-#define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)\n-#define IAVFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */\n-#define IAVFPE_CQPTAIL1_WQTAIL_SHIFT 0\n-#define IAVFPE_CQPTAIL1_WQTAIL_MASK IAVF_MASK(0x7FF, IAVFPE_CQPTAIL1_WQTAIL_SHIFT)\n-#define IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31\n-#define IAVFPE_CQPTAIL1_CQP_OP_ERR_MASK IAVF_MASK(0x1, IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)\n-#define IAVFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */\n-#define IAVFPE_IPCONFIG01_PEIPID_SHIFT 0\n-#define IAVFPE_IPCONFIG01_PEIPID_MASK IAVF_MASK(0xFFFF, IAVFPE_IPCONFIG01_PEIPID_SHIFT)\n-#define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16\n-#define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_MASK IAVF_MASK(0x1, IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)\n-#define IAVFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */\n-#define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0\n-#define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK IAVF_MASK(0x1F, IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)\n-#define IAVFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */\n-#define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0\n-#define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK IAVF_MASK(0xFFFFFF, IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)\n-#define IAVFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */\n-#define IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0\n-#define IAVFPE_TCPNOWTIMER1_TCP_NOW_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)\n-#define IAVFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */\n-#define IAVFPE_WQEALLOC1_PEQPID_SHIFT 0\n-#define IAVFPE_WQEALLOC1_PEQPID_MASK IAVF_MASK(0x3FFFF, IAVFPE_WQEALLOC1_PEQPID_SHIFT)\n-#define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20\n-#define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_MASK IAVF_MASK(0xFFF, IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)\n+#define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n+#define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n+#define IAVF_VFQF_HKEY_MAX_INDEX 12\n+#define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n+#define IAVF_VFQF_HLUT_MAX_INDEX 15\n+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)\n \n #endif /* _IAVF_REGISTER_H_ */\ndiff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c\nindex 4f80113ae..39faf7fac 100644\n--- a/drivers/net/iavf/iavf_ethdev.c\n+++ b/drivers/net/iavf/iavf_ethdev.c\n@@ -323,9 +323,10 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n \t\t VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {\n \t\t\t/* If WB_ON_ITR supports, enable it */\n \t\t\tvf->msix_base = IAVF_RX_VEC_START;\n-\t\t\tIAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(vf->msix_base - 1),\n-\t\t\t\t IAVFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t\t IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK);\n+\t\t\tIAVF_WRITE_REG(hw,\n+\t\t\t\t IAVF_VFINT_DYN_CTLN1(vf->msix_base - 1),\n+\t\t\t\t IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n+\t\t\t\t IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);\n \t\t} else {\n \t\t\t/* If no WB_ON_ITR offload flags, need to set\n \t\t\t * interrupt for descriptor write back.\n@@ -335,12 +336,12 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n \t\t\t/* set ITR to max */\n \t\t\tinterval = iavf_calc_itr_interval(\n \t\t\t\t\tIAVF_QUEUE_ITR_INTERVAL_MAX);\n-\t\t\tIAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,\n-\t\t\t\t IAVFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t\t (IAVF_ITR_INDEX_DEFAULT <<\n-\t\t\t\t IAVFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n-\t\t\t\t (interval <<\n-\t\t\t\t IAVFINT_DYN_CTL01_INTERVAL_SHIFT));\n+\t\t\tIAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,\n+\t\t\t\t IAVF_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t\t (IAVF_ITR_INDEX_DEFAULT <<\n+\t\t\t\t\tIAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |\n+\t\t\t\t (interval <<\n+\t\t\t\t\tIAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));\n \t\t}\n \t\tIAVF_WRITE_FLUSH(hw);\n \t\t/* map all queues to the same interrupt */\n@@ -1115,16 +1116,17 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n \tmsix_intr = pci_dev->intr_handle.intr_vec[queue_id];\n \tif (msix_intr == IAVF_MISC_VEC_ID) {\n \t\tPMD_DRV_LOG(INFO, \"MISC is also enabled for control\");\n-\t\tIAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,\n-\t\t\t IAVFINT_DYN_CTL01_INTENA_MASK |\n-\t\t\t IAVFINT_DYN_CTL01_CLEARPBA_MASK |\n-\t\t\t IAVFINT_DYN_CTL01_ITR_INDX_MASK);\n+\t\tIAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,\n+\t\t\t IAVF_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t\t IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |\n+\t\t\t IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);\n \t} else {\n \t\tIAVF_WRITE_REG(hw,\n-\t\t\t IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),\n-\t\t\t IAVFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t IAVFINT_DYN_CTL01_CLEARPBA_MASK |\n-\t\t\t IAVFINT_DYN_CTLN1_ITR_INDX_MASK);\n+\t\t\t IAVF_VFINT_DYN_CTLN1\n+\t\t\t\t(msix_intr - IAVF_RX_VEC_START),\n+\t\t\t IAVF_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |\n+\t\t\t IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK);\n \t}\n \n \tIAVF_WRITE_FLUSH(hw);\n@@ -1148,7 +1150,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n \t}\n \n \tIAVF_WRITE_REG(hw,\n-\t\t IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),\n+\t\t IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),\n \t\t 0);\n \n \tIAVF_WRITE_FLUSH(hw);\n@@ -1161,9 +1163,9 @@ iavf_check_vf_reset_done(struct iavf_hw *hw)\n \tint i, reset;\n \n \tfor (i = 0; i < IAVF_RESET_WAIT_CNT; i++) {\n-\t\treset = IAVF_READ_REG(hw, IAVFGEN_RSTAT) &\n-\t\t\tIAVFGEN_RSTAT_VFR_STATE_MASK;\n-\t\treset = reset >> IAVFGEN_RSTAT_VFR_STATE_SHIFT;\n+\t\treset = IAVF_READ_REG(hw, IAVF_VFGEN_RSTAT) &\n+\t\t\tIAVF_VFGEN_RSTAT_VFR_STATE_MASK;\n+\t\treset = reset >> IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT;\n \t\tif (reset == VIRTCHNL_VFR_VFACTIVE ||\n \t\t reset == VIRTCHNL_VFR_COMPLETED)\n \t\t\tbreak;\n@@ -1260,10 +1262,13 @@ static inline void\n iavf_enable_irq0(struct iavf_hw *hw)\n {\n \t/* Enable admin queue interrupt trigger */\n-\tIAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, IAVFINT_ICR0_ENA1_ADMINQ_MASK);\n+\tIAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1,\n+\t\t IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK);\n \n-\tIAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01, IAVFINT_DYN_CTL01_INTENA_MASK |\n-\t\tIAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTL01_ITR_INDX_MASK);\n+\tIAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,\n+\t\t IAVF_VFINT_DYN_CTL01_INTENA_MASK |\n+\t\t IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |\n+\t\t IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);\n \n \tIAVF_WRITE_FLUSH(hw);\n }\n@@ -1272,9 +1277,9 @@ static inline void\n iavf_disable_irq0(struct iavf_hw *hw)\n {\n \t/* Disable all interrupt types */\n-\tIAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, 0);\n-\tIAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,\n-\t\t IAVFINT_DYN_CTL01_ITR_INDX_MASK);\n+\tIAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1, 0);\n+\tIAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,\n+\t\t IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);\n \tIAVF_WRITE_FLUSH(hw);\n }\n \n", "prefixes": [ "03/17" ] }