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GET /api/patches/63010/?format=api
{ "id": 63010, "url": "http://patches.dpdk.org/api/patches/63010/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1573722187-148846-14-git-send-email-rosen.xu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1573722187-148846-14-git-send-email-rosen.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1573722187-148846-14-git-send-email-rosen.xu@intel.com", "date": "2019-11-14T09:03:01", "name": "[v18,13/19] raw/ifpga/base: add secure support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fd6bc6b30c821dc377e1538d15dde4423609d498", "submitter": { "id": 946, "url": "http://patches.dpdk.org/api/people/946/?format=api", "name": "Xu, Rosen", "email": "rosen.xu@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1573722187-148846-14-git-send-email-rosen.xu@intel.com/mbox/", "series": [ { "id": 7455, "url": "http://patches.dpdk.org/api/series/7455/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7455", "date": "2019-11-14T09:02:48", "name": "add PCIe AER disable and IRQ support for ipn3ke", "version": 18, "mbox": "http://patches.dpdk.org/series/7455/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63010/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/63010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DBC2BA04C2;\n\tThu, 14 Nov 2019 10:06:31 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 044AA1BEEA;\n\tThu, 14 Nov 2019 10:04:59 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 136651BEC9\n for <dev@dpdk.org>; Thu, 14 Nov 2019 10:04:50 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 14 Nov 2019 01:04:50 -0800", "from dpdk-rosen-02.sh.intel.com ([10.67.110.156])\n by fmsmga006.fm.intel.com with ESMTP; 14 Nov 2019 01:04:49 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.68,302,1569308400\"; d=\"scan'208\";a=\"406259596\"", "From": "Rosen Xu <rosen.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "rosen.xu@intel.com, tianfei.zhang@intel.com, andy.pei@intel.com,\n xiaolong.ye@intel.com, ferruh.yigit@intel.com", "Date": "Thu, 14 Nov 2019 17:03:01 +0800", "Message-Id": "<1573722187-148846-14-git-send-email-rosen.xu@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1573722187-148846-1-git-send-email-rosen.xu@intel.com>", "References": "<1571917119-149534-2-git-send-email-andy.pei@intel.com>\n <1573722187-148846-1-git-send-email-rosen.xu@intel.com>", "Subject": "[dpdk-dev] [PATCH v18 13/19] raw/ifpga/base: add secure support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tianfei zhang <tianfei.zhang@intel.com>\n\nAdd secure max10 device support.\n\nSigned-off-by: Tianfei zhang <tianfei.zhang@intel.com>\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_defines.h | 2 +\n drivers/raw/ifpga/base/ifpga_fme.c | 26 ++++--\n drivers/raw/ifpga/base/opae_intel_max10.c | 137 +++++++++++++++++++++++++-----\n drivers/raw/ifpga/base/opae_intel_max10.h | 80 ++++++++++++-----\n 4 files changed, 198 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/raw/ifpga/base/ifpga_defines.h b/drivers/raw/ifpga/base/ifpga_defines.h\nindex 8993cc6..1e84b15 100644\n--- a/drivers/raw/ifpga/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga/base/ifpga_defines.h\n@@ -1698,6 +1698,8 @@ struct ifpga_fme_board_info {\n \tu32 patch_version;\n \tu32 minor_version;\n \tu32 major_version;\n+\tu32 max10_version;\n+\tu32 nios_fw_version;\n \tu32 nums_of_retimer;\n \tu32 ports_per_retimer;\n \tu32 nums_of_fvl;\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c\nindex 794ca09..87fa596 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme.c\n@@ -825,6 +825,7 @@ static int board_type_to_info(u32 type,\n static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n {\n \tstruct fme_bitstream_id id;\n+\tu32 val;\n \n \tif (fme_hdr_get_bitstream_id(fme, &id.id))\n \t\treturn -EINVAL;\n@@ -850,6 +851,18 @@ static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n \t\t\tfme->board_info.nums_of_fvl,\n \t\t\tfme->board_info.ports_per_fvl);\n \n+\tif (max10_sys_read(MAX10_BUILD_VER, &val))\n+\t\treturn -EINVAL;\n+\tfme->board_info.max10_version = val & 0xffffff;\n+\n+\tif (max10_sys_read(NIOS2_FW_VERSION, &val))\n+\t\treturn -EINVAL;\n+\tfme->board_info.nios_fw_version = val & 0xffffff;\n+\n+\tdev_info(fme, \"max10 version 0x%x, nios fw version 0x%x\\n\",\n+\t\tfme->board_info.max10_version,\n+\t\tfme->board_info.nios_fw_version);\n+\n \treturn 0;\n }\n \n@@ -858,16 +871,11 @@ static int spi_self_checking(void)\n \tu32 val;\n \tint ret;\n \n-\tret = max10_reg_read(0x30043c, &val);\n+\tret = max10_sys_read(MAX10_TEST_REG, &val);\n \tif (ret)\n \t\treturn -EIO;\n \n-\tif (val != 0x87654321) {\n-\t\tdev_err(NULL, \"Read MAX10 test register fail: 0x%x\\n\", val);\n-\t\treturn -EIO;\n-\t}\n-\n-\tdev_info(NULL, \"Read MAX10 test register success, SPI self-test done\\n\");\n+\tdev_info(NULL, \"Read MAX10 test register 0x%x\\n\", val);\n \n \treturn 0;\n }\n@@ -1283,7 +1291,7 @@ int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,\n \tif (!dev)\n \t\treturn -ENODEV;\n \n-\tif (max10_reg_read(PKVL_LINK_STATUS, &val)) {\n+\tif (max10_sys_read(PKVL_LINK_STATUS, &val)) {\n \t\tdev_err(dev, \"%s: read pkvl status fail\\n\", __func__);\n \t\treturn -EINVAL;\n \t}\n@@ -1311,7 +1319,7 @@ int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,\n \tif (!dev)\n \t\treturn -ENODEV;\n \n-\tif (max10_reg_read(sensor->value_reg, value)) {\n+\tif (max10_sys_read(sensor->value_reg, value)) {\n \t\tdev_err(dev, \"%s: read sensor value register 0x%x fail\\n\",\n \t\t\t\t__func__, sensor->value_reg);\n \t\treturn -EINVAL;\ndiff --git a/drivers/raw/ifpga/base/opae_intel_max10.c b/drivers/raw/ifpga/base/opae_intel_max10.c\nindex ae7a8df..748ab56 100644\n--- a/drivers/raw/ifpga/base/opae_intel_max10.c\n+++ b/drivers/raw/ifpga/base/opae_intel_max10.c\n@@ -30,6 +30,22 @@ int max10_reg_write(unsigned int reg, unsigned int val)\n \t\t\treg, 4, (unsigned char *)&tmp);\n }\n \n+int max10_sys_read(unsigned int offset, unsigned int *val)\n+{\n+\tif (!g_max10)\n+\t\treturn -ENODEV;\n+\n+\treturn max10_reg_read(g_max10->base + offset, val);\n+}\n+\n+int max10_sys_write(unsigned int offset, unsigned int val)\n+{\n+\tif (!g_max10)\n+\t\treturn -ENODEV;\n+\n+\treturn max10_reg_write(g_max10->base + offset, val);\n+}\n+\n static struct max10_compatible_id max10_id_table[] = {\n \t{.compatible = MAX10_PAC,},\n \t{.compatible = MAX10_PAC_N3000,},\n@@ -66,7 +82,8 @@ static void max10_check_capability(struct intel_max10_device *max10)\n \t\tmax10->flags |= MAX10_FLAGS_NO_I2C2 |\n \t\t\t\tMAX10_FLAGS_NO_BMCIMG_FLASH;\n \t\tdev_info(max10, \"found %s card\\n\", max10->id->compatible);\n-\t}\n+\t} else\n+\t\tmax10->flags |= MAX10_FLAGS_MAC_CACHE;\n }\n \n static int altera_nor_flash_read(u32 offset,\n@@ -100,7 +117,7 @@ static int enable_nor_flash(bool on)\n \tunsigned int val = 0;\n \tint ret;\n \n-\tret = max10_reg_read(RSU_REG_OFF, &val);\n+\tret = max10_sys_read(RSU_REG, &val);\n \tif (ret) {\n \t\tdev_err(NULL \"enabling flash error\\n\");\n \t\treturn ret;\n@@ -111,7 +128,7 @@ static int enable_nor_flash(bool on)\n \telse\n \t\tval &= ~RSU_ENABLE;\n \n-\treturn max10_reg_write(RSU_REG_OFF, val);\n+\treturn max10_sys_write(RSU_REG, val);\n }\n \n static int init_max10_device_table(struct intel_max10_device *max10)\n@@ -123,7 +140,7 @@ static int init_max10_device_table(struct intel_max10_device *max10)\n \tu32 dt_size, dt_addr, val;\n \tint ret;\n \n-\tret = max10_reg_read(DT_AVAIL_REG_OFF, &val);\n+\tret = max10_sys_read(DT_AVAIL_REG, &val);\n \tif (ret) {\n \t\tdev_err(max10 \"cannot read DT_AVAIL_REG\\n\");\n \t\treturn ret;\n@@ -134,7 +151,7 @@ static int init_max10_device_table(struct intel_max10_device *max10)\n \t\treturn -EINVAL;\n \t}\n \n-\tret = max10_reg_read(DT_BASE_ADDR_REG_OFF, &dt_addr);\n+\tret = max10_sys_read(DT_BASE_ADDR_REG, &dt_addr);\n \tif (ret) {\n \t\tdev_info(max10 \"cannot get base addr of device table\\n\");\n \t\treturn ret;\n@@ -315,7 +332,7 @@ static int max10_add_sensor(struct raw_sensor_info *info,\n \t\tif (!sensor_reg_valid(&info->regs[i]))\n \t\t\tcontinue;\n \n-\t\tret = max10_reg_read(info->regs[i].regoff, &val);\n+\t\tret = max10_sys_read(info->regs[i].regoff, &val);\n \t\tif (ret)\n \t\t\tbreak;\n \n@@ -355,7 +372,8 @@ static int max10_add_sensor(struct raw_sensor_info *info,\n \treturn ret;\n }\n \n-static int max10_sensor_init(struct intel_max10_device *dev)\n+static int\n+max10_sensor_init(struct intel_max10_device *dev, int parent)\n {\n \tint i, ret = 0, offset = 0;\n \tconst fdt32_t *num;\n@@ -370,7 +388,7 @@ static int max10_sensor_init(struct intel_max10_device *dev)\n \t\treturn 0;\n \t}\n \n-\tfdt_for_each_subnode(offset, fdt_root, 0) {\n+\tfdt_for_each_subnode(offset, fdt_root, parent) {\n \t\tptr = fdt_get_name(fdt_root, offset, NULL);\n \t\tif (!ptr) {\n \t\t\tdev_err(dev, \"failed to fdt get name\\n\");\n@@ -417,7 +435,16 @@ static int max10_sensor_init(struct intel_max10_device *dev)\n \t\t\t\tcontinue;\n \t\t\t}\n \n-\t\t\traw->regs[i].regoff = start;\n+\t\t\t/* This is a hack to compatible with non-secure\n+\t\t\t * solution. If sensors are included in root node,\n+\t\t\t * then it's non-secure dtb, which use absolute addr\n+\t\t\t * of non-secure solution.\n+\t\t\t */\n+\t\t\tif (parent)\n+\t\t\t\traw->regs[i].regoff = start;\n+\t\t\telse\n+\t\t\t\traw->regs[i].regoff = start -\n+\t\t\t\t\tMAX10_BASE_ADDR;\n \t\t\traw->regs[i].size = size;\n \t\t}\n \n@@ -469,6 +496,63 @@ static int max10_sensor_init(struct intel_max10_device *dev)\n \treturn ret;\n }\n \n+static int check_max10_version(struct intel_max10_device *dev)\n+{\n+\tunsigned int v;\n+\n+\tif (!max10_reg_read(MAX10_SEC_BASE_ADDR + MAX10_BUILD_VER,\n+\t\t\t\t&v)) {\n+\t\tif (v != 0xffffffff) {\n+\t\t\tdev_info(dev, \"secure MAX10 detected\\n\");\n+\t\t\tdev->base = MAX10_SEC_BASE_ADDR;\n+\t\t\tdev->flags |= MAX10_FLAGS_SECURE;\n+\t\t} else {\n+\t\t\tdev_info(dev, \"non-secure MAX10 detected\\n\");\n+\t\t\tdev->base = MAX10_BASE_ADDR;\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\treturn -ENODEV;\n+}\n+\n+static int\n+max10_secure_hw_init(struct intel_max10_device *dev)\n+{\n+\tint offset, sysmgr_offset = 0;\n+\tchar *fdt_root;\n+\n+\tfdt_root = dev->fdt_root;\n+\tif (!fdt_root) {\n+\t\tdev_debug(dev, \"skip init as not find Device Tree\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tfdt_for_each_subnode(offset, fdt_root, 0) {\n+\t\tif (!fdt_node_check_compatible(fdt_root, offset,\n+\t\t\t\t\t\"intel-max10,system-manager\")) {\n+\t\t\tsysmgr_offset = offset;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tmax10_check_capability(dev);\n+\n+\tmax10_sensor_init(dev, sysmgr_offset);\n+\n+\treturn 0;\n+}\n+\n+static int\n+max10_non_secure_hw_init(struct intel_max10_device *dev)\n+{\n+\tmax10_check_capability(dev);\n+\n+\tmax10_sensor_init(dev, 0);\n+\n+\treturn 0;\n+}\n+\n struct intel_max10_device *\n intel_max10_device_probe(struct altera_spi_device *spi,\n \t\tint chipselect)\n@@ -492,32 +576,47 @@ struct intel_max10_device *\n \t/* set the max10 device firstly */\n \tg_max10 = dev;\n \n-\t/* init the MAX10 device table */\n+\t/* check the max10 version */\n+\tret = check_max10_version(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to find max10 hardware!\\n\");\n+\t\tgoto free_dev;\n+\t}\n+\n+\t/* load the MAX10 device table */\n \tret = init_max10_device_table(dev);\n \tif (ret) {\n-\t\tdev_err(dev, \"init max10 device table fail\\n\");\n+\t\tdev_err(dev, \"Init max10 device table fail\\n\");\n \t\tgoto free_dev;\n \t}\n \n-\tmax10_check_capability(dev);\n+\t/* init max10 devices, like sensor*/\n+\tif (dev->flags & MAX10_FLAGS_SECURE)\n+\t\tret = max10_secure_hw_init(dev);\n+\telse\n+\t\tret = max10_non_secure_hw_init(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to init max10 hardware!\\n\");\n+\t\tgoto free_dtb;\n+\t}\n \n \t/* read FPGA loading information */\n-\tret = max10_reg_read(FPGA_PAGE_INFO_OFF, &val);\n+\tret = max10_sys_read(FPGA_PAGE_INFO, &val);\n \tif (ret) {\n \t\tdev_err(dev, \"fail to get FPGA loading info\\n\");\n-\t\tgoto spi_tran_fail;\n+\t\tgoto release_max10_hw;\n \t}\n \tdev_info(dev, \"FPGA loaded from %s Image\\n\", val ? \"User\" : \"Factory\");\n \n-\n-\tmax10_sensor_init(dev);\n-\n \treturn dev;\n \n-spi_tran_fail:\n+release_max10_hw:\n+\tmax10_sensor_uinit();\n+free_dtb:\n \tif (dev->fdt_root)\n \t\topae_free(dev->fdt_root);\n-\tspi_transaction_remove(dev->spi_tran_dev);\n+\tif (dev->spi_tran_dev)\n+\t\tspi_transaction_remove(dev->spi_tran_dev);\n free_dev:\n \tg_max10 = NULL;\n \topae_free(dev);\ndiff --git a/drivers/raw/ifpga/base/opae_intel_max10.h b/drivers/raw/ifpga/base/opae_intel_max10.h\nindex 90bf098..e632941 100644\n--- a/drivers/raw/ifpga/base/opae_intel_max10.h\n+++ b/drivers/raw/ifpga/base/opae_intel_max10.h\n@@ -23,6 +23,8 @@ struct max10_compatible_id {\n #define MAX10_FLAGS_SPI BIT(3)\n #define MAX10_FLGAS_NIOS_SPI BIT(4)\n #define MAX10_FLAGS_PKVL BIT(5)\n+#define MAX10_FLAGS_SECURE\t\tBIT(6)\n+#define MAX10_FLAGS_MAC_CACHE\t\tBIT(7)\n \n struct intel_max10_device {\n \tunsigned int flags; /*max10 hardware capability*/\n@@ -30,6 +32,7 @@ struct intel_max10_device {\n \tstruct spi_transaction_dev *spi_tran_dev;\n \tstruct max10_compatible_id *id; /*max10 compatible*/\n \tchar *fdt_root;\n+\tunsigned int base; /* max10 base address */\n };\n \n /* retimer speed */\n@@ -74,30 +77,69 @@ struct opae_retimer_status {\n #define FLASH_BASE 0x10000000\n #define FLASH_OPTION_BITS 0x10000\n \n-#define NIOS2_FW_VERSION_OFF 0x300400\n-#define RSU_REG_OFF 0x30042c\n-#define FPGA_RP_LOAD\t\tBIT(3)\n-#define NIOS2_PRERESET\t\tBIT(4)\n-#define NIOS2_HANG\t\tBIT(5)\n-#define RSU_ENABLE\t\tBIT(6)\n-#define NIOS2_RESET\t\tBIT(7)\n-#define NIOS2_I2C2_POLL_STOP\tBIT(13)\n-#define FPGA_RECONF_REG_OFF\t0x300430\n-#define COUNTDOWN_START\t\tBIT(18)\n-#define MAX10_BUILD_VER_OFF\t0x300468\n-#define PCB_INFO\t\tGENMASK(31, 24)\n-#define MAX10_BUILD_VERION\tGENMASK(23, 0)\n-#define FPGA_PAGE_INFO_OFF\t0x30046c\n-#define DT_AVAIL_REG_OFF\t0x300490\n-#define DT_AVAIL\t\tBIT(0)\n-#define DT_BASE_ADDR_REG_OFF\t0x300494\n-#define PKVL_POLLING_CTRL 0x300480\n-#define PKVL_LINK_STATUS 0x300564\n+/* System Registers */\n+#define MAX10_BASE_ADDR\t\t0x300400\n+#define MAX10_SEC_BASE_ADDR\t0x300800\n+/* Register offset of system registers */\n+#define NIOS2_FW_VERSION\t0x0\n+#define MAX10_MACADDR1\t\t0x10\n+#define MAX10_MAC_BYTE4\tGENMASK(7, 0)\n+#define MAX10_MAC_BYTE3\tGENMASK(15, 8)\n+#define MAX10_MAC_BYTE2\tGENMASK(23, 16)\n+#define MAX10_MAC_BYTE1\tGENMASK(31, 24)\n+#define MAX10_MACADDR2\t\t0x14\n+#define MAX10_MAC_BYTE6\tGENMASK(7, 0)\n+#define MAX10_MAC_BYTE5\tGENMASK(15, 8)\n+#define MAX10_MAC_COUNT\tGENMASK(23, 16)\n+#define RSU_REG\t\t\t0x2c\n+#define FPGA_RECONF_PAGE\tGENMASK(2, 0)\n+#define FPGA_RP_LOAD\t\tBIT(3)\n+#define NIOS2_PRERESET\tBIT(4)\n+#define NIOS2_HANG\t\tBIT(5)\n+#define RSU_ENABLE\t\tBIT(6)\n+#define NIOS2_RESET\t\tBIT(7)\n+#define NIOS2_I2C2_POLL_STOP\tBIT(13)\n+#define PKVL_EEPROM_LOAD\tBIT(31)\n+#define FPGA_RECONF_REG\t\t0x30\n+#define MAX10_TEST_REG\t\t0x3c\n+#define COUNTDOWN_START\tBIT(18)\n+#define MAX10_BUILD_VER\t\t0x68\n+#define MAX10_VERSION_MAJOR\tGENMASK(23, 16)\n+#define PCB_INFO\t\tGENMASK(31, 24)\n+#define FPGA_PAGE_INFO\t\t0x6c\n+#define DT_AVAIL_REG\t\t0x90\n+#define DT_AVAIL\t\tBIT(0)\n+#define DT_BASE_ADDR_REG\t0x94\n+#define MAX10_DOORBELL\t\t0x400\n+#define RSU_REQUEST\t\tBIT(0)\n+#define SEC_PROGRESS\t\tGENMASK(7, 4)\n+#define HOST_STATUS\t\tGENMASK(11, 8)\n+#define SEC_STATUS\t\tGENMASK(23, 16)\n+\n+/* PKVL related registers, in system register region */\n+#define PKVL_POLLING_CTRL\t\t0x80\n+#define POLLING_MODE\t\t\tGENMASK(15, 0)\n+#define PKVL_A_PRELOAD\t\tBIT(16)\n+#define PKVL_A_PRELOAD_TIMEOUT\tBIT(17)\n+#define PKVL_A_DATA_TOO_BIG\t\tBIT(18)\n+#define PKVL_A_HDR_CHECKSUM\t\tBIT(20)\n+#define PKVL_B_PRELOAD\t\tBIT(24)\n+#define PKVL_B_PRELOAD_TIMEOUT\tBIT(25)\n+#define PKVL_B_DATA_TOO_BIG\t\tBIT(26)\n+#define PKVL_B_HDR_CHECKSUM\t\tBIT(28)\n+#define PKVL_EEPROM_UPG_STATUS\tGENMASK(31, 16)\n+#define PKVL_LINK_STATUS\t\t0x164\n+#define PKVL_A_VERSION\t\t\t0x254\n+#define PKVL_B_VERSION\t\t\t0x258\n+#define SERDES_VERSION\t\tGENMASK(15, 0)\n+#define SBUS_VERSION\t\t\tGENMASK(31, 16)\n \n #define DFT_MAX_SIZE\t\t0x7e0000\n \n int max10_reg_read(unsigned int reg, unsigned int *val);\n int max10_reg_write(unsigned int reg, unsigned int val);\n+int max10_sys_read(unsigned int offset, unsigned int *val);\n+int max10_sys_write(unsigned int offset, unsigned int val);\n struct intel_max10_device *\n intel_max10_device_probe(struct altera_spi_device *spi,\n \t\tint chipselect);\n", "prefixes": [ "v18", "13/19" ] }