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{
    "id": 630,
    "url": "http://patches.dpdk.org/api/patches/630/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1411974986-28137-10-git-send-email-changchun.ouyang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1411974986-28137-10-git-send-email-changchun.ouyang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-10-git-send-email-changchun.ouyang@intel.com",
    "date": "2014-09-29T07:16:17",
    "name": "[dpdk-dev,v2,09/18] ixgbe: Support new device id 82599_QSFP and 82599_LS",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "bfb92ded38bce5ebd47766f40ca32b14f8dd7170",
    "submitter": {
        "id": 31,
        "url": "http://patches.dpdk.org/api/people/31/?format=api",
        "name": "Ouyang Changchun",
        "email": "changchun.ouyang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1411974986-28137-10-git-send-email-changchun.ouyang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/630/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/630/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 32A457E60;\n\tMon, 29 Sep 2014 09:10:43 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id E96F87E4B\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:37 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga101.fm.intel.com with ESMTP; 29 Sep 2014 00:17:10 -0700",
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            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7H4tn028398; Mon, 29 Sep 2014 15:17:06 +0800",
            "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7H4RH028394; \n\tMon, 29 Sep 2014 15:17:04 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"606847751\"",
        "From": "Ouyang Changchun <changchun.ouyang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Mon, 29 Sep 2014 15:16:17 +0800",
        "Message-Id": "<1411974986-28137-10-git-send-email-changchun.ouyang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>",
        "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 09/18] ixgbe: Support new device id 82599_QSFP\n\tand 82599_LS",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
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        "List-Post": "<mailto:dev@dpdk.org>",
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        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch support new device id 82599_QSFP and 82599_LS in IXGBE\nbase code.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c  |  79 +++--\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c    |   2 +\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c |   8 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c    | 481 ++++++++++++++++++++++++++++--\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h    |  18 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h   |  24 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c     |  15 +\n 7 files changed, 541 insertions(+), 86 deletions(-)",
    "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex 277cc25..3e442f7 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -111,9 +111,27 @@ s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)\n \tstruct ixgbe_mac_info *mac = &hw->mac;\n \tstruct ixgbe_phy_info *phy = &hw->phy;\n \ts32 ret_val = IXGBE_SUCCESS;\n+\tu32 esdp;\n \n \tDEBUGFUNC(\"ixgbe_init_phy_ops_82599\");\n \n+\tif (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {\n+\t\t/* Store flag indicating I2C bus access control unit. */\n+\t\thw->phy.qsfp_shared_i2c_bus = TRUE;\n+\n+\t\t/* Initialize access to QSFP+ I2C bus */\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tesdp |= IXGBE_ESDP_SDP0_DIR;\n+\t\tesdp &= ~IXGBE_ESDP_SDP1_DIR;\n+\t\tesdp &= ~IXGBE_ESDP_SDP0;\n+\t\tesdp &= ~IXGBE_ESDP_SDP0_NATIVE;\n+\t\tesdp &= ~IXGBE_ESDP_SDP1_NATIVE;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t\tIXGBE_WRITE_FLUSH(hw);\n+\n+\t\tphy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;\n+\t\tphy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;\n+\t}\n \t/* Identify the PHY or SFP module */\n \tret_val = phy->ops.identify(hw);\n \tif (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)\n@@ -397,10 +415,8 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n \t/* Check if 1G SFP module. */\n \tif (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n \t    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n-#ifdef SUPPORT_1000BASE_LX\n \t    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n \t    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n-#endif\n \t    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n \t    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {\n \t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n@@ -477,7 +493,13 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n \t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL |\n \t\t\t  IXGBE_LINK_SPEED_1GB_FULL;\n \n-\t\t*autoneg = true;\n+\t\t/* QSFP must not enable full auto-negotiation\n+\t\t * Limited autoneg is enabled at 1G\n+\t\t */\n+\t\tif (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)\n+\t\t\t*autoneg = false;\n+\t\telse\n+\t\t\t*autoneg = true;\n \t}\n \n out:\n@@ -530,6 +552,12 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)\n \tcase IXGBE_DEV_ID_82599_T3_LOM:\n \t\tmedia_type = ixgbe_media_type_copper;\n \t\tbreak;\n+\tcase IXGBE_DEV_ID_82599_LS:\n+\t\tmedia_type = ixgbe_media_type_fiber_lco;\n+\t\tbreak;\n+\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n+\t\tmedia_type = ixgbe_media_type_fiber_qsfp;\n+\t\tbreak;\n \tdefault:\n \t\tmedia_type = ixgbe_media_type_unknown;\n \t\tbreak;\n@@ -755,6 +783,9 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n \t\t\tIXGBE_WRITE_FLUSH(hw);\n \t\t\tbreak;\n+\t\tcase ixgbe_media_type_fiber_qsfp:\n+\t\t\t/* QSFP module automatically detects MAC link speed */\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDEBUGOUT(\"Unexpected media type.\\n\");\n \t\t\tbreak;\n@@ -813,6 +844,9 @@ s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n \t\t\tIXGBE_WRITE_FLUSH(hw);\n \t\t\tbreak;\n+\t\tcase ixgbe_media_type_fiber_qsfp:\n+\t\t\t/* QSFP module automatically detects link speed */\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDEBUGOUT(\"Unexpected media type.\\n\");\n \t\t\tbreak;\n@@ -1052,7 +1086,7 @@ s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,\n \t\tif ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&\n \t\t    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {\n \t\t\tautoc &= ~IXGBE_AUTOC_LMS_MASK;\n-\t\t\tif (autoneg)\n+\t\t\tif (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)\n \t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_AN;\n \t\t\telse\n \t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;\n@@ -2204,8 +2238,6 @@ u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)\n \tu32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;\n \tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n \tu16 ext_ability = 0;\n-\tu8 comp_codes_10g = 0;\n-\tu8 comp_codes_1g = 0;\n \n \tDEBUGFUNC(\"ixgbe_get_support_physical_layer_82599\");\n \n@@ -2273,40 +2305,7 @@ sfp_check:\n \t/* SFP check must be done last since DA modules are sometimes used to\n \t * test KR mode -  we need to id KR mode correctly before SFP module.\n \t * Call identify_sfp because the pluggable module may have changed */\n-\thw->phy.ops.identify_sfp(hw);\n-\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n-\t\tgoto out;\n-\n-\tswitch (hw->phy.type) {\n-\tcase ixgbe_phy_sfp_passive_tyco:\n-\tcase ixgbe_phy_sfp_passive_unknown:\n-\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n-\t\tbreak;\n-\tcase ixgbe_phy_sfp_ftl_active:\n-\tcase ixgbe_phy_sfp_active_unknown:\n-\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;\n-\t\tbreak;\n-\tcase ixgbe_phy_sfp_avago:\n-\tcase ixgbe_phy_sfp_ftl:\n-\tcase ixgbe_phy_sfp_intel:\n-\tcase ixgbe_phy_sfp_unknown:\n-\t\thw->phy.ops.read_i2c_eeprom(hw,\n-\t\t      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);\n-\t\thw->phy.ops.read_i2c_eeprom(hw,\n-\t\t      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);\n-\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n-\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n-\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n-\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n-\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)\n-\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;\n-\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)\n-\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n+\tphysical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);\n out:\n \treturn physical_layer;\n }\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\nindex 378304f..8ed4b75 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n@@ -138,8 +138,10 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n \tcase IXGBE_DEV_ID_82599_SFP_EM:\n \tcase IXGBE_DEV_ID_82599_SFP_SF2:\n \tcase IXGBE_DEV_ID_82599_SFP_SF_QP:\n+\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n \tcase IXGBE_DEV_ID_82599EN_SFP:\n \tcase IXGBE_DEV_ID_82599_CX4:\n+\tcase IXGBE_DEV_ID_82599_LS:\n \tcase IXGBE_DEV_ID_82599_T3_LOM:\n \t\thw->mac.type = ixgbe_mac_82599EB;\n \t\tbreak;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex 850c12d..833aae9 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -165,6 +165,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \tDEBUGFUNC(\"ixgbe_device_supports_autoneg_fc\");\n \n \tswitch (hw->phy.media_type) {\n+\tcase ixgbe_media_type_fiber_qsfp:\n \tcase ixgbe_media_type_fiber:\n \t\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n \t\t/* if link is down, assume supported */\n@@ -213,10 +214,7 @@ STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)\n \n \tDEBUGFUNC(\"ixgbe_setup_fc\");\n \n-\t/*\n-\t * Validate the requested mode.  Strict IEEE mode does not allow\n-\t * ixgbe_fc_rx_pause because it will cause us to fail at UNH.\n-\t */\n+\t/* Validate the requested mode */\n \tif (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {\n \t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,\n \t\t\t   \"ixgbe_fc_rx_pause not valid in strict IEEE mode\\n\");\n@@ -244,6 +242,7 @@ STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)\n \t\t\tgoto out;\n \n \t\t/* only backplane uses autoc so fall though */\n+\tcase ixgbe_media_type_fiber_qsfp:\n \tcase ixgbe_media_type_fiber:\n \t\treg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n \n@@ -3023,6 +3022,7 @@ void ixgbe_fc_autoneg(struct ixgbe_hw *hw)\n \n \tswitch (hw->phy.media_type) {\n \t/* Autoneg flow control on fiber adapters */\n+\tcase ixgbe_media_type_fiber_qsfp:\n \tcase ixgbe_media_type_fiber:\n \t\tif (speed == IXGBE_LINK_SPEED_1GB_FULL)\n \t\t\tret_val = ixgbe_fc_autoneg_fiber(hw);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\nindex 4351f4f..462e884 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n@@ -46,11 +46,193 @@ STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);\n STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\n STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\n STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);\n-STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);\n+STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);\n STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\t\t  u8 *sff8472_data);\n \n /**\n+ * ixgbe_out_i2c_byte_ack - Send I2C byte with ack\n+ * @hw: pointer to the hardware structure\n+ * @byte: byte to send\n+ *\n+ * Returns an error code on error.\n+ */\n+STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)\n+{\n+\ts32 status;\n+\n+\tstatus = ixgbe_clock_out_i2c_byte(hw, byte);\n+\tif (status)\n+\t\treturn status;\n+\treturn ixgbe_get_i2c_ack(hw);\n+}\n+\n+/**\n+ * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack\n+ * @hw: pointer to the hardware structure\n+ * @byte: pointer to a u8 to receive the byte\n+ *\n+ * Returns an error code on error.\n+ */\n+STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)\n+{\n+\ts32 status;\n+\n+\tstatus = ixgbe_clock_in_i2c_byte(hw, byte);\n+\tif (status)\n+\t\treturn status;\n+\t/* ACK */\n+\treturn ixgbe_clock_out_i2c_bit(hw, false);\n+}\n+\n+/**\n+ * ixgbe_ones_comp_byte_add - Perform one's complement addition\n+ * @add1 - addend 1\n+ * @add2 - addend 2\n+ *\n+ * Returns one's complement 8-bit sum.\n+ */\n+STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)\n+{\n+\tu16 sum = add1 + add2;\n+\n+\tsum = (sum & 0xFF) + (sum >> 8);\n+\treturn sum & 0xFF;\n+}\n+\n+/**\n+ * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to read from\n+ * @reg: I2C device register to read from\n+ * @val: pointer to location to receive read value\n+ *\n+ * Returns an error code on error.\n+ */\n+STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n+\t\t\t\t\t   u16 reg, u16 *val)\n+{\n+\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n+\tint max_retry = 10;\n+\tint retry = 0;\n+\tu8 csum_byte;\n+\tu8 high_bits;\n+\tu8 low_bits;\n+\tu8 reg_high;\n+\tu8 csum;\n+\n+\treg_high = ((reg >> 7) & 0xFE) | 1;\t/* Indicate read combined */\n+\tcsum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);\n+\tcsum = ~csum;\n+\tdo {\n+\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))\n+\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n+\t\tixgbe_i2c_start(hw);\n+\t\t/* Device Address and write indication */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, addr))\n+\t\t\tgoto fail;\n+\t\t/* Write bits 14:8 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, reg_high))\n+\t\t\tgoto fail;\n+\t\t/* Write bits 7:0 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))\n+\t\t\tgoto fail;\n+\t\t/* Write csum */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, csum))\n+\t\t\tgoto fail;\n+\t\t/* Re-start condition */\n+\t\tixgbe_i2c_start(hw);\n+\t\t/* Device Address and read indication */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, addr | 1))\n+\t\t\tgoto fail;\n+\t\t/* Get upper bits */\n+\t\tif (ixgbe_in_i2c_byte_ack(hw, &high_bits))\n+\t\t\tgoto fail;\n+\t\t/* Get low bits */\n+\t\tif (ixgbe_in_i2c_byte_ack(hw, &low_bits))\n+\t\t\tgoto fail;\n+\t\t/* Get csum */\n+\t\tif (ixgbe_clock_in_i2c_byte(hw, &csum_byte))\n+\t\t\tgoto fail;\n+\t\t/* NACK */\n+\t\tif (ixgbe_clock_out_i2c_bit(hw, false))\n+\t\t\tgoto fail;\n+\t\tixgbe_i2c_stop(hw);\n+\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\t\t*val = (high_bits << 8) | low_bits;\n+\t\treturn 0;\n+\n+fail:\n+\t\tixgbe_i2c_bus_clear(hw);\n+\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\t\tretry++;\n+\t\tif (retry < max_retry)\n+\t\t\tDEBUGOUT(\"I2C byte read combined error - Retrying.\\n\");\n+\t\telse\n+\t\t\tDEBUGOUT(\"I2C byte read combined error.\\n\");\n+\t} while (retry < max_retry);\n+\n+\treturn IXGBE_ERR_I2C;\n+}\n+\n+/**\n+ * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation\n+ * @hw: pointer to the hardware structure\n+ * @addr: I2C bus address to write to\n+ * @reg: I2C device register to write to\n+ * @val: value to write\n+ *\n+ * Returns an error code on error.\n+ */\n+STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,\n+\t\t\t\t\t    u8 addr, u16 reg, u16 val)\n+{\n+\tint max_retry = 1;\n+\tint retry = 0;\n+\tu8 reg_high;\n+\tu8 csum;\n+\n+\treg_high = (reg >> 7) & 0xFE;\t/* Indicate write combined */\n+\tcsum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);\n+\tcsum = ixgbe_ones_comp_byte_add(csum, val >> 8);\n+\tcsum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);\n+\tcsum = ~csum;\n+\tdo {\n+\t\tixgbe_i2c_start(hw);\n+\t\t/* Device Address and write indication */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, addr))\n+\t\t\tgoto fail;\n+\t\t/* Write bits 14:8 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, reg_high))\n+\t\t\tgoto fail;\n+\t\t/* Write bits 7:0 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))\n+\t\t\tgoto fail;\n+\t\t/* Write data 15:8 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, val >> 8))\n+\t\t\tgoto fail;\n+\t\t/* Write data 7:0 */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))\n+\t\t\tgoto fail;\n+\t\t/* Write csum */\n+\t\tif (ixgbe_out_i2c_byte_ack(hw, csum))\n+\t\t\tgoto fail;\n+\t\tixgbe_i2c_stop(hw);\n+\t\treturn 0;\n+\n+fail:\n+\t\tixgbe_i2c_bus_clear(hw);\n+\t\tretry++;\n+\t\tif (retry < max_retry)\n+\t\t\tDEBUGOUT(\"I2C byte write combined error - Retrying.\\n\");\n+\t\telse\n+\t\t\tDEBUGOUT(\"I2C byte write combined error.\\n\");\n+\t} while (retry < max_retry);\n+\n+\treturn IXGBE_ERR_I2C;\n+}\n+\n+/**\n  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs\n  *  @hw: pointer to the hardware structure\n  *\n@@ -81,6 +263,8 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)\n \tphy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;\n \tphy->ops.identify_sfp = &ixgbe_identify_module_generic;\n \tphy->sfp_type = ixgbe_sfp_type_unknown;\n+\tphy->ops.read_i2c_combined = &ixgbe_read_i2c_combined_generic;\n+\tphy->ops.write_i2c_combined = &ixgbe_write_i2c_combined_generic;\n \tphy->ops.check_overtemp = &ixgbe_tn_check_overtemp;\n \treturn IXGBE_SUCCESS;\n }\n@@ -1019,6 +1203,9 @@ s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)\n \t\tstatus = ixgbe_identify_sfp_module_generic(hw);\n \t\tbreak;\n \n+\tcase ixgbe_media_type_fiber_qsfp:\n+\t\tstatus = ixgbe_identify_qsfp_module_generic(hw);\n+\t\tbreak;\n \n \tdefault:\n \t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n@@ -1115,7 +1302,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_lr;\n \t\t\telse\n \t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n-\t\t} else if (hw->mac.type == ixgbe_mac_82599EB) {\n+\t\t} else {\n \t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {\n \t\t\t\tif (hw->bus.lan_id == 0)\n \t\t\t\t\thw->phy.sfp_type =\n@@ -1148,16 +1335,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\t\t\telse\n \t\t\t\t\thw->phy.sfp_type =\n \t\t\t\t\t\t      ixgbe_sfp_type_srlr_core1;\n-#ifdef SUPPORT_10GBASE_ER\n-\t\t\t} else if (comp_codes_10g &\n-\t\t\t\t   IXGBE_SFF_10GBASEER_CAPABLE) {\n-\t\t\t\tif (hw->bus.lan_id == 0)\n-\t\t\t\t\thw->phy.sfp_type =\n-\t\t\t\t\t\t\tixgbe_sfp_type_er_core0;\n-\t\t\t\telse\n-\t\t\t\t\thw->phy.sfp_type =\n-\t\t\t\t\t\t\tixgbe_sfp_type_er_core1;\n-#endif /* SUPPORT_10GBASE_ER */\n \t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {\n \t\t\t\tif (hw->bus.lan_id == 0)\n \t\t\t\t\thw->phy.sfp_type =\n@@ -1172,7 +1349,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\t\t\telse\n \t\t\t\t\thw->phy.sfp_type =\n \t\t\t\t\t\tixgbe_sfp_type_1g_sx_core1;\n-#ifdef SUPPORT_1000BASE_LX\n \t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {\n \t\t\t\tif (hw->bus.lan_id == 0)\n \t\t\t\t\thw->phy.sfp_type =\n@@ -1180,7 +1356,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\t\t\telse\n \t\t\t\t\thw->phy.sfp_type =\n \t\t\t\t\t\tixgbe_sfp_type_1g_lx_core1;\n-#endif /* SUPPORT_1000BASE_LX */\n \t\t\t} else {\n \t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n \t\t\t}\n@@ -1268,10 +1443,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\tif (comp_codes_10g == 0 &&\n \t\t    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n-#ifdef SUPPORT_1000BASE_LX\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n-#endif\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {\n \t\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n@@ -1289,14 +1462,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n \t\tif (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&\n \t\t    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n-#ifdef SUPPORT_1000BASE_LX\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n-#endif\n-#ifdef SUPPORT_10GBASE_ER\n-\t\t      hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||\n-\t\t      hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||\n-#endif\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n \t\t      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {\n \t\t\t/* Make sure we're a supported PHY type */\n@@ -1339,6 +1506,266 @@ err_read_i2c_eeprom:\n \treturn IXGBE_ERR_SFP_NOT_PRESENT;\n }\n \n+/**\n+ *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Determines physical layer capabilities of the current SFP.\n+ */\n+s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)\n+{\n+\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\tu8 comp_codes_10g = 0;\n+\tu8 comp_codes_1g = 0;\n+\n+\tDEBUGFUNC(\"ixgbe_get_supported_phy_sfp_layer_generic\");\n+\n+\thw->phy.ops.identify_sfp(hw);\n+\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n+\t\treturn physical_layer;\n+\n+\tswitch (hw->phy.type) {\n+\tcase ixgbe_phy_sfp_passive_tyco:\n+\tcase ixgbe_phy_sfp_passive_unknown:\n+\tcase ixgbe_phy_qsfp_passive_unknown:\n+\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n+\t\tbreak;\n+\tcase ixgbe_phy_sfp_ftl_active:\n+\tcase ixgbe_phy_sfp_active_unknown:\n+\tcase ixgbe_phy_qsfp_active_unknown:\n+\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;\n+\t\tbreak;\n+\tcase ixgbe_phy_sfp_avago:\n+\tcase ixgbe_phy_sfp_ftl:\n+\tcase ixgbe_phy_sfp_intel:\n+\tcase ixgbe_phy_sfp_unknown:\n+\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);\n+\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);\n+\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n+\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n+\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;\n+\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n+\t\tbreak;\n+\tcase ixgbe_phy_qsfp_intel:\n+\tcase ixgbe_phy_qsfp_unknown:\n+\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t      IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);\n+\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n+\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n+\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn physical_layer;\n+}\n+\n+/**\n+ *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Searches for and identifies the QSFP module and assigns appropriate PHY type\n+ **/\n+s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)\n+{\n+\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n+\tu32 vendor_oui = 0;\n+\tenum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;\n+\tu8 identifier = 0;\n+\tu8 comp_codes_1g = 0;\n+\tu8 comp_codes_10g = 0;\n+\tu8 oui_bytes[3] = {0, 0, 0};\n+\tu16 enforce_sfp = 0;\n+\tu8 connector = 0;\n+\tu8 cable_length = 0;\n+\tu8 device_tech = 0;\n+\tbool active_cable = false;\n+\n+\tDEBUGFUNC(\"ixgbe_identify_qsfp_module_generic\");\n+\n+\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {\n+\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n+\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n+\t\tgoto out;\n+\t}\n+\n+\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,\n+\t\t\t\t\t     &identifier);\n+\n+\tif (status != IXGBE_SUCCESS)\n+\t\tgoto err_read_i2c_eeprom;\n+\n+\tif (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {\n+\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n+\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n+\t\tgoto out;\n+\t}\n+\n+\thw->phy.id = identifier;\n+\n+\t/* LAN ID is needed for sfp_type determination */\n+\thw->mac.ops.set_lan_id(hw);\n+\n+\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,\n+\t\t\t\t\t     &comp_codes_10g);\n+\n+\tif (status != IXGBE_SUCCESS)\n+\t\tgoto err_read_i2c_eeprom;\n+\n+\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,\n+\t\t\t\t\t     &comp_codes_1g);\n+\n+\tif (status != IXGBE_SUCCESS)\n+\t\tgoto err_read_i2c_eeprom;\n+\n+\tif (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {\n+\t\thw->phy.type = ixgbe_phy_qsfp_passive_unknown;\n+\t\tif (hw->bus.lan_id == 0)\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;\n+\t\telse\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;\n+\t} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |\n+\t\t\t\t     IXGBE_SFF_10GBASELR_CAPABLE)) {\n+\t\tif (hw->bus.lan_id == 0)\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;\n+\t\telse\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;\n+\t} else {\n+\t\tif (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)\n+\t\t\tactive_cable = true;\n+\n+\t\tif (!active_cable) {\n+\t\t\t/* check for active DA cables that pre-date\n+\t\t\t * SFF-8436 v3.6 */\n+\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\tIXGBE_SFF_QSFP_CONNECTOR,\n+\t\t\t\t\t&connector);\n+\n+\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\tIXGBE_SFF_QSFP_CABLE_LENGTH,\n+\t\t\t\t\t&cable_length);\n+\n+\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\tIXGBE_SFF_QSFP_DEVICE_TECH,\n+\t\t\t\t\t&device_tech);\n+\n+\t\t\tif ((connector ==\n+\t\t\t\t     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&\n+\t\t\t    (cable_length > 0) &&\n+\t\t\t    ((device_tech >> 4) ==\n+\t\t\t\t     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))\n+\t\t\t\tactive_cable = true;\n+\t\t}\n+\n+\t\tif (active_cable) {\n+\t\t\thw->phy.type = ixgbe_phy_qsfp_active_unknown;\n+\t\t\tif (hw->bus.lan_id == 0)\n+\t\t\t\thw->phy.sfp_type =\n+\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core0;\n+\t\t\telse\n+\t\t\t\thw->phy.sfp_type =\n+\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core1;\n+\t\t} else {\n+\t\t\t/* unsupported module type */\n+\t\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n+\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\tif (hw->phy.sfp_type != stored_sfp_type)\n+\t\thw->phy.sfp_setup_needed = true;\n+\n+\t/* Determine if the QSFP+ PHY is dual speed or not. */\n+\thw->phy.multispeed_fiber = false;\n+\tif (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&\n+\t   (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||\n+\t   ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&\n+\t   (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))\n+\t\thw->phy.multispeed_fiber = true;\n+\n+\t/* Determine PHY vendor for optical modules */\n+\tif (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |\n+\t\t\t      IXGBE_SFF_10GBASELR_CAPABLE))  {\n+\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\t    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,\n+\t\t\t\t\t    &oui_bytes[0]);\n+\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\tgoto err_read_i2c_eeprom;\n+\n+\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\t    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,\n+\t\t\t\t\t    &oui_bytes[1]);\n+\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\tgoto err_read_i2c_eeprom;\n+\n+\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n+\t\t\t\t\t    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,\n+\t\t\t\t\t    &oui_bytes[2]);\n+\n+\t\tif (status != IXGBE_SUCCESS)\n+\t\t\tgoto err_read_i2c_eeprom;\n+\n+\t\tvendor_oui =\n+\t\t  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |\n+\t\t   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |\n+\t\t   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));\n+\n+\t\tif (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)\n+\t\t\thw->phy.type = ixgbe_phy_qsfp_intel;\n+\t\telse\n+\t\t\thw->phy.type = ixgbe_phy_qsfp_unknown;\n+\n+\t\tixgbe_get_device_caps(hw, &enforce_sfp);\n+\t\tif (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {\n+\t\t\t/* Make sure we're a supported PHY type */\n+\t\t\tif (hw->phy.type == ixgbe_phy_qsfp_intel) {\n+\t\t\t\tstatus = IXGBE_SUCCESS;\n+\t\t\t} else {\n+\t\t\t\tif (hw->allow_unsupported_sfp == true) {\n+\t\t\t\t\tEWARN(hw, \"WARNING: Intel (R) Network \"\n+\t\t\t\t\t      \"Connections are quality tested \"\n+\t\t\t\t\t      \"using Intel (R) Ethernet Optics.\"\n+\t\t\t\t\t      \" Using untested modules is not \"\n+\t\t\t\t\t      \"supported and may cause unstable\"\n+\t\t\t\t\t      \" operation or damage to the \"\n+\t\t\t\t\t      \"module or the adapter. Intel \"\n+\t\t\t\t\t      \"Corporation is not responsible \"\n+\t\t\t\t\t      \"for any harm caused by using \"\n+\t\t\t\t\t      \"untested modules.\\n\", status);\n+\t\t\t\t\tstatus = IXGBE_SUCCESS;\n+\t\t\t\t} else {\n+\t\t\t\t\tDEBUGOUT(\"QSFP module not supported\\n\");\n+\t\t\t\t\thw->phy.type =\n+\t\t\t\t\t\tixgbe_phy_sfp_unsupported;\n+\t\t\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\tstatus = IXGBE_SUCCESS;\n+\t\t}\n+\t}\n+\n+out:\n+\treturn status;\n+\n+err_read_i2c_eeprom:\n+\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n+\thw->phy.id = 0;\n+\thw->phy.type = ixgbe_phy_unknown;\n+\n+\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n+}\n \n \n /**\n@@ -1374,22 +1801,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n \t * SR modules\n \t */\n \tif (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||\n-#ifdef SUPPORT_10GBASE_ER\n-\t    sfp_type == ixgbe_sfp_type_er_core0 ||\n-#endif /* SUPPORT_10GBASE_ER */\n-#ifdef SUPPORT_1000BASE_LX\n \t    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n-#endif /* SUPPORT_1000BASE_LX */\n \t    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n \t    sfp_type == ixgbe_sfp_type_1g_sx_core0)\n \t\tsfp_type = ixgbe_sfp_type_srlr_core0;\n \telse if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||\n-#ifdef SUPPORT_10GBASE_ER\n-\t\t sfp_type == ixgbe_sfp_type_er_core1 ||\n-#endif /* SUPPORT_10GBASE_ER */\n-#ifdef SUPPORT_1000BASE_LX\n \t\t sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n-#endif /* SUPPORT_1000BASE_LX */\n \t\t sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n \t\t sfp_type == ixgbe_sfp_type_1g_sx_core1)\n \t\tsfp_type = ixgbe_sfp_type_srlr_core1;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\nindex 696a0d5..c47812b 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h\n@@ -51,6 +51,15 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_SFF_CABLE_SPEC_COMP\t0x3C\n #define IXGBE_SFF_SFF_8472_SWAP\t\t0x5C\n #define IXGBE_SFF_SFF_8472_COMP\t\t0x5E\n+#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS\t0xD\n+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0\t0xA5\n+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1\t0xA6\n+#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2\t0xA7\n+#define IXGBE_SFF_QSFP_CONNECTOR\t0x82\n+#define IXGBE_SFF_QSFP_10GBE_COMP\t0x83\n+#define IXGBE_SFF_QSFP_1GBE_COMP\t0x86\n+#define IXGBE_SFF_QSFP_CABLE_LENGTH\t0x92\n+#define IXGBE_SFF_QSFP_DEVICE_TECH\t0x93\n \n /* Bitmasks */\n #define IXGBE_SFF_DA_PASSIVE_CABLE\t0x4\n@@ -61,10 +70,11 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_SFF_1GBASET_CAPABLE\t0x8\n #define IXGBE_SFF_10GBASESR_CAPABLE\t0x10\n #define IXGBE_SFF_10GBASELR_CAPABLE\t0x20\n-#ifdef SUPPORT_10GBASE_ER\n-#define IXGBE_SFF_10GBASEER_CAPABLE    0x80\n-#endif /* SUPPORT_10GBASE_ER */\n #define IXGBE_SFF_ADDRESSING_MODE\t0x4\n+#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE\t0x1\n+#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE\t0x8\n+#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE\t0x23\n+#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL\t0x0\n #define IXGBE_I2C_EEPROM_READ_MASK\t0x100\n #define IXGBE_I2C_EEPROM_STATUS_MASK\t0x3\n #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION\t0x0\n@@ -143,6 +153,8 @@ s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);\n s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);\n s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);\n+s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);\n+s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);\n s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n \t\t\t\t\tu16 *list_offset,\n \t\t\t\t\tu16 *data_offset);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex 89543c0..bfe1235 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -114,12 +114,14 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_DEV_ID_82599_SFP_EM\t\t0x1507\n #define IXGBE_DEV_ID_82599_SFP_SF2\t\t0x154D\n #define IXGBE_DEV_ID_82599_SFP_SF_QP\t\t0x154A\n+#define IXGBE_DEV_ID_82599_QSFP_SF_QP\t\t0x1558\n #define IXGBE_DEV_ID_82599EN_SFP\t\t0x1557\n #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1\t0x0001\n #define IXGBE_DEV_ID_82599_XAUI_LOM\t\t0x10FC\n #define IXGBE_DEV_ID_82599_T3_LOM\t\t0x151C\n #define IXGBE_DEV_ID_82599_VF\t\t\t0x10ED\n #define IXGBE_DEV_ID_82599_VF_HV\t\t0x152E\n+#define IXGBE_DEV_ID_82599_LS\t\t\t0x154F\n #define IXGBE_DEV_ID_X540T\t\t\t0x1528\n #define IXGBE_DEV_ID_X540_VF\t\t\t0x1515\n #define IXGBE_DEV_ID_X540_VF_HV\t\t\t0x1530\n@@ -131,7 +133,10 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_CTRL_EXT\t\t0x00018\n #define IXGBE_ESDP\t\t0x00020\n #define IXGBE_EODSDP\t\t0x00028\n-#define IXGBE_I2CCTL\t\t0x00028\n+#define IXGBE_I2CCTL_82599\t0x00028\n+#define IXGBE_I2CCTL_X550\t0x15F5C\n+#define IXGBE_I2CCTL_BY_MAC(_hw) ((((_hw)->mac.type >= ixgbe_mac_X550) ? \\\n+\t\t\t\t IXGBE_I2CCTL_X550 : IXGBE_I2CCTL_82599))\n #define IXGBE_PHY_GPIO\t\t0x00028\n #define IXGBE_MAC_GPIO\t\t0x00030\n #define IXGBE_PHYINT_STATUS0\t0x00100\n@@ -2844,6 +2849,10 @@ enum ixgbe_phy_type {\n \tixgbe_phy_sfp_ftl_active,\n \tixgbe_phy_sfp_unknown,\n \tixgbe_phy_sfp_intel,\n+\tixgbe_phy_qsfp_passive_unknown,\n+\tixgbe_phy_qsfp_active_unknown,\n+\tixgbe_phy_qsfp_intel,\n+\tixgbe_phy_qsfp_unknown,\n \tixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/\n \tixgbe_phy_generic\n };\n@@ -2875,14 +2884,8 @@ enum ixgbe_sfp_type {\n \tixgbe_sfp_type_1g_cu_core1 = 10,\n \tixgbe_sfp_type_1g_sx_core0 = 11,\n \tixgbe_sfp_type_1g_sx_core1 = 12,\n-#ifdef SUPPORT_1000BASE_LX\n \tixgbe_sfp_type_1g_lx_core0 = 13,\n \tixgbe_sfp_type_1g_lx_core1 = 14,\n-#endif /* SUPPORT_1000BASE_LX */\n-#ifdef SUPPORT_10GBASE_ER\n-\tixgbe_sfp_type_er_core0 = 15,\n-\tixgbe_sfp_type_er_core1 = 16,\n-#endif /* SUPPORT_10GBASE_ER */\n \tixgbe_sfp_type_not_present = 0xFFFE,\n \tixgbe_sfp_type_unknown = 0xFFFF\n };\n@@ -2890,6 +2893,8 @@ enum ixgbe_sfp_type {\n enum ixgbe_media_type {\n \tixgbe_media_type_unknown = 0,\n \tixgbe_media_type_fiber,\n+\tixgbe_media_type_fiber_qsfp,\n+\tixgbe_media_type_fiber_lco,\n \tixgbe_media_type_copper,\n \tixgbe_media_type_backplane,\n \tixgbe_media_type_cx4,\n@@ -3181,6 +3186,8 @@ struct ixgbe_phy_operations {\n \ts32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);\n \ts32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);\n \tvoid (*i2c_bus_clear)(struct ixgbe_hw *);\n+\ts32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);\n+\ts32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);\n \ts32 (*check_overtemp)(struct ixgbe_hw *);\n };\n \n@@ -3235,12 +3242,15 @@ struct ixgbe_phy_info {\n \tbool sfp_setup_needed;\n \tu32 revision;\n \tenum ixgbe_media_type media_type;\n+\tu32 phy_semaphore_mask;\n+\tu8 lan_id;\n \tbool reset_disable;\n \tixgbe_autoneg_advertised autoneg_advertised;\n \tenum ixgbe_smart_speed smart_speed;\n \tbool smart_speed_active;\n \tbool multispeed_fiber;\n \tbool reset_if_overtemp;\n+\tbool qsfp_shared_i2c_bus;\n };\n \n #include \"ixgbe_mbx.h\"\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c\nindex af0e0fd..a2d6e61 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c\n@@ -515,6 +515,21 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \tif (!(links_reg & IXGBE_LINKS_UP))\n \t\tgoto out;\n \n+\t/* for SFP+ modules and DA cables on 82599 it can take up to 500usecs\n+\t * before the link status is correct\n+\t */\n+\tif (mac->type == ixgbe_mac_82599_vf) {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < 5; i++) {\n+\t\t\tusec_delay(100);\n+\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);\n+\n+\t\t\tif (!(links_reg & IXGBE_LINKS_UP))\n+\t\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n \tswitch (links_reg & IXGBE_LINKS_SPEED_82599) {\n \tcase IXGBE_LINKS_SPEED_10G_82599:\n \t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "09/18"
    ]
}