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GET /api/patches/628/?format=api
{ "id": 628, "url": "http://patches.dpdk.org/api/patches/628/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1411974986-28137-9-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411974986-28137-9-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-9-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-29T07:16:16", "name": "[dpdk-dev,v2,08/18] ixgbe: New function to read and write I2C bytes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "eb006cd5fbd5a9ebf9908ab34a1a6757b36ceffa", "submitter": { "id": 31, "url": "http://patches.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1411974986-28137-9-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/628/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/628/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id BD4787E58;\n\tMon, 29 Sep 2014 09:10:41 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 5949F7E49\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:38 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga103.fm.intel.com with ESMTP; 29 Sep 2014 00:07:46 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 29 Sep 2014 00:17:06 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8T7H4k1013691;\n\tMon, 29 Sep 2014 15:17:04 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7H2Yj028390; Mon, 29 Sep 2014 15:17:04 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7H2wX028386; \n\tMon, 29 Sep 2014 15:17:02 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"598147212\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 29 Sep 2014 15:16:16 +0800", "Message-Id": "<1411974986-28137-9-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 08/18] ixgbe: New function to read and write\n\tI2C bytes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch implement functions to do I2C byte read and write in\nIXGBE base code; it also relocates function of ixgbe_mng_enabled.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 136 +++++++++++++++++++++++++-----\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c | 27 ++++++\n 2 files changed, 144 insertions(+), 19 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex adf0e52..277cc25 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -53,25 +53,10 @@ STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n \t\t\t\t u16 offset, u16 *data);\n STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n \t\t\t\t\t u16 words, u16 *data);\n-\n-bool ixgbe_mng_enabled(struct ixgbe_hw *hw)\n-{\n-\tu32 fwsm, manc, factps;\n-\n-\tfwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);\n-\tif ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)\n-\t\treturn false;\n-\n-\tmanc = IXGBE_READ_REG(hw, IXGBE_MANC);\n-\tif (!(manc & IXGBE_MANC_RCV_TCO_EN))\n-\t\treturn false;\n-\n-\tfactps = IXGBE_READ_REG(hw, IXGBE_FACTPS);\n-\tif (factps & IXGBE_FACTPS_MNGCG)\n-\t\treturn false;\n-\n-\treturn true;\n-}\n+STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\t\tu8 dev_addr, u8 *data);\n+STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\t\tu8 dev_addr, u8 data);\n \n void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)\n {\n@@ -2583,4 +2568,117 @@ reset_pipeline_out:\n }\n \n \n+/**\n+ * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to read\n+ * @data: value read\n+ *\n+ * Performs byte read operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n+ **/\n+STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 dev_addr, u8 *data)\n+{\n+\tu32 esdp;\n+\ts32 status;\n+\ts32 timeout = 200;\n+\n+\tDEBUGFUNC(\"ixgbe_read_i2c_byte_82599\");\n+\n+\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n+\t\t/* Acquire I2C bus ownership. */\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tesdp |= IXGBE_ESDP_SDP0;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t\tIXGBE_WRITE_FLUSH(hw);\n+\n+\t\twhile (timeout) {\n+\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n+\t\t\t\tbreak;\n+\n+\t\t\tmsec_delay(5);\n+\t\t\ttimeout--;\n+\t\t}\n+\n+\t\tif (!timeout) {\n+\t\t\tDEBUGOUT(\"Driver can't access resource,\"\n+\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n+\t\t\tstatus = IXGBE_ERR_I2C;\n+\t\t\tgoto release_i2c_access;\n+\t\t}\n+\t}\n+\n+\tstatus = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n+\n+release_i2c_access:\n+\n+\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n+\t\t/* Release I2C bus ownership. */\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tesdp &= ~IXGBE_ESDP_SDP0;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t\tIXGBE_WRITE_FLUSH(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset to write\n+ * @data: value to write\n+ *\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface at\n+ * a specified device address.\n+ **/\n+STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\t u8 dev_addr, u8 data)\n+{\n+\tu32 esdp;\n+\ts32 status;\n+\ts32 timeout = 200;\n+\n+\tDEBUGFUNC(\"ixgbe_write_i2c_byte_82599\");\n+\n+\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n+\t\t/* Acquire I2C bus ownership. */\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tesdp |= IXGBE_ESDP_SDP0;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t\tIXGBE_WRITE_FLUSH(hw);\n+\n+\t\twhile (timeout) {\n+\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n+\t\t\t\tbreak;\n+\n+\t\t\tmsec_delay(5);\n+\t\t\ttimeout--;\n+\t\t}\n+\n+\t\tif (!timeout) {\n+\t\t\tDEBUGOUT(\"Driver can't access resource,\"\n+\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n+\t\t\tstatus = IXGBE_ERR_I2C;\n+\t\t\tgoto release_i2c_access;\n+\t\t}\n+\t}\n+\n+\tstatus = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n+\n+release_i2c_access:\n+\n+\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n+\t\t/* Release I2C bus ownership. */\n+\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\t\tesdp &= ~IXGBE_ESDP_SDP0;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\t\tIXGBE_WRITE_FLUSH(hw);\n+\t}\n+\n+\treturn status;\n+}\n \ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex 749188d..850c12d 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -4663,3 +4663,30 @@ void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)\n \t\t}\n \t}\n }\n+\n+/**\n+ * ixgbe_mng_enabled - Is the manageability engine enabled?\n+ * @hw: pointer to hardware structure\n+ *\n+ * Returns true if the manageability engine is enabled.\n+ **/\n+bool ixgbe_mng_enabled(struct ixgbe_hw *hw)\n+{\n+\tu32 fwsm, manc, factps;\n+\n+\tfwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);\n+\tif ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)\n+\t\treturn false;\n+\n+\tmanc = IXGBE_READ_REG(hw, IXGBE_MANC);\n+\tif (!(manc & IXGBE_MANC_RCV_TCO_EN))\n+\t\treturn false;\n+\n+\tif (hw->mac.type <= ixgbe_mac_X540) {\n+\t\tfactps = IXGBE_READ_REG(hw, IXGBE_FACTPS);\n+\t\tif (factps & IXGBE_FACTPS_MNGCG)\n+\t\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n", "prefixes": [ "dpdk-dev", "v2", "08/18" ] }