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GET /api/patches/62687/?format=api
{ "id": 62687, "url": "http://patches.dpdk.org/api/patches/62687/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1573146604-17803-10-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1573146604-17803-10-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1573146604-17803-10-git-send-email-viacheslavo@mellanox.com", "date": "2019-11-07T17:09:54", "name": "[v3,09/19] net/mlx5: add devarg for extensive metadata support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "497559c70fd2bab5b76d531a398a163553b6176f", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1573146604-17803-10-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 7336, "url": "http://patches.dpdk.org/api/series/7336/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7336", "date": "2019-11-07T17:09:46", "name": "net/mlx5: implement extensive metadata feature", "version": 3, "mbox": "http://patches.dpdk.org/series/7336/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/62687/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/62687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D7AB6A034E;\n\tThu, 7 Nov 2019 18:11:44 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 562661BFE8;\n\tThu, 7 Nov 2019 18:10:36 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 2DF7B1BFAE\n for <dev@dpdk.org>; Thu, 7 Nov 2019 18:10:28 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 7 Nov 2019 19:10:22 +0200", "from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx\n [10.210.16.104])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id xA7HAMev023032;\n Thu, 7 Nov 2019 19:10:22 +0200", "from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id xA7HAMOV017955;\n Thu, 7 Nov 2019 17:10:22 GMT", "(from viacheslavo@localhost)\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id xA7HAMZg017954;\n Thu, 7 Nov 2019 17:10:22 GMT" ], "X-Authentication-Warning": "pegasus11.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net,\n orika@mellanox.com, Yongseok Koh <yskoh@mellanox.com>", "Date": "Thu, 7 Nov 2019 17:09:54 +0000", "Message-Id": "<1573146604-17803-10-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1573146604-17803-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1572940915-29416-1-git-send-email-viacheslavo@mellanox.com>\n <1573146604-17803-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v3 09/19] net/mlx5: add devarg for extensive\n\tmetadata support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The PMD parameter dv_xmeta_en is added to control extensive\nmetadata support. A nonzero value enables extensive flow\nmetadata support if device is capable and driver supports it.\nThis can enable extensive support of MARK and META item of\nrte_flow. The newly introduced SET_TAG and SET_META actions\ndo not depend on dv_xmeta_en parameter, because there is\nno compatibility issue for new entities. The dv_xmeta_en is\ndisabled by default.\n\nThere are some possible configurations, depending on parameter\nvalue:\n\n- 0, this is default value, defines the legacy mode, the MARK\n and META related actions and items operate only within NIC Tx\n and NIC Rx steering domains, no MARK and META information\n crosses the domain boundaries. The MARK item is 24 bits wide,\n the META item is 32 bits wide.\n\n- 1, this engages extensive metadata mode, the MARK and META\n related actions and items operate within all supported steering\n domains, including FDB, MARK and META information may cross\n the domain boundaries. The ``MARK`` item is 24 bits wide, the\n META item width depends on kernel and firmware configurations\n and might be 0, 16 or 32 bits. Within NIC Tx domain META data\n width is 32 bits for compatibility, the actual width of data\n transferred to the FDB domain depends on kernel configuration\n and may be vary. The actual supported width can be retrieved\n in runtime by series of rte_flow_validate() trials.\n\n- 2, this engages extensive metadata mode, the MARK and META\n related actions and items operate within all supported steering\n domains, including FDB, MARK and META information may cross\n the domain boundaries. The META item is 32 bits wide, the MARK\n item width depends on kernel and firmware configurations and\n might be 0, 16 or 24 bits. The actual supported width can be\n retrieved in runtime by series of rte_flow_validate() trials.\n\nIf there is no E-Switch configuration the ``dv_xmeta_en`` parameter is\nignored and the device is configured to operate in legacy mode (0).\n\nSigned-off-by: Yongseok Koh <yskoh@mellanox.com>\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n doc/guides/nics/mlx5.rst | 49 ++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.c | 33 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_defs.h | 4 ++++\n drivers/net/mlx5/mlx5_prm.h | 3 +++\n 5 files changed, 90 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 4f1093f..0ccc1c8 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -578,6 +578,55 @@ Run-time configuration\n \n Disabled by default.\n \n+- ``dv_xmeta_en`` parameter [int]\n+\n+ A nonzero value enables extensive flow metadata support if device is\n+ capable and driver supports it. This can enable extensive support of\n+ ``MARK`` and ``META`` item of ``rte_flow``. The newly introduced\n+ ``SET_TAG`` and ``SET_META`` actions do not depend on ``dv_xmeta_en``.\n+\n+ There are some possible configurations, depending on parameter value:\n+\n+ - 0, this is default value, defines the legacy mode, the ``MARK`` and\n+ ``META`` related actions and items operate only within NIC Tx and\n+ NIC Rx steering domains, no ``MARK`` and ``META`` information crosses\n+ the domain boundaries. The ``MARK`` item is 24 bits wide, the ``META``\n+ item is 32 bits wide and match supported on egress only.\n+\n+ - 1, this engages extensive metadata mode, the ``MARK`` and ``META``\n+ related actions and items operate within all supported steering domains,\n+ including FDB, ``MARK`` and ``META`` information may cross the domain\n+ boundaries. The ``MARK`` item is 24 bits wide, the ``META`` item width\n+ depends on kernel and firmware configurations and might be 0, 16 or\n+ 32 bits. Within NIC Tx domain ``META`` data width is 32 bits for\n+ compatibility, the actual width of data transferred to the FDB domain\n+ depends on kernel configuration and may be vary. The actual supported\n+ width can be retrieved in runtime by series of rte_flow_validate()\n+ trials.\n+\n+ - 2, this engages extensive metadata mode, the ``MARK`` and ``META``\n+ related actions and items operate within all supported steering domains,\n+ including FDB, ``MARK`` and ``META`` information may cross the domain\n+ boundaries. The ``META`` item is 32 bits wide, the ``MARK`` item width\n+ depends on kernel and firmware configurations and might be 0, 16 or\n+ 24 bits. The actual supported width can be retrieved in runtime by\n+ series of rte_flow_validate() trials.\n+\n+ +------+-----------+-----------+-------------+-------------+\n+ | Mode | ``MARK`` | ``META`` | ``META`` Tx | FDB/Through |\n+ +======+===========+===========+=============+=============+\n+ | 0 | 24 bits | 32 bits | 32 bits | no |\n+ +------+-----------+-----------+-------------+-------------+\n+ | 1 | 24 bits | vary 0-32 | 32 bits | yes |\n+ +------+-----------+-----------+-------------+-------------+\n+ | 2 | vary 0-32 | 32 bits | 32 bits | yes |\n+ +------+-----------+-----------+-------------+-------------+\n+\n+ If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is\n+ ignored and the device is configured to operate in legacy mode (0).\n+\n+ Disabled by default (set to 0).\n+\n - ``dv_flow_en`` parameter [int]\n \n A nonzero value enables the DV flow steering assuming it is supported\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 1b86b7b..943d0e8 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -125,6 +125,9 @@\n /* Activate DV flow steering. */\n #define MLX5_DV_FLOW_EN \"dv_flow_en\"\n \n+/* Enable extensive flow metadata support. */\n+#define MLX5_DV_XMETA_EN \"dv_xmeta_en\"\n+\n /* Activate Netlink support in VF mode. */\n #define MLX5_VF_NL_EN \"vf_nl_en\"\n \n@@ -1310,6 +1313,16 @@ struct mlx5_flow_id_pool *\n \t\tconfig->dv_esw_en = !!tmp;\n \t} else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {\n \t\tconfig->dv_flow_en = !!tmp;\n+\t} else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {\n+\t\tif (tmp != MLX5_XMETA_MODE_LEGACY &&\n+\t\t tmp != MLX5_XMETA_MODE_META16 &&\n+\t\t tmp != MLX5_XMETA_MODE_META32) {\n+\t\t\tDRV_LOG(WARNING, \"invalid extensive \"\n+\t\t\t\t\t \"metadata parameter\");\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tconfig->dv_xmeta_en = tmp;\n \t} else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {\n \t\tconfig->mr_ext_memseg_en = !!tmp;\n \t} else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {\n@@ -1361,6 +1374,7 @@ struct mlx5_flow_id_pool *\n \t\tMLX5_VF_NL_EN,\n \t\tMLX5_DV_ESW_EN,\n \t\tMLX5_DV_FLOW_EN,\n+\t\tMLX5_DV_XMETA_EN,\n \t\tMLX5_MR_EXT_MEMSEG_EN,\n \t\tMLX5_REPRESENTOR,\n \t\tMLX5_MAX_DUMP_FILES_NUM,\n@@ -1734,6 +1748,12 @@ struct mlx5_flow_id_pool *\n \t\trte_errno = EINVAL;\n \t\treturn rte_errno;\n \t}\n+\tif (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {\n+\t\tDRV_LOG(ERR, \"\\\"dv_xmeta_en\\\" configuration mismatch\"\n+\t\t\t \" for shared %s context\", sh->ibdev_name);\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n \treturn 0;\n }\n /**\n@@ -2347,10 +2367,23 @@ struct mlx5_flow_id_pool *\n \t\terr = -err;\n \t\tgoto error;\n \t}\n+\tif (!priv->config.dv_esw_en &&\n+\t priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {\n+\t\tDRV_LOG(WARNING, \"metadata mode %u is not supported \"\n+\t\t\t\t \"(no E-Switch)\", priv->config.dv_xmeta_en);\n+\t\tpriv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;\n+\t}\n \tif (!mlx5_flow_ext_mreg_supported(eth_dev)) {\n \t\tDRV_LOG(DEBUG,\n \t\t\t\"port %u extensive metadata register is not supported\",\n \t\t\teth_dev->data->port_id);\n+\t\tif (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {\n+\t\t\tDRV_LOG(ERR, \"metadata mode %u is not supported \"\n+\t\t\t\t \"(no metadata registers available)\",\n+\t\t\t\t priv->config.dv_xmeta_en);\n+\t\t\terr = ENOTSUP;\n+\t\t\tgoto error;\n+\t\t}\n \t}\n \treturn eth_dev;\n error:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 6b82c6d..e59f8f6 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -238,6 +238,7 @@ struct mlx5_dev_config {\n \tunsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */\n \tunsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */\n \tunsigned int dv_flow_en:1; /* Enable DV flow. */\n+\tunsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */\n \tunsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */\n \tunsigned int devx:1; /* Whether devx interface is available or not. */\n \tunsigned int dest_tir:1; /* Whether advanced DR API is available. */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex e36ab55..a77c430 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -141,6 +141,10 @@\n /* Cache size of mempool for Multi-Packet RQ. */\n #define MLX5_MPRQ_MP_CACHE_SZ 32U\n \n+#define MLX5_XMETA_MODE_LEGACY 0\n+#define MLX5_XMETA_MODE_META16 1\n+#define MLX5_XMETA_MODE_META32 2\n+\n /* Definition of static_assert found in /usr/include/assert.h */\n #ifndef HAVE_STATIC_ASSERT\n #define static_assert _Static_assert\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex c17ba66..b405cb6 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -226,6 +226,9 @@\n /* Default mark value used when none is provided. */\n #define MLX5_FLOW_MARK_DEFAULT 0xffffff\n \n+/* Default mark mask for metadata legacy mode. */\n+#define MLX5_FLOW_MARK_MASK 0xffffff\n+\n /* Maximum number of DS in WQE. Limited by 6-bit field. */\n #define MLX5_DSEG_MAX 63\n \n", "prefixes": [ "v3", "09/19" ] }