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{
    "id": 62685,
    "url": "http://patches.dpdk.org/api/patches/62685/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1573146604-17803-7-git-send-email-viacheslavo@mellanox.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1573146604-17803-7-git-send-email-viacheslavo@mellanox.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1573146604-17803-7-git-send-email-viacheslavo@mellanox.com",
    "date": "2019-11-07T17:09:51",
    "name": "[v3,06/19] net/mlx5: update meta register matcher set",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d9f53bf9ff9598c050e0887b76dea98d38e97fdd",
    "submitter": {
        "id": 1102,
        "url": "http://patches.dpdk.org/api/people/1102/?format=api",
        "name": "Slava Ovsiienko",
        "email": "viacheslavo@mellanox.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1573146604-17803-7-git-send-email-viacheslavo@mellanox.com/mbox/",
    "series": [
        {
            "id": 7336,
            "url": "http://patches.dpdk.org/api/series/7336/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7336",
            "date": "2019-11-07T17:09:46",
            "name": "net/mlx5: implement extensive metadata feature",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/7336/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/62685/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/62685/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A5C8AA034E;\n\tThu,  7 Nov 2019 18:11:23 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 789F51BFD7;\n\tThu,  7 Nov 2019 18:10:31 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 27D131BFB3\n for <dev@dpdk.org>; Thu,  7 Nov 2019 18:10:23 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 7 Nov 2019 19:10:18 +0200",
            "from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx\n [10.210.16.104])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id xA7HAI98022109;\n Thu, 7 Nov 2019 19:10:18 +0200",
            "from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id xA7HAImC017949;\n Thu, 7 Nov 2019 17:10:18 GMT",
            "(from viacheslavo@localhost)\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id xA7HAI8l017948;\n Thu, 7 Nov 2019 17:10:18 GMT"
        ],
        "X-Authentication-Warning": "pegasus11.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f",
        "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>",
        "To": "dev@dpdk.org",
        "Cc": "matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net,\n orika@mellanox.com, Yongseok Koh <yskoh@mellanox.com>",
        "Date": "Thu,  7 Nov 2019 17:09:51 +0000",
        "Message-Id": "<1573146604-17803-7-git-send-email-viacheslavo@mellanox.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1573146604-17803-1-git-send-email-viacheslavo@mellanox.com>",
        "References": "<1572940915-29416-1-git-send-email-viacheslavo@mellanox.com>\n <1573146604-17803-1-git-send-email-viacheslavo@mellanox.com>",
        "Subject": "[dpdk-dev] [PATCH v3 06/19] net/mlx5: update meta register matcher\n\tset",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Introduce the dedicated matcher register field setup routine.\nUpdate the code to use this unified one.\n\nSigned-off-by: Yongseok Koh <yskoh@mellanox.com>\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 171 +++++++++++++++++++---------------------\n 1 file changed, 82 insertions(+), 89 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex b7e8e0a..170726f 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -4905,6 +4905,78 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n+ * Add metadata register item to matcher\n+ *\n+ * @param[in, out] matcher\n+ *   Flow matcher.\n+ * @param[in, out] key\n+ *   Flow matcher value.\n+ * @param[in] reg_type\n+ *   Type of device metadata register\n+ * @param[in] value\n+ *   Register value\n+ * @param[in] mask\n+ *   Register mask\n+ */\n+static void\n+flow_dv_match_meta_reg(void *matcher, void *key,\n+\t\t       enum modify_reg reg_type,\n+\t\t       uint32_t data, uint32_t mask)\n+{\n+\tvoid *misc2_m =\n+\t\tMLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);\n+\tvoid *misc2_v =\n+\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);\n+\n+\tdata &= mask;\n+\tswitch (reg_type) {\n+\tcase REG_A:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);\n+\t\tbreak;\n+\tcase REG_B:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);\n+\t\tbreak;\n+\tcase REG_C_0:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);\n+\t\tbreak;\n+\tcase REG_C_1:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);\n+\t\tbreak;\n+\tcase REG_C_2:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);\n+\t\tbreak;\n+\tcase REG_C_3:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);\n+\t\tbreak;\n+\tcase REG_C_4:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);\n+\t\tbreak;\n+\tcase REG_C_5:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);\n+\t\tbreak;\n+\tcase REG_C_6:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);\n+\t\tbreak;\n+\tcase REG_C_7:\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);\n+\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);\n+\t\tbreak;\n+\tdefault:\n+\t\tassert(false);\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n  * Add META item to matcher\n  *\n  * @param[in, out] matcher\n@@ -4922,21 +4994,15 @@ struct field_modify_info modify_tcp[] = {\n {\n \tconst struct rte_flow_item_meta *meta_m;\n \tconst struct rte_flow_item_meta *meta_v;\n-\tvoid *misc2_m =\n-\t\tMLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);\n-\tvoid *misc2_v =\n-\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);\n \n \tmeta_m = (const void *)item->mask;\n \tif (!meta_m)\n \t\tmeta_m = &rte_flow_item_meta_mask;\n \tmeta_v = (const void *)item->spec;\n-\tif (meta_v) {\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m,\n-\t\t\t metadata_reg_a, meta_m->data);\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v,\n-\t\t\t metadata_reg_a, meta_v->data & meta_m->data);\n-\t}\n+\tif (meta_v)\n+\t\tflow_dv_match_meta_reg(matcher, key, REG_A,\n+\t\t\t\t       rte_cpu_to_be_32(meta_v->data),\n+\t\t\t\t       rte_cpu_to_be_32(meta_m->data));\n }\n \n /**\n@@ -4953,13 +5019,7 @@ struct field_modify_info modify_tcp[] = {\n flow_dv_translate_item_meta_vport(void *matcher, void *key,\n \t\t\t\t  uint32_t value, uint32_t mask)\n {\n-\tvoid *misc2_m =\n-\t\tMLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);\n-\tvoid *misc2_v =\n-\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);\n-\n-\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);\n-\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);\n+\tflow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);\n }\n \n /**\n@@ -4973,81 +5033,14 @@ struct field_modify_info modify_tcp[] = {\n  *   Flow pattern to translate.\n  */\n static void\n-flow_dv_translate_item_tag(void *matcher, void *key,\n-\t\t\t   const struct rte_flow_item *item)\n+flow_dv_translate_mlx5_item_tag(void *matcher, void *key,\n+\t\t\t\tconst struct rte_flow_item *item)\n {\n-\tvoid *misc2_m =\n-\t\tMLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);\n-\tvoid *misc2_v =\n-\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);\n \tconst struct mlx5_rte_flow_item_tag *tag_v = item->spec;\n \tconst struct mlx5_rte_flow_item_tag *tag_m = item->mask;\n \tenum modify_reg reg = tag_v->id;\n-\trte_be32_t value = tag_v->data;\n-\trte_be32_t mask = tag_m->data;\n \n-\tswitch (reg) {\n-\tcase REG_A:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,\n-\t\t\t\trte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_B:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_0:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_1:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_2:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_3:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_4:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_5:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_6:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\tcase REG_C_7:\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,\n-\t\t\t\t rte_be_to_cpu_32(mask));\n-\t\tMLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,\n-\t\t\t\trte_be_to_cpu_32(value));\n-\t\tbreak;\n-\t}\n+\tflow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);\n }\n \n /**\n@@ -6179,8 +6172,8 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tlast_item = MLX5_FLOW_LAYER_ICMP6;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n-\t\t\tflow_dv_translate_item_tag(match_mask, match_value,\n-\t\t\t\t\t\t   items);\n+\t\t\tflow_dv_translate_mlx5_item_tag(match_mask,\n+\t\t\t\t\t\t\tmatch_value, items);\n \t\t\tlast_item = MLX5_FLOW_ITEM_TAG;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n",
    "prefixes": [
        "v3",
        "06/19"
    ]
}