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GET /api/patches/62427/?format=api
{ "id": 62427, "url": "http://patches.dpdk.org/api/patches/62427/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1572940915-29416-11-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1572940915-29416-11-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1572940915-29416-11-git-send-email-viacheslavo@mellanox.com", "date": "2019-11-05T08:01:45", "name": "[10/20] net/mlx5: adjust shared register according to mask", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a8af1d78a0d375edc74aae5a6ad058a4f006c95c", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1572940915-29416-11-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 7242, "url": "http://patches.dpdk.org/api/series/7242/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7242", "date": "2019-11-05T08:01:35", "name": "net/mlx5: implement extensive metadata feature", "version": 1, "mbox": "http://patches.dpdk.org/series/7242/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/62427/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/62427/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ACD98A0352;\n\tTue, 5 Nov 2019 09:03:40 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E4361BEAA;\n\tTue, 5 Nov 2019 09:02:20 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 852D41BE86\n for <dev@dpdk.org>; Tue, 5 Nov 2019 09:02:13 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 5 Nov 2019 10:02:10 +0200", "from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx\n [10.210.16.104])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id xA582Aai026497;\n Tue, 5 Nov 2019 10:02:10 +0200", "from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id xA582AEa030774;\n Tue, 5 Nov 2019 08:02:10 GMT", "(from viacheslavo@localhost)\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id xA582AFt030773;\n Tue, 5 Nov 2019 08:02:10 GMT" ], "X-Authentication-Warning": "pegasus11.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net,\n orika@mellanox.com", "Date": "Tue, 5 Nov 2019 08:01:45 +0000", "Message-Id": "<1572940915-29416-11-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1572940915-29416-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1572940915-29416-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 10/20] net/mlx5: adjust shared register according\n\tto mask", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The metadata register reg_c[0] might be used by kernel or\nfirmware for their internal purposes. The actual used mask\ncan be queried from the kernel. The remaining bits can be\nused by PMD to provide META or MARK feature. The code queries\nthe mask of reg_c[0] and adjust the resource usage dynamically.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 95 +++++++++++++++++++++++++++++++++++------\n drivers/net/mlx5/mlx5.h | 3 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 26 +++++++++--\n 3 files changed, 107 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 943d0e8..fb7b94b 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1584,6 +1584,60 @@ struct mlx5_flow_id_pool *\n }\n \n /**\n+ * Configures the metadata mask fields in the shared context.\n+ *\n+ * @param [in] dev\n+ * Pointer to Ethernet device.\n+ */\n+static void\n+mlx5_set_metadata_mask(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_ibv_shared *sh = priv->sh;\n+\tuint32_t meta, mark, reg_c0;\n+\n+\treg_c0 = ~priv->vport_meta_mask;\n+\tswitch (priv->config.dv_xmeta_en) {\n+\tcase MLX5_XMETA_MODE_LEGACY:\n+\t\tmeta = UINT32_MAX;\n+\t\tmark = MLX5_FLOW_MARK_MASK;\n+\t\tbreak;\n+\tcase MLX5_XMETA_MODE_META16:\n+\t\tmeta = reg_c0 >> rte_bsf32(reg_c0);\n+\t\tmark = MLX5_FLOW_MARK_MASK;\n+\t\tbreak;\n+\tcase MLX5_XMETA_MODE_META32:\n+\t\tmeta = UINT32_MAX;\n+\t\tmark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;\n+\t\tbreak;\n+\tdefault:\n+\t\tmeta = 0;\n+\t\tmark = 0;\n+\t\tassert(false);\n+\t\tbreak;\n+\t}\n+\tif (sh->dv_mark_mask && sh->dv_mark_mask != mark)\n+\t\tDRV_LOG(WARNING, \"metadata MARK mask mismatche %08X:%08X\",\n+\t\t\t\t sh->dv_mark_mask, mark);\n+\telse\n+\t\tsh->dv_mark_mask = mark;\n+\tif (sh->dv_meta_mask && sh->dv_meta_mask != meta)\n+\t\tDRV_LOG(WARNING, \"metadata META mask mismatche %08X:%08X\",\n+\t\t\t\t sh->dv_meta_mask, meta);\n+\telse\n+\t\tsh->dv_meta_mask = meta;\n+\tif (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)\n+\t\tDRV_LOG(WARNING, \"metadata reg_c0 mask mismatche %08X:%08X\",\n+\t\t\t\t sh->dv_meta_mask, reg_c0);\n+\telse\n+\t\tsh->dv_regc0_mask = reg_c0;\n+\tDRV_LOG(DEBUG, \"metadata mode %u\", priv->config.dv_xmeta_en);\n+\tDRV_LOG(DEBUG, \"metadata MARK mask %08X\", sh->dv_mark_mask);\n+\tDRV_LOG(DEBUG, \"metadata META mask %08X\", sh->dv_meta_mask);\n+\tDRV_LOG(DEBUG, \"metadata reg_c0 mask %08X\", sh->dv_regc0_mask);\n+}\n+\n+/**\n * Allocate page of door-bells and register it using DevX API.\n *\n * @param [in] dev\n@@ -1803,7 +1857,7 @@ struct mlx5_flow_id_pool *\n \tuint16_t port_id;\n \tunsigned int i;\n #ifdef HAVE_MLX5DV_DR_DEVX_PORT\n-\tstruct mlx5dv_devx_port devx_port;\n+\tstruct mlx5dv_devx_port devx_port = { .comp_mask = 0 };\n #endif\n \n \t/* Determine if this port representor is supposed to be spawned. */\n@@ -2035,13 +2089,17 @@ struct mlx5_flow_id_pool *\n \t * vport index. The engaged part of metadata register is\n \t * defined by mask.\n \t */\n-\tdevx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |\n-\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0;\n-\terr = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port, &devx_port);\n-\tif (err) {\n-\t\tDRV_LOG(WARNING, \"can't query devx port %d on device %s\",\n-\t\t\tspawn->ibv_port, spawn->ibv_dev->name);\n-\t\tdevx_port.comp_mask = 0;\n+\tif (switch_info->representor || switch_info->master) {\n+\t\tdevx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |\n+\t\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0;\n+\t\terr = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,\n+\t\t\t\t\t\t &devx_port);\n+\t\tif (err) {\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"can't query devx port %d on device %s\",\n+\t\t\t\tspawn->ibv_port, spawn->ibv_dev->name);\n+\t\t\tdevx_port.comp_mask = 0;\n+\t\t}\n \t}\n \tif (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {\n \t\tpriv->vport_meta_tag = devx_port.reg_c_0.value;\n@@ -2361,18 +2419,27 @@ struct mlx5_flow_id_pool *\n \t\tgoto error;\n \t}\n \tpriv->config.flow_prio = err;\n-\t/* Query availibility of metadata reg_c's. */\n-\terr = mlx5_flow_discover_mreg_c(eth_dev);\n-\tif (err < 0) {\n-\t\terr = -err;\n-\t\tgoto error;\n-\t}\n \tif (!priv->config.dv_esw_en &&\n \t priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {\n \t\tDRV_LOG(WARNING, \"metadata mode %u is not supported \"\n \t\t\t\t \"(no E-Switch)\", priv->config.dv_xmeta_en);\n \t\tpriv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;\n \t}\n+\tmlx5_set_metadata_mask(eth_dev);\n+\tif (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&\n+\t !priv->sh->dv_regc0_mask) {\n+\t\tDRV_LOG(ERR, \"metadata mode %u is not supported \"\n+\t\t\t \"(no metadata reg_c[0] is available)\",\n+\t\t\t priv->config.dv_xmeta_en);\n+\t\t\terr = ENOTSUP;\n+\t\t\tgoto error;\n+\t}\n+\t/* Query availibility of metadata reg_c's. */\n+\terr = mlx5_flow_discover_mreg_c(eth_dev);\n+\tif (err < 0) {\n+\t\terr = -err;\n+\t\tgoto error;\n+\t}\n \tif (!mlx5_flow_ext_mreg_supported(eth_dev)) {\n \t\tDRV_LOG(DEBUG,\n \t\t\t\"port %u extensive metadata register is not supported\",\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex e59f8f6..92d445a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -622,6 +622,9 @@ struct mlx5_ibv_shared {\n \t} mr;\n \t/* Shared DV/DR flow data section. */\n \tpthread_mutex_t dv_mutex; /* DV context mutex. */\n+\tuint32_t dv_meta_mask; /* flow META metadata supported mask. */\n+\tuint32_t dv_mark_mask; /* flow MARK metadata supported mask. */\n+\tuint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */\n \tuint32_t dv_refcnt; /* DV/DR data reference counter. */\n \tvoid *fdb_domain; /* FDB Direct Rules name space handle. */\n \tstruct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 8b93022..049d6ae 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -899,13 +899,13 @@ struct field_modify_info modify_tcp[] = {\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev __rte_unused,\n+flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,\n \t\t\t\t struct mlx5_flow_dv_modify_hdr_resource *res,\n \t\t\t\t const struct rte_flow_action *action,\n \t\t\t\t struct rte_flow_error *error)\n {\n \tconst struct mlx5_flow_action_copy_mreg *conf = action->conf;\n-\tuint32_t mask = RTE_BE32(UINT32_MAX);\n+\trte_be32_t mask = RTE_BE32(UINT32_MAX);\n \tstruct rte_flow_item item = {\n \t\t.spec = NULL,\n \t\t.mask = &mask,\n@@ -915,9 +915,29 @@ struct field_modify_info modify_tcp[] = {\n \t\t{0, 0, 0},\n \t};\n \tstruct field_modify_info reg_dst = {\n-\t\t.offset = (uint32_t)-1, /* Same as src. */\n+\t\t.offset = 0,\n \t\t.id = reg_to_field[conf->dst],\n \t};\n+\t/* Adjust reg_c[0] usage according to reported mask. */\n+\tif (conf->dst == REG_C_0 || conf->src == REG_C_0) {\n+\t\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\t\tuint32_t reg_c0 = priv->sh->dv_regc0_mask;\n+\n+\t\tassert(reg_c0);\n+\t\tassert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);\n+\t\tif (conf->dst == REG_C_0) {\n+\t\t\t/* Copy to reg_c[0], within mask only. */\n+\t\t\treg_dst.offset = rte_bsf32(reg_c0);\n+\t\t\t/*\n+\t\t\t * Mask is ignoring the enianness, because\n+\t\t\t * there is no conversion in datapath.\n+\t\t\t */\n+\t\t\tmask = reg_c0 >> reg_dst.offset;\n+\t\t} else {\n+\t\t\t/* Copy from reg_c[0] to destination lower bits. */\n+\t\t\tmask = rte_cpu_to_be_32(reg_c0);\n+\t\t}\n+\t}\n \treturn flow_dv_convert_modify_action(&item,\n \t\t\t\t\t reg_src, ®_dst, res,\n \t\t\t\t\t MLX5_MODIFICATION_TYPE_COPY,\n", "prefixes": [ "10/20" ] }