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{
    "id": 61827,
    "url": "http://patches.dpdk.org/api/patches/61827/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191024074432.30705-7-somnath.kotur@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191024074432.30705-7-somnath.kotur@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191024074432.30705-7-somnath.kotur@broadcom.com",
    "date": "2019-10-24T07:44:21",
    "name": "[06/17] net/bnxt: update HWRM API to version 1.10.1.6",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "a6c35a09cf7aa3cbcc28ead7f8e20bc904446b92",
    "submitter": {
        "id": 908,
        "url": "http://patches.dpdk.org/api/people/908/?format=api",
        "name": "Somnath Kotur",
        "email": "somnath.kotur@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191024074432.30705-7-somnath.kotur@broadcom.com/mbox/",
    "series": [
        {
            "id": 7031,
            "url": "http://patches.dpdk.org/api/series/7031/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7031",
            "date": "2019-10-24T07:44:16",
            "name": "bnxt patchset with bug fixes",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/7031/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/61827/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/61827/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3BFE71D444;\n\tThu, 24 Oct 2019 09:52:43 +0200 (CEST)",
            "from relay.smtp.broadcom.com (unknown [192.19.232.149])\n\tby dpdk.org (Postfix) with ESMTP id 9B56F1D407\n\tfor <dev@dpdk.org>; Thu, 24 Oct 2019 09:52:25 +0200 (CEST)",
            "from dhcp-10-123-153-55.dhcp.broadcom.net\n\t(dhcp-10-123-153-55.dhcp.broadcom.net [10.123.153.55])\n\tby relay.smtp.broadcom.com (Postfix) with ESMTP id F27D61B9E23;\n\tThu, 24 Oct 2019 00:52:23 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.10.3 relay.smtp.broadcom.com F27D61B9E23",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1571903545;\n\tbh=4rb+YunbvC76q5jiGCqRC+gj8q6ZOBPDtG0OJGwOgXE=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=gMcFPJsyac1OmW8LT9u1rim2LgU5+Uhew5hCYqxq0MBFG2aqKkdadAHApa0IAzJpN\n\tK+3aEa2ST/6s7+epreruKEGZZXlikdbz3KUSTfOcLDXsVK8hMO6y0Yb4teAAUmutez\n\tsesXyxzAp39pSzZ7YOqgmpUmHGOElzG586ZXaIHE=",
        "From": "Somnath Kotur <somnath.kotur@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com",
        "Date": "Thu, 24 Oct 2019 13:14:21 +0530",
        "Message-Id": "<20191024074432.30705-7-somnath.kotur@broadcom.com>",
        "X-Mailer": "git-send-email 2.10.1.613.g2cc2e70",
        "In-Reply-To": "<20191024074432.30705-1-somnath.kotur@broadcom.com>",
        "References": "<20191024074432.30705-1-somnath.kotur@broadcom.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 06/17] net/bnxt: update HWRM API to version\n\t1.10.1.6",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Ajit Khaparde <ajit.khaparde@broadcom.com>\n\nUpdate HWRM API to version 1.10.1.6\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Kalesh Anakkur Purayil <kalesh-anakkur.purayil@broadcom.com>\nSigned-off-by: Somnath Kotur <somnath.kotur@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 2273 +++++++++++++++++++++++++-------\n 1 file changed, 1818 insertions(+), 455 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex c45d088..cb41768 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -80,16 +80,18 @@ struct hwrm_resp_hdr {\n #define TLV_TYPE_ENGINE_CKV_AUTH_TAG             UINT32_C(0x8004)\n /* Engine CKV - The encrypted data. */\n #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           UINT32_C(0x8005)\n-/* Engine CKV - Supported algorithms. */\n-#define TLV_TYPE_ENGINE_CKV_ALGORITHMS           UINT32_C(0x8006)\n+/* Engine CKV - Supported host_algorithms. */\n+#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      UINT32_C(0x8006)\n /* Engine CKV - The Host EC curve name and ECC public key information. */\n #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  UINT32_C(0x8007)\n /* Engine CKV - The ECDSA signature. */\n #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      UINT32_C(0x8008)\n-/* Engine CKV - The SRT EC curve name and ECC public key information. */\n-#define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY   UINT32_C(0x8009)\n+/* Engine CKV - The firmware EC curve name and ECC public key information. */\n+#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    UINT32_C(0x8009)\n+/* Engine CKV - Supported firmware algorithms. */\n+#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        UINT32_C(0x800a)\n #define TLV_TYPE_LAST \\\n-\tTLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY\n+\tTLV_TYPE_ENGINE_CKV_FW_ALGORITHMS\n \n \n /* tlv (size:64b/8B) */\n@@ -319,11 +321,8 @@ struct cmd_nums {\n \t#define HWRM_QUEUE_PRI2COS_CFG                    UINT32_C(0x38)\n \t#define HWRM_QUEUE_COS2BW_QCFG                    UINT32_C(0x39)\n \t#define HWRM_QUEUE_COS2BW_CFG                     UINT32_C(0x3a)\n-\t/* Experimental */\n \t#define HWRM_QUEUE_DSCP_QCAPS                     UINT32_C(0x3b)\n-\t/* Experimental */\n \t#define HWRM_QUEUE_DSCP2PRI_QCFG                  UINT32_C(0x3c)\n-\t/* Experimental */\n \t#define HWRM_QUEUE_DSCP2PRI_CFG                   UINT32_C(0x3d)\n \t#define HWRM_VNIC_ALLOC                           UINT32_C(0x40)\n \t#define HWRM_VNIC_FREE                            UINT32_C(0x41)\n@@ -351,6 +350,9 @@ struct cmd_nums {\n \t#define HWRM_RESERVED6                            UINT32_C(0x65)\n \t#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            UINT32_C(0x70)\n \t#define HWRM_VNIC_RSS_COS_LB_CTX_FREE             UINT32_C(0x71)\n+\t#define HWRM_QUEUE_MPLS_QCAPS                     UINT32_C(0x80)\n+\t#define HWRM_QUEUE_MPLSTC2PRI_QCFG                UINT32_C(0x81)\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG                 UINT32_C(0x82)\n \t#define HWRM_CFA_L2_FILTER_ALLOC                  UINT32_C(0x90)\n \t#define HWRM_CFA_L2_FILTER_FREE                   UINT32_C(0x91)\n \t#define HWRM_CFA_L2_FILTER_CFG                    UINT32_C(0x92)\n@@ -382,11 +384,13 @@ struct cmd_nums {\n \t#define HWRM_PORT_QSTATS_EXT                      UINT32_C(0xb4)\n \t#define HWRM_PORT_PHY_MDIO_WRITE                  UINT32_C(0xb5)\n \t#define HWRM_PORT_PHY_MDIO_READ                   UINT32_C(0xb6)\n+\t#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            UINT32_C(0xb7)\n+\t#define HWRM_PORT_PHY_MDIO_BUS_RELEASE            UINT32_C(0xb8)\n \t#define HWRM_FW_RESET                             UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS                           UINT32_C(0xc1)\n \t#define HWRM_FW_HEALTH_CHECK                      UINT32_C(0xc2)\n \t#define HWRM_FW_SYNC                              UINT32_C(0xc3)\n-\t#define HWRM_FW_STATE_BUFFER_QCAPS                UINT32_C(0xc4)\n+\t#define HWRM_FW_STATE_QCAPS                       UINT32_C(0xc4)\n \t#define HWRM_FW_STATE_QUIESCE                     UINT32_C(0xc5)\n \t#define HWRM_FW_STATE_BACKUP                      UINT32_C(0xc6)\n \t#define HWRM_FW_STATE_RESTORE                     UINT32_C(0xc7)\n@@ -407,7 +411,14 @@ struct cmd_nums {\n \t#define HWRM_OEM_CMD                              UINT32_C(0xd4)\n \t/* Tells the fw to run PRBS test on a given port and lane. */\n \t#define HWRM_PORT_PRBS_TEST                       UINT32_C(0xd5)\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG                UINT32_C(0xd6)\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG               UINT32_C(0xd7)\n+\t#define HWRM_FW_STATE_UNQUIESCE                   UINT32_C(0xd8)\n+\t/* Tells the fw to collect dsc dump on a given port and lane. */\n+\t#define HWRM_PORT_DSC_DUMP                        UINT32_C(0xd9)\n \t#define HWRM_TEMP_MONITOR_QUERY                   UINT32_C(0xe0)\n+\t#define HWRM_REG_POWER_QUERY                      UINT32_C(0xe1)\n+\t#define HWRM_CORE_FREQUENCY_QUERY                 UINT32_C(0xe2)\n \t#define HWRM_WOL_FILTER_ALLOC                     UINT32_C(0xf0)\n \t#define HWRM_WOL_FILTER_FREE                      UINT32_C(0xf1)\n \t#define HWRM_WOL_FILTER_QCFG                      UINT32_C(0xf2)\n@@ -561,6 +572,8 @@ struct cmd_nums {\n \t#define HWRM_ENGINE_STATS_CLEAR                   UINT32_C(0x156)\n \t/* Engine - Query the statistics accumulator for an Engine. */\n \t#define HWRM_ENGINE_STATS_QUERY                   UINT32_C(0x157)\n+\t/* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */\n+\t#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  UINT32_C(0x158)\n \t/* Engine - Allocate an Engine RQ. */\n \t#define HWRM_ENGINE_RQ_ALLOC                      UINT32_C(0x15e)\n \t/* Engine - Free an Engine RQ. */\n@@ -731,7 +744,7 @@ struct ret_codes {\n \t#define HWRM_ERR_CODE_HOT_RESET_FAIL               UINT32_C(0xb)\n \t/*\n \t * This error code is only reported by the firmware when during\n-\t * flow allocation when a requeest for a flow counter fails because\n+\t * flow allocation when a request for a flow counter fails because\n \t * the number of flow counters are exhausted.\n \t */\n \t#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)\n@@ -753,10 +766,15 @@ struct ret_codes {\n \t */\n \t#define HWRM_ERR_CODE_HWRM_ERROR                   UINT32_C(0xf)\n \t/*\n+\t * Firmware is unable to service the request at the present time. Caller\n+\t * may try again later.\n+\t */\n+\t#define HWRM_ERR_CODE_BUSY                         UINT32_C(0x10)\n+\t/*\n \t * This value indicates that the HWRM response is in TLV format and\n \t * should be interpreted as one or more TLVs starting with the\n-\t * hwrm_resp_hdr TLV. This value is not an indicatation of any error\n-\t * by itself, just an indicatation that the response should be parsed\n+\t * hwrm_resp_hdr TLV. This value is not an indication of any error\n+\t * by itself, just an indication that the response should be parsed\n \t * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.\n \t */\n \t#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    UINT32_C(0x8000)\n@@ -837,10 +855,10 @@ struct hwrm_err_output {\n #define HWRM_TARGET_ID_TOOLS 0xFFFD\n #define HWRM_VERSION_MAJOR 1\n #define HWRM_VERSION_MINOR 10\n-#define HWRM_VERSION_UPDATE 0\n+#define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 91\n-#define HWRM_VERSION_STR \"1.10.0.91\"\n+#define HWRM_VERSION_RSVD 6\n+#define HWRM_VERSION_STR \"1.10.1.6\"\n \n /****************\n  * hwrm_ver_get *\n@@ -1395,12 +1413,12 @@ struct bd_base {\n \t#define BD_BASE_TYPE_TX_BD_SHORT        UINT32_C(0x0)\n \t/*\n \t * Indicates that this BD is 1BB long and is an empty\n-\t * TX BD.  Not valid for use by the driver.\n+\t * TX BD. Not valid for use by the driver.\n \t */\n \t#define BD_BASE_TYPE_TX_BD_EMPTY        UINT32_C(0x1)\n \t/*\n \t * Indicates that this BD is 16B long and is an RX Producer\n-\t * (ie. empty) buffer descriptor.\n+\t * (i.e. empty) buffer descriptor.\n \t */\n \t#define BD_BASE_TYPE_RX_PROD_PKT        UINT32_C(0x4)\n \t/*\n@@ -1454,7 +1472,7 @@ struct tx_bd_short {\n \t#define TX_BD_SHORT_FLAGS_SFT            6\n \t/*\n \t * If set to 1, the packet ends with the data in the buffer\n-\t * pointed to by this descriptor.  This flag must be\n+\t * pointed to by this descriptor. This flag must be\n \t * valid on every BD.\n \t */\n \t#define TX_BD_SHORT_FLAGS_PACKET_END      UINT32_C(0x40)\n@@ -1472,9 +1490,9 @@ struct tx_bd_short {\n \t * This value indicates how many 16B BD locations are consumed\n \t * in the ring by this packet.\n \t * A value of 1 indicates that this BD is the only BD (and that\n-\t * the it is a short BD).  A value\n+\t * it is a short BD). A value\n \t * of 3 indicates either 3 short BDs or 1 long BD and one short\n-\t * BD in the packet.  A value of 0 indicates\n+\t * BD in the packet. A value of 0 indicates\n \t * that there are 32 BD locations in the packet (the maximum).\n \t *\n \t * This field is valid only on the first BD of a packet.\n@@ -1562,7 +1580,7 @@ struct tx_bd_long {\n \t#define TX_BD_LONG_FLAGS_SFT            6\n \t/*\n \t * If set to 1, the packet ends with the data in the buffer\n-\t * pointed to by this descriptor.  This flag must be\n+\t * pointed to by this descriptor. This flag must be\n \t * valid on every BD.\n \t */\n \t#define TX_BD_LONG_FLAGS_PACKET_END      UINT32_C(0x40)\n@@ -1580,9 +1598,9 @@ struct tx_bd_long {\n \t * This value indicates how many 16B BD locations are consumed\n \t * in the ring by this packet.\n \t * A value of 1 indicates that this BD is the only BD (and that\n-\t * the it is a short BD).  A value\n+\t * it is a short BD). A value\n \t * of 3 indicates either 3 short BDs or 1 long BD and one short\n-\t * BD in the packet.  A value of 0 indicates\n+\t * BD in the packet. A value of 0 indicates\n \t * that there are 32 BD locations in the packet (the maximum).\n \t *\n \t * This field is valid only on the first BD of a packet.\n@@ -1663,7 +1681,7 @@ struct tx_bd_long_hi {\n \t */\n \t#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM     UINT32_C(0x1)\n \t/*\n-\t * If set to 1,  the controller replaces the IP checksum of the\n+\t * If set to 1, the controller replaces the IP checksum of the\n \t * normal packets, or the inner IP checksum of the encapsulated\n \t * packets with the hardware calculated IP checksum for the\n \t * packet associated with this descriptor.\n@@ -1677,9 +1695,9 @@ struct tx_bd_long_hi {\n \t *\n \t * This bit must be valid on the first BD of a packet.\n \t *\n-\t * Packet must be 64B or longer when this flag is set.  It is not\n+\t * Packet must be 64B or longer when this flag is set. It is not\n \t * useful to use this bit with any form of TX offload such as\n-\t * CSO or LSO.  The intent is that the packet from the host already\n+\t * CSO or LSO. The intent is that the packet from the host already\n \t * has a valid Ethernet CRC on the packet.\n \t */\n \t#define TX_BD_LONG_LFLAGS_NOCRC              UINT32_C(0x4)\n@@ -1708,9 +1726,9 @@ struct tx_bd_long_hi {\n \t */\n \t#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM        UINT32_C(0x10)\n \t/*\n-\t * If set to 1,  the device will treat this packet with LSO(Large\n+\t * If set to 1, the device will treat this packet with LSO(Large\n \t * Send Offload) processing for both normal or encapsulated\n-\t * packets, which is a form of TCP segmentation.  When this bit\n+\t * packets, which is a form of TCP segmentation. When this bit\n \t * is 1, the hdr_size and mss fields must be valid. The driver\n \t * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum\n \t * flags since the controller will replace the appropriate\n@@ -1743,19 +1761,19 @@ struct tx_bd_long_hi {\n \t#define TX_BD_LONG_LFLAGS_T_IPID             UINT32_C(0x80)\n \t/*\n \t * If set to '1', then the RoCE ICRC will be appended to the\n-\t * packet.  Packet must be a valid RoCE format packet.\n+\t * packet. Packet must be a valid RoCE format packet.\n \t */\n \t#define TX_BD_LONG_LFLAGS_ROCE_CRC           UINT32_C(0x100)\n \t/*\n \t * If set to '1', then the FCoE CRC will be appended to the\n-\t * packet.  Packet must be a valid FCoE format packet.\n+\t * packet. Packet must be a valid FCoE format packet.\n \t */\n \t#define TX_BD_LONG_LFLAGS_FCOE_CRC           UINT32_C(0x200)\n \tuint16_t\thdr_size;\n \t/*\n \t * When LSO is '1', this field must contain the offset of the\n \t * TCP payload from the beginning of the packet in as\n-\t * 16b words. In case of encapsulated/tunneling packet, this  field\n+\t * 16b words. In case of encapsulated/tunneling packet, this field\n \t * contains the offset of the inner TCP payload from beginning of the\n \t * packet as 16-bit words.\n \t *\n@@ -1862,7 +1880,7 @@ struct tx_bd_long_inline {\n \t#define TX_BD_LONG_INLINE_FLAGS_SFT             6\n \t/*\n \t * If set to 1, the packet ends with the data in the buffer\n-\t * pointed to by this descriptor.  This flag must be\n+\t * pointed to by this descriptor. This flag must be\n \t * valid on every BD.\n \t */\n \t#define TX_BD_LONG_INLINE_FLAGS_PACKET_END       UINT32_C(0x40)\n@@ -1967,12 +1985,12 @@ struct tx_bd_long_inline {\n \t#define TX_BD_LONG_INLINE_LFLAGS_T_IPID             UINT32_C(0x80)\n \t/*\n \t * If set to '1', then the RoCE ICRC will be appended to the\n-\t * packet.  Packet must be a valid RoCE format packet.\n+\t * packet. Packet must be a valid RoCE format packet.\n \t */\n \t#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC           UINT32_C(0x100)\n \t/*\n \t * If set to '1', then the FCoE CRC will be appended to the\n-\t * packet.  Packet must be a valid FCoE format packet.\n+\t * packet. Packet must be a valid FCoE format packet.\n \t */\n \t#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC           UINT32_C(0x200)\n \tuint16_t\tunused2;\n@@ -2055,7 +2073,7 @@ struct tx_bd_empty {\n \t#define TX_BD_EMPTY_TYPE_SFT        0\n \t/*\n \t * Indicates that this BD is 1BB long and is an empty\n-\t * TX BD.  Not valid for use by the driver.\n+\t * TX BD. Not valid for use by the driver.\n \t */\n \t#define TX_BD_EMPTY_TYPE_TX_BD_EMPTY  UINT32_C(0x1)\n \t#define TX_BD_EMPTY_TYPE_LAST        TX_BD_EMPTY_TYPE_TX_BD_EMPTY\n@@ -2074,7 +2092,7 @@ struct rx_prod_pkt_bd {\n \t#define RX_PROD_PKT_BD_TYPE_SFT          0\n \t/*\n \t * Indicates that this BD is 16B long and is an RX Producer\n-\t * (ie. empty) buffer descriptor.\n+\t * (i.e. empty) buffer descriptor.\n \t */\n \t#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT    UINT32_C(0x4)\n \t#define RX_PROD_PKT_BD_TYPE_LAST \\\n@@ -2083,7 +2101,7 @@ struct rx_prod_pkt_bd {\n \t#define RX_PROD_PKT_BD_FLAGS_SFT         6\n \t/*\n \t * If set to 1, the packet will be placed at the address plus\n-\t * 2B.  The 2 Bytes of padding will be written as zero.\n+\t * 2B. The 2 Bytes of padding will be written as zero.\n \t */\n \t#define RX_PROD_PKT_BD_FLAGS_SOP_PAD      UINT32_C(0x40)\n \t/*\n@@ -2093,9 +2111,9 @@ struct rx_prod_pkt_bd {\n \t#define RX_PROD_PKT_BD_FLAGS_EOP_PAD      UINT32_C(0x80)\n \t/*\n \t * This value is the number of additional buffers in the ring that\n-\t * describe the buffer space to be consumed for the this packet.\n+\t * describe the buffer space to be consumed for this packet.\n \t * If the value is zero, then the packet must fit within the\n-\t * space described by this BD.  If this value is 1 or more, it\n+\t * space described by this BD. If this value is 1 or more, it\n \t * indicates how many additional \"buffer\" BDs are in the ring\n \t * immediately following this BD to be used for the same\n \t * network packet.\n@@ -2118,7 +2136,7 @@ struct rx_prod_pkt_bd {\n \tuint32_t\topaque;\n \t/*\n \t * This is the host physical address where data for the packet may\n-\t * by placed in host memory.\n+\t * be placed in host memory.\n \t */\n \tuint64_t\taddress;\n } __attribute__((packed));\n@@ -2147,7 +2165,7 @@ struct rx_prod_bfr_bd {\n \tuint32_t\topaque;\n \t/*\n \t * This is the host physical address where data for the packet may\n-\t * by placed in host memory.\n+\t * be placed in host memory.\n \t */\n \tuint64_t\taddress;\n } __attribute__((packed));\n@@ -2186,7 +2204,7 @@ struct rx_prod_agg_bd {\n \tuint32_t\topaque;\n \t/*\n \t * This is the host physical address where data for the packet may\n-\t * by placed in host memory.\n+\t * be placed in host memory.\n \t */\n \tuint64_t\taddress;\n } __attribute__((packed));\n@@ -2197,15 +2215,15 @@ struct cmpl_base {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define CMPL_BASE_TYPE_MASK            UINT32_C(0x3f)\n \t#define CMPL_BASE_TYPE_SFT             0\n \t/*\n \t * TX L2 completion:\n-\t * Completion of TX packet.  Length = 16B\n+\t * Completion of TX packet. Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_TX_L2             UINT32_C(0x0)\n \t/*\n@@ -2216,7 +2234,7 @@ struct cmpl_base {\n \t/*\n \t * RX Aggregation Buffer completion :\n \t * Completion of an L2 aggregation buffer in support of\n-\t * TPA, HDS, or Jumbo packet completion.  Length = 16B\n+\t * TPA, HDS, or Jumbo packet completion. Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_RX_AGG            UINT32_C(0x12)\n \t/*\n@@ -2265,8 +2283,8 @@ struct cmpl_base {\n \tuint32_t\tinfo2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \tuint32_t\tinfo3_v;\n \t#define CMPL_BASE_V         UINT32_C(0x1)\n@@ -2282,15 +2300,15 @@ struct tx_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define TX_CMPL_TYPE_MASK       UINT32_C(0x3f)\n \t#define TX_CMPL_TYPE_SFT        0\n \t/*\n \t * TX L2 completion:\n-\t * Completion of TX packet.  Length = 16B\n+\t * Completion of TX packet. Length = 16B\n \t */\n \t#define TX_CMPL_TYPE_TX_L2        UINT32_C(0x0)\n \t#define TX_CMPL_TYPE_LAST        TX_CMPL_TYPE_TX_L2\n@@ -2298,14 +2316,14 @@ struct tx_cmpl {\n \t#define TX_CMPL_FLAGS_SFT       6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type.  Type of error is indicated in\n+\t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n \t#define TX_CMPL_FLAGS_ERROR      UINT32_C(0x40)\n \t/*\n \t * When this bit is '1', it indicates that the packet completed\n \t * was transmitted using the push acceleration data provided\n-\t * by the driver.  When this bit is '0', it indicates that the\n+\t * by the driver. When this bit is '0', it indicates that the\n \t * packet had not push acceleration data written or was executed\n \t * as a normal packet even though push data was provided.\n \t */\n@@ -2320,8 +2338,8 @@ struct tx_cmpl {\n \tuint16_t\terrors_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define TX_CMPL_V                              UINT32_C(0x1)\n \t#define TX_CMPL_ERRORS_MASK                    UINT32_C(0xfffe)\n@@ -2343,7 +2361,7 @@ struct tx_cmpl {\n \t\tTX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT\n \t/*\n \t * When this bit is '1', it indicates that the length of\n-\t * the packet was zero.  No packet was transmitted.\n+\t * the packet was zero. No packet was transmitted.\n \t */\n \t#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT          UINT32_C(0x10)\n \t/*\n@@ -2360,7 +2378,7 @@ struct tx_cmpl {\n \t#define TX_CMPL_ERRORS_DMA_ERROR                UINT32_C(0x40)\n \t/*\n \t * When this bit is '1', it indicates that the packet was longer\n-\t * than indicated by the hint.  No packet was transmitted.\n+\t * than indicated by the hint. No packet was transmitted.\n \t */\n \t#define TX_CMPL_ERRORS_HINT_TOO_SHORT           UINT32_C(0x80)\n \t/*\n@@ -2381,8 +2399,8 @@ struct rx_pkt_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_PKT_CMPL_TYPE_MASK                   UINT32_C(0x3f)\n@@ -2397,7 +2415,7 @@ struct rx_pkt_cmpl {\n \t#define RX_PKT_CMPL_FLAGS_SFT                   6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type.  Type of error is indicated in\n+\t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n \t#define RX_PKT_CMPL_FLAGS_ERROR                  UINT32_C(0x40)\n@@ -2498,9 +2516,9 @@ struct rx_pkt_cmpl {\n \t\tRX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP\n \t/*\n \t * This is the length of the data for the packet stored in the\n-\t * buffer(s) identified by the opaque value.  This includes\n-\t * the packet BD and any associated buffer BDs.  This does not include\n-\t * the the length of any data places in aggregation BDs.\n+\t * buffer(s) identified by the opaque value. This includes\n+\t * the packet BD and any associated buffer BDs. This does not include\n+\t * the length of any data places in aggregation BDs.\n \t */\n \tuint16_t\tlen;\n \t/*\n@@ -2511,8 +2529,8 @@ struct rx_pkt_cmpl {\n \tuint8_t\tagg_bufs_v1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_PKT_CMPL_V1           UINT32_C(0x1)\n \t/*\n@@ -2527,7 +2545,7 @@ struct rx_pkt_cmpl {\n \t#define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)\n \t#define RX_PKT_CMPL_UNUSED1_SFT  6\n \t/*\n-\t * This is the RSS hash type for the packet.  The value is packed\n+\t * This is the RSS hash type for the packet. The value is packed\n \t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n \t *\n \t * The value of tuple_extrac_op provides the information about\n@@ -2558,7 +2576,7 @@ struct rx_pkt_cmpl {\n \tuint8_t\trss_hash_type;\n \t/*\n \t * This value indicates the offset in bytes from the beginning of the packet\n-\t * where the inner payload starts.  This value is valid for TCP, UDP,\n+\t * where the inner payload starts. This value is valid for TCP, UDP,\n \t * FCoE, and RoCE packets.\n \t *\n \t * A value of zero indicates that header is 256B into the packet.\n@@ -2604,7 +2622,7 @@ struct rx_pkt_cmpl_hi {\n \t/* This value indicates what format the metadata field is. */\n \t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK           UINT32_C(0xf0)\n \t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT            4\n-\t/* No metadata informtaion.  Value is zero. */\n+\t/* No metadata information. Value is zero. */\n \t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \\\n \t\t(UINT32_C(0x0) << 4)\n \t/*\n@@ -2623,7 +2641,7 @@ struct rx_pkt_cmpl_hi {\n \t * - VXLAN = VNI[23:0] -> VXLAN Network ID\n \t * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.\n \t * - NVGRE = TNI[23:0] -> Tenant Network ID\n-\t * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0\n+\t * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0\n \t * - IPV4 = 0 (not populated)\n \t * - IPV6 = Flow Label[19:0]\n \t * - PPPoE = sessionID[15:0]\n@@ -2653,7 +2671,7 @@ struct rx_pkt_cmpl_hi {\n \t\tRX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET\n \t/*\n \t * This field indicates the IP type for the inner-most IP header.\n-\t * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.\n+\t * A value of '0' indicates IPv4. A value of '1' indicates IPv6.\n \t * This value is only valid if itype indicates a packet\n \t * with an IP header.\n \t */\n@@ -2697,8 +2715,8 @@ struct rx_pkt_cmpl_hi {\n \tuint16_t\terrors_v2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_PKT_CMPL_V2 \\\n \t\tUINT32_C(0x1)\n@@ -2708,7 +2726,7 @@ struct rx_pkt_cmpl_hi {\n \t/*\n \t * This error indicates that there was some sort of problem with\n \t * the BDs for the packet that was found after part of the\n-\t * packet was already placed.  The packet should be treated as\n+\t * packet was already placed. The packet should be treated as\n \t * invalid.\n \t */\n \t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \\\n@@ -2721,7 +2739,7 @@ struct rx_pkt_cmpl_hi {\n \t * Did Not Fit:\n \t * Packet did not fit into packet buffer provided.\n \t * For regular placement, this means the packet did not fit\n-\t * in the buffer provided.  For HDS and jumbo placement, this\n+\t * in the buffer provided. For HDS and jumbo placement, this\n \t * means that the packet could not be placed into 7 physical\n \t * buffers or less.\n \t */\n@@ -2774,7 +2792,7 @@ struct rx_pkt_cmpl_hi {\n \t\tUINT32_C(0x80)\n \t/*\n \t * This indicates that there was a CRC error on either an FCoE\n-\t * or RoCE packet.  The itype indicates the packet type.\n+\t * or RoCE packet. The itype indicates the packet type.\n \t */\n \t#define RX_PKT_CMPL_ERRORS_CRC_ERROR \\\n \t\tUINT32_C(0x100)\n@@ -2912,7 +2930,7 @@ struct rx_pkt_cmpl_hi {\n \t * This value holds the reordering sequence number for the packet.\n \t * If the reordering sequence is not valid, then this value is zero.\n \t * The reordering domain for the packet is in the bottom 8 to 10b of\n-\t * the rss_hash value.  The bottom 20b of this value contain the\n+\t * the rss_hash value. The bottom 20b of this value contain the\n \t * ordering domain value for the packet.\n \t */\n \t#define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)\n@@ -2929,8 +2947,8 @@ struct rx_tpa_start_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_TPA_START_CMPL_TYPE_MASK                UINT32_C(0x3f)\n@@ -2952,9 +2970,9 @@ struct rx_tpa_start_cmpl {\n \t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT       7\n \t/*\n \t * Jumbo:\n-\t * TPA Packet was placed using jumbo algorithm.  This means\n+\t * TPA Packet was placed using jumbo algorithm. This means\n \t * that the first buffer will be filled with data before\n-\t * moving to aggregation buffers.  Each aggregation buffer\n+\t * moving to aggregation buffers. Each aggregation buffer\n \t * will be filled before moving to the next aggregation\n \t * buffer.\n \t */\n@@ -3020,19 +3038,19 @@ struct rx_tpa_start_cmpl {\n \tuint32_t\topaque;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \tuint8_t\tv1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)\n \t#define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1\n \t/*\n-\t * This is the RSS hash type for the packet.  The value is packed\n+\t * This is the RSS hash type for the packet. The value is packed\n \t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n \t *\n \t * The value of tuple_extrac_op provides the information about\n@@ -3063,7 +3081,7 @@ struct rx_tpa_start_cmpl {\n \tuint8_t\trss_hash_type;\n \t/*\n \t * This is the aggregation ID that the completion is associated\n-\t * with.  Use this number to correlate the TPA start completion\n+\t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n \tuint16_t\tagg_id;\n@@ -3072,7 +3090,7 @@ struct rx_tpa_start_cmpl {\n \t#define RX_TPA_START_CMPL_UNUSED2_SFT 0\n \t/*\n \t * This is the aggregation ID that the completion is associated\n-\t * with.  Use this number to correlate the TPA start completion\n+\t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n \t#define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)\n@@ -3120,7 +3138,7 @@ struct rx_tpa_start_cmpl_hi {\n \t/* This value indicates what format the metadata field is. */\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT  4\n-\t/* No metadata information.  Value is zero. */\n+\t/* No metadata information. Value is zero. */\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \\\n \t\t(UINT32_C(0x0) << 4)\n \t/*\n@@ -3136,7 +3154,7 @@ struct rx_tpa_start_cmpl_hi {\n \t\tRX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN\n \t/*\n \t * This field indicates the IP type for the inner-most IP header.\n-\t * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.\n+\t * A value of '0' indicates IPv4. A value of '1' indicates IPv6.\n \t */\n \t#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE          UINT32_C(0x100)\n \t/*\n@@ -3158,8 +3176,8 @@ struct rx_tpa_start_cmpl_hi {\n \tuint16_t\tv2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_START_CMPL_V2     UINT32_C(0x1)\n \t/*\n@@ -3175,7 +3193,7 @@ struct rx_tpa_start_cmpl_hi {\n \tuint32_t\tinner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;\n \t/*\n \t * This is the offset from the beginning of the packet in bytes for\n-\t * the outer L3 header.  If there is no outer L3 header, then this\n+\t * the outer L3 header. If there is no outer L3 header, then this\n \t * value is zero.\n \t */\n \t#define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)\n@@ -3211,8 +3229,8 @@ struct rx_tpa_end_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_TPA_END_CMPL_TYPE_MASK                UINT32_C(0x3f)\n@@ -3229,7 +3247,7 @@ struct rx_tpa_end_cmpl {\n \t#define RX_TPA_END_CMPL_FLAGS_SFT                6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type.  Type of error is indicated in\n+\t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n \t#define RX_TPA_END_CMPL_FLAGS_ERROR               UINT32_C(0x40)\n@@ -3238,9 +3256,9 @@ struct rx_tpa_end_cmpl {\n \t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT       7\n \t/*\n \t * Jumbo:\n-\t * TPA Packet was placed using jumbo algorithm.  This means\n+\t * TPA Packet was placed using jumbo algorithm. This means\n \t * that the first buffer will be filled with data before\n-\t * moving to aggregation buffers.  Each aggregation buffer\n+\t * moving to aggregation buffers. Each aggregation buffer\n \t * will be filled before moving to the next aggregation\n \t * buffer.\n \t */\n@@ -3283,7 +3301,7 @@ struct rx_tpa_end_cmpl {\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n \t * - 2 TCP Packet\n-\t *     Indicates that the packet was IP and TCP.  This indicates\n+\t *     Indicates that the packet was IP and TCP. This indicates\n \t *     that the ip_cs field is valid and that the tcp_udp_cs\n \t *     field is valid and contains the TCP checksum.\n \t *     This also indicates that the payload_offset field is valid.\n@@ -3303,14 +3321,14 @@ struct rx_tpa_end_cmpl {\n \tuint32_t\topaque;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \tuint8_t\tagg_bufs_v1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_END_CMPL_V1           UINT32_C(0x1)\n \t/*\n@@ -3326,7 +3344,7 @@ struct rx_tpa_end_cmpl {\n \tuint8_t\ttpa_segs;\n \t/*\n \t * This value indicates the offset in bytes from the beginning of the packet\n-\t * where the inner payload starts.  This value is valid for TCP, UDP,\n+\t * where the inner payload starts. This value is valid for TCP, UDP,\n \t * FCoE, and RoCE packets.\n \t *\n \t * A value of zero indicates an offset of 256 bytes.\n@@ -3337,7 +3355,7 @@ struct rx_tpa_end_cmpl {\n \t#define RX_TPA_END_CMPL_UNUSED2     UINT32_C(0x1)\n \t/*\n \t * This is the aggregation ID that the completion is associated\n-\t * with.  Use this number to correlate the TPA start completion\n+\t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n \t#define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)\n@@ -3351,8 +3369,8 @@ struct rx_tpa_end_cmpl {\n \t * For GRO packets, this field is zero except for the following\n \t * sub-fields.\n \t * - tsdelta[31]\n-\t *     Timestamp present indication.  When '0', no Timestamp\n-\t *     option is in the packet.  When '1', then a Timestamp\n+\t *     Timestamp present indication. When '0', no Timestamp\n+\t *     option is in the packet. When '1', then a Timestamp\n \t *     option is present in the packet.\n \t */\n \tuint32_t\ttsdelta;\n@@ -3374,13 +3392,13 @@ struct rx_tpa_end_cmpl_hi {\n \t#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)\n \t#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0\n \t/*\n-\t * This value is the valid when TPA completion is active.  It\n+\t * This value is the valid when TPA completion is active. It\n \t * indicates the length of the longest segment of the TPA operation\n \t * for LRO mode and the length of the first segment in GRO mode.\n \t *\n \t * This value may be used by GRO software to re-construct the original\n-\t * packet stream from the TPA packet.  This is the length of all\n-\t * but the last segment for GRO.  In LRO mode this value may be used\n+\t * packet stream from the TPA packet. This is the length of all\n+\t * but the last segment for GRO. In LRO mode this value may be used\n \t * to indicate MSS size to the stack.\n \t */\n \tuint16_t\ttpa_seg_len;\n@@ -3389,8 +3407,8 @@ struct rx_tpa_end_cmpl_hi {\n \tuint16_t\terrors_v2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_END_CMPL_V2                             UINT32_C(0x1)\n \t#define RX_TPA_END_CMPL_ERRORS_MASK                    UINT32_C(0xfffe)\n@@ -3398,14 +3416,14 @@ struct rx_tpa_end_cmpl_hi {\n \t/*\n \t * This error indicates that there was some sort of problem with\n \t * the BDs for the packet that was found after part of the\n-\t * packet was already placed.  The packet should be treated as\n+\t * packet was already placed. The packet should be treated as\n \t * invalid.\n \t */\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK        UINT32_C(0xe)\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT         1\n \t/*\n \t * This error occurs when there is a fatal HW problem in\n-\t * the chip only.  It indicates that there were not\n+\t * the chip only. It indicates that there were not\n \t * BDs on chip but that there was adequate reservation.\n \t * provided by the TPA block.\n \t */\n@@ -3414,7 +3432,7 @@ struct rx_tpa_end_cmpl_hi {\n \t/*\n \t * This error occurs when TPA block was not configured to\n \t * reserve adequate BDs for TPA operations on this RX\n-\t * ring.  All data for the TPA operation was not placed.\n+\t * ring. All data for the TPA operation was not placed.\n \t *\n \t * This error can also be generated when the number of\n \t * segments is not programmed correctly in TPA and the\n@@ -3444,8 +3462,8 @@ struct rx_tpa_v2_start_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_TPA_V2_START_CMPL_TYPE_MASK \\\n@@ -3472,9 +3490,9 @@ struct rx_tpa_v2_start_cmpl {\n \t#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT             7\n \t/*\n \t * Jumbo:\n-\t * TPA Packet was placed using jumbo algorithm.  This means\n+\t * TPA Packet was placed using jumbo algorithm. This means\n \t * that the first buffer will be filled with data before\n-\t * moving to aggregation buffers.  Each aggregation buffer\n+\t * moving to aggregation buffers. Each aggregation buffer\n \t * will be filled before moving to the next aggregation\n \t * buffer.\n \t */\n@@ -3551,19 +3569,19 @@ struct rx_tpa_v2_start_cmpl {\n \tuint32_t\topaque;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \tuint8_t\tv1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)\n \t#define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1\n \t/*\n-\t * This is the RSS hash type for the packet.  The value is packed\n+\t * This is the RSS hash type for the packet. The value is packed\n \t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n \t *\n \t * The value of tuple_extrac_op provides the information about\n@@ -3594,7 +3612,7 @@ struct rx_tpa_v2_start_cmpl {\n \tuint8_t\trss_hash_type;\n \t/*\n \t * This is the aggregation ID that the completion is associated\n-\t * with.  Use this number to correlate the TPA start completion\n+\t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n \tuint16_t\tagg_id;\n@@ -3646,7 +3664,7 @@ struct rx_tpa_v2_start_cmpl_hi {\n \t#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \\\n \t\tUINT32_C(0xf0)\n \t#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT            4\n-\t/* No metadata informtaion.  Value is zero. */\n+\t/* No metadata informtaion. Value is zero. */\n \t#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \\\n \t\t(UINT32_C(0x0) << 4)\n \t/*\n@@ -3695,7 +3713,7 @@ struct rx_tpa_v2_start_cmpl_hi {\n \t\tRX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET\n \t/*\n \t * This field indicates the IP type for the inner-most IP header.\n-\t * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.\n+\t * A value of '0' indicates IPv4. A value of '1' indicates IPv6.\n \t */\n \t#define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \\\n \t\tUINT32_C(0x100)\n@@ -3742,8 +3760,8 @@ struct rx_tpa_v2_start_cmpl_hi {\n \tuint16_t\terrors_v2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_V2_START_CMPL_V2 \\\n \t\tUINT32_C(0x1)\n@@ -3753,7 +3771,7 @@ struct rx_tpa_v2_start_cmpl_hi {\n \t/*\n \t * This error indicates that there was some sort of problem with\n \t * the BDs for the packet that was found after part of the\n-\t * packet was already placed.  The packet should be treated as\n+\t * packet was already placed. The packet should be treated as\n \t * invalid.\n \t */\n \t#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \\\n@@ -3794,7 +3812,7 @@ struct rx_tpa_v2_start_cmpl_hi {\n \tuint32_t\tinner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;\n \t/*\n \t * This is the offset from the beginning of the packet in bytes for\n-\t * the outer L3 header.  If there is no outer L3 header, then this\n+\t * the outer L3 header. If there is no outer L3 header, then this\n \t * value is zero.\n \t */\n \t#define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)\n@@ -3830,8 +3848,8 @@ struct rx_tpa_v2_end_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_TPA_V2_END_CMPL_TYPE_MASK                UINT32_C(0x3f)\n@@ -3848,7 +3866,7 @@ struct rx_tpa_v2_end_cmpl {\n \t#define RX_TPA_V2_END_CMPL_FLAGS_SFT                6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type.  Type of error is indicated in\n+\t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n \t#define RX_TPA_V2_END_CMPL_FLAGS_ERROR               UINT32_C(0x40)\n@@ -3857,9 +3875,9 @@ struct rx_tpa_v2_end_cmpl {\n \t#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT       7\n \t/*\n \t * Jumbo:\n-\t * TPA Packet was placed using jumbo algorithm.  This means\n+\t * TPA Packet was placed using jumbo algorithm. This means\n \t * that the first buffer will be filled with data before\n-\t * moving to aggregation buffers.  Each aggregation buffer\n+\t * moving to aggregation buffers. Each aggregation buffer\n \t * will be filled before moving to the next aggregation\n \t * buffer.\n \t */\n@@ -3902,7 +3920,7 @@ struct rx_tpa_v2_end_cmpl {\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n \t * - 2 TCP Packet\n-\t *     Indicates that the packet was IP and TCP.  This indicates\n+\t *     Indicates that the packet was IP and TCP. This indicates\n \t *     that the ip_cs field is valid and that the tcp_udp_cs\n \t *     field is valid and contains the TCP checksum.\n \t *     This also indicates that the payload_offset field is valid.\n@@ -3923,15 +3941,15 @@ struct rx_tpa_v2_end_cmpl {\n \tuint8_t\tv1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_V2_END_CMPL_V1     UINT32_C(0x1)\n \t/* This value is the number of segments in the TPA operation. */\n \tuint8_t\ttpa_segs;\n \t/*\n \t * This is the aggregation ID that the completion is associated\n-\t * with.  Use this number to correlate the TPA start completion\n+\t * with. Use this number to correlate the TPA start completion\n \t * with the TPA end completion.\n \t */\n \tuint16_t\tagg_id;\n@@ -3944,8 +3962,8 @@ struct rx_tpa_v2_end_cmpl {\n \t * For GRO packets, this field is zero except for the following\n \t * sub-fields.\n \t * - tsdelta[31]\n-\t *     Timestamp present indication.  When '0', no Timestamp\n-\t *     option is in the packet.  When '1', then a Timestamp\n+\t *     Timestamp present indication. When '0', no Timestamp\n+\t *     option is in the packet. When '1', then a Timestamp\n \t *     option is present in the packet.\n \t */\n \tuint32_t\ttsdelta;\n@@ -3986,13 +4004,13 @@ struct rx_tpa_v2_end_cmpl_hi {\n \t */\n \tuint8_t\ttpa_agg_bufs;\n \t/*\n-\t * This value is the valid when TPA completion is active.  It\n+\t * This value is the valid when TPA completion is active. It\n \t * indicates the length of the longest segment of the TPA operation\n \t * for LRO mode and the length of the first segment in GRO mode.\n \t *\n \t * This value may be used by GRO software to re-construct the original\n-\t * packet stream from the TPA packet.  This is the length of all\n-\t * but the last segment for GRO.  In LRO mode this value may be used\n+\t * packet stream from the TPA packet. This is the length of all\n+\t * but the last segment for GRO. In LRO mode this value may be used\n \t * to indicate MSS size to the stack.\n \t */\n \tuint16_t\ttpa_seg_len;\n@@ -4000,8 +4018,8 @@ struct rx_tpa_v2_end_cmpl_hi {\n \tuint16_t\terrors_v2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_V2_END_CMPL_V2                             UINT32_C(0x1)\n \t#define RX_TPA_V2_END_CMPL_ERRORS_MASK \\\n@@ -4010,7 +4028,7 @@ struct rx_tpa_v2_end_cmpl_hi {\n \t/*\n \t * This error indicates that there was some sort of problem with\n \t * the BDs for the packet that was found after part of the\n-\t * packet was already placed.  The packet should be treated as\n+\t * packet was already placed. The packet should be treated as\n \t * invalid.\n \t */\n \t#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \\\n@@ -4021,7 +4039,7 @@ struct rx_tpa_v2_end_cmpl_hi {\n \t\t(UINT32_C(0x0) << 1)\n \t/*\n \t * This error occurs when there is a fatal HW problem in\n-\t * the chip only.  It indicates that there were not\n+\t * the chip only. It indicates that there were not\n \t * BDs on chip but that there was adequate reservation.\n \t * provided by the TPA block.\n \t */\n@@ -4036,7 +4054,7 @@ struct rx_tpa_v2_end_cmpl_hi {\n \t/*\n \t * This error occurs when TPA block was not configured to\n \t * reserve adequate BDs for TPA operations on this RX\n-\t * ring.  All data for the TPA operation was not placed.\n+\t * ring. All data for the TPA operation was not placed.\n \t *\n \t * This error can also be generated when the number of\n \t * segments is not programmed correctly in TPA and the\n@@ -4071,8 +4089,8 @@ struct rx_tpa_v2_abuf_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_TPA_V2_ABUF_CMPL_TYPE_MASK      UINT32_C(0x3f)\n@@ -4080,17 +4098,17 @@ struct rx_tpa_v2_abuf_cmpl {\n \t/*\n \t * RX TPA Aggregation Buffer completion :\n \t * Completion of an L2 aggregation buffer in support of\n-\t * TPA packet completion.  Length = 16B\n+\t * TPA packet completion. Length = 16B\n \t */\n \t#define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG  UINT32_C(0x16)\n \t#define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \\\n \t\tRX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG\n \t/*\n \t * This is the length of the data for the packet stored in this\n-\t * aggregation buffer identified by the opaque value.  This does not\n+\t * aggregation buffer identified by the opaque value. This does not\n \t * include the length of any\n \t * data placed in other aggregation BDs or in the packet or buffer\n-\t * BDs.   This length does not include any space added due to\n+\t * BDs. This length does not include any space added due to\n \t * hdr_offset register during HDS placement mode.\n \t */\n \tuint16_t\tlen;\n@@ -4102,8 +4120,8 @@ struct rx_tpa_v2_abuf_cmpl {\n \tuint16_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_TPA_V2_ABUF_CMPL_V     UINT32_C(0x1)\n \t/*\n@@ -4121,8 +4139,8 @@ struct rx_abuf_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define RX_ABUF_CMPL_TYPE_MASK  UINT32_C(0x3f)\n@@ -4130,16 +4148,16 @@ struct rx_abuf_cmpl {\n \t/*\n \t * RX Aggregation Buffer completion :\n \t * Completion of an L2 aggregation buffer in support of\n-\t * TPA, HDS, or Jumbo packet completion.  Length = 16B\n+\t * TPA, HDS, or Jumbo packet completion. Length = 16B\n \t */\n \t#define RX_ABUF_CMPL_TYPE_RX_AGG  UINT32_C(0x12)\n \t#define RX_ABUF_CMPL_TYPE_LAST   RX_ABUF_CMPL_TYPE_RX_AGG\n \t/*\n \t * This is the length of the data for the packet stored in this\n-\t * aggregation buffer identified by the opaque value.  This does not\n+\t * aggregation buffer identified by the opaque value. This does not\n \t * include the length of any\n \t * data placed in other aggregation BDs or in the packet or buffer\n-\t * BDs.   This length does not include any space added due to\n+\t * BDs. This length does not include any space added due to\n \t * hdr_offset register during HDS placement mode.\n \t */\n \tuint16_t\tlen;\n@@ -4151,8 +4169,8 @@ struct rx_abuf_cmpl {\n \tuint32_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define RX_ABUF_CMPL_V     UINT32_C(0x1)\n \t/* unused3 is 32 b */\n@@ -4165,8 +4183,8 @@ struct eject_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define EJECT_CMPL_TYPE_MASK       UINT32_C(0x3f)\n@@ -4182,7 +4200,7 @@ struct eject_cmpl {\n \t#define EJECT_CMPL_FLAGS_SFT       6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n-\t * error of some type.  Type of error is indicated in\n+\t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n \t#define EJECT_CMPL_FLAGS_ERROR      UINT32_C(0x40)\n@@ -4199,8 +4217,8 @@ struct eject_cmpl {\n \tuint16_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define EJECT_CMPL_V                              UINT32_C(0x1)\n \t#define EJECT_CMPL_ERRORS_MASK                    UINT32_C(0xfffe)\n@@ -4247,8 +4265,8 @@ struct hwrm_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_CMPL_TYPE_MASK     UINT32_C(0x3f)\n@@ -4266,8 +4284,8 @@ struct hwrm_cmpl {\n \tuint32_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_CMPL_V     UINT32_C(0x1)\n \t/* unused4 is 32 b */\n@@ -4279,16 +4297,16 @@ struct hwrm_fwd_req_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \tuint16_t\treq_len_type;\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_FWD_REQ_CMPL_TYPE_MASK        UINT32_C(0x3f)\n@@ -4314,8 +4332,8 @@ struct hwrm_fwd_req_cmpl {\n \tuint32_t\treq_buf_addr_v[2];\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_FWD_REQ_CMPL_V                UINT32_C(0x1)\n \t/* Address of forwarded request. */\n@@ -4329,8 +4347,8 @@ struct hwrm_fwd_resp_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_FWD_RESP_CMPL_TYPE_MASK         UINT32_C(0x3f)\n@@ -4355,8 +4373,8 @@ struct hwrm_fwd_resp_cmpl {\n \tuint32_t\tresp_buf_addr_v[2];\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_FWD_RESP_CMPL_V                 UINT32_C(0x1)\n \t/* Address of forwarded request. */\n@@ -4370,8 +4388,8 @@ struct hwrm_async_event_cmpl {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK            UINT32_C(0x3f)\n@@ -4497,6 +4515,12 @@ struct hwrm_async_event_cmpl {\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \\\n \t\tUINT32_C(0x3e)\n \t/*\n+\t * An event signifying completion for HWRM_FW_STATE_QUIESCE\n+\t * (completion, timeout, or error)\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \\\n+\t\tUINT32_C(0x3f)\n+\t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n \t * event, not meant for production use at this time.\n@@ -4513,8 +4537,8 @@ struct hwrm_async_event_cmpl {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -4534,8 +4558,8 @@ struct hwrm_async_event_cmpl_link_status_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \\\n@@ -4558,8 +4582,8 @@ struct hwrm_async_event_cmpl_link_status_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -4613,8 +4637,8 @@ struct hwrm_async_event_cmpl_link_mtu_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \\\n@@ -4637,8 +4661,8 @@ struct hwrm_async_event_cmpl_link_mtu_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -4663,8 +4687,8 @@ struct hwrm_async_event_cmpl_link_speed_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \\\n@@ -4687,8 +4711,8 @@ struct hwrm_async_event_cmpl_link_speed_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -4758,8 +4782,8 @@ struct hwrm_async_event_cmpl_dcb_config_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \\\n@@ -4791,8 +4815,8 @@ struct hwrm_async_event_cmpl_dcb_config_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -4839,8 +4863,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \\\n@@ -4864,8 +4888,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \\\n \t\tUINT32_C(0x1)\n@@ -4915,8 +4939,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \\\n@@ -4940,8 +4964,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \\\n \t\tUINT32_C(0x1)\n@@ -4968,8 +4992,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \\\n@@ -4993,8 +5017,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -5037,8 +5061,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \\\n@@ -5062,8 +5086,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -5113,8 +5137,8 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \\\n@@ -5137,8 +5161,8 @@ struct hwrm_async_event_cmpl_reset_notify {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5213,8 +5237,8 @@ struct hwrm_async_event_cmpl_error_recovery {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \\\n@@ -5242,8 +5266,8 @@ struct hwrm_async_event_cmpl_error_recovery {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5282,8 +5306,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \\\n@@ -5306,8 +5330,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5333,8 +5357,8 @@ struct hwrm_async_event_cmpl_func_drvr_load {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \\\n@@ -5357,8 +5381,8 @@ struct hwrm_async_event_cmpl_func_drvr_load {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5382,8 +5406,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \\\n@@ -5407,8 +5431,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \\\n \t\tUINT32_C(0x1)\n@@ -5435,8 +5459,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \\\n@@ -5459,8 +5483,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5488,8 +5512,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \\\n@@ -5512,8 +5536,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5541,8 +5565,8 @@ struct hwrm_async_event_cmpl_vf_flr {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \\\n@@ -5564,8 +5588,8 @@ struct hwrm_async_event_cmpl_vf_flr {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5593,8 +5617,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \\\n@@ -5617,8 +5641,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -5645,8 +5669,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \\\n@@ -5670,8 +5694,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -5701,8 +5725,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \\\n@@ -5725,8 +5749,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5786,8 +5810,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \\\n@@ -5814,8 +5838,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -5865,8 +5889,8 @@ struct hwrm_async_event_cmpl_default_vnic_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \\\n@@ -5885,7 +5909,7 @@ struct hwrm_async_event_cmpl_default_vnic_change {\n \t\t6\n \t/* Identifiers of events. */\n \tuint16_t\tevent_id;\n-\t/* Notification of a default vnic allocaiton or free */\n+\t/* Notification of a default vnic allocation or free */\n \t#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \\\n \t\tUINT32_C(0x35)\n \t#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \\\n@@ -5895,8 +5919,8 @@ struct hwrm_async_event_cmpl_default_vnic_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -5947,8 +5971,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \\\n@@ -5971,8 +5995,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -6014,8 +6038,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \\\n@@ -6039,8 +6063,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \\\n \t\tUINT32_C(0x1)\n@@ -6062,8 +6086,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \\\n@@ -6090,8 +6114,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \\\n \t\tUINT32_C(0x1)\n@@ -6118,8 +6142,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \\\n@@ -6143,8 +6167,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \\\n \t\tUINT32_C(0x1)\n@@ -6166,8 +6190,8 @@ struct hwrm_async_event_cmpl_eem_flow_active {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \\\n@@ -6209,8 +6233,8 @@ struct hwrm_async_event_cmpl_eem_flow_active {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -6266,8 +6290,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \\\n@@ -6290,8 +6314,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -6317,14 +6341,87 @@ struct hwrm_async_event_cmpl_eem_cfg_change {\n \t\tUINT32_C(0x2)\n } __attribute__((packed));\n \n+/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */\n+struct hwrm_async_event_cmpl_quiesce_done {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT             0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* An event signifying completion of HWRM_FW_STATE_QUIESCE */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\t/* Status of HWRM_FW_STATE_QUIESCE completion */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \\\n+\t\t0\n+\t/*\n+\t * The quiesce operation started by HWRM_FW_STATE_QUIESCE\n+\t * completed successfully.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed\n+\t * out.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * The quiesce operation started by HWRM_FW_STATE_QUIESCE\n+\t * encountered an error.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V          UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Time stamp for error event */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \\\n+\t\tUINT32_C(0x1)\n+} __attribute__((packed));\n+\n /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */\n struct hwrm_async_event_cmpl_fw_trace_msg {\n \tuint16_t\ttype;\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \\\n@@ -6363,8 +6460,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -6430,8 +6527,8 @@ struct hwrm_async_event_cmpl_hwrm_error {\n \t/*\n \t * This field indicates the exact type of the completion.\n \t * By convention, the LSB identifies the length of the\n-\t * record in 16B units.  Even values indicate 16B\n-\t * records.  Odd values indicate 32B\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n \t * records.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \\\n@@ -6469,8 +6566,8 @@ struct hwrm_async_event_cmpl_hwrm_error {\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue.   The even passes\n-\t * will write 1.  The odd passes will write 0.\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V          UINT32_C(0x1)\n \t/* opaque is 7 b */\n@@ -7336,6 +7433,15 @@ struct hwrm_func_qcaps_output {\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \\\n \t\tUINT32_C(0x2000000)\n \t/*\n+\t * If the query is for a VF, then this flag (always set to 0) shall\n+\t * be ignored. If this query is for a PF and this flag is set to 1,\n+\t * host, when registered for the default vnic change async event,\n+\t * receives async notification whenever a default vnic state is\n+\t * changed for any of child or adopted VFs.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \\\n+\t\tUINT32_C(0x4000000)\n+\t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n \t * MAC address is currently configured.\n@@ -7905,7 +8011,12 @@ struct hwrm_func_qcfg_output {\n \t * after receiving the RESET Notify event.\n \t */\n \tuint32_t\treset_addr_poll;\n-\tuint8_t\tunused_2[3];\n+\t/*\n+\t * This field specifies legacy L2 doorbell size in KBytes. Drivers should use\n+\t * this value to find out the doorbell page offset from the BAR.\n+\t */\n+\tuint16_t\tlegacy_l2_db_size_kb;\n+\tuint8_t\tunused_2[1];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -8606,9 +8717,22 @@ struct hwrm_func_qstats_input {\n \t * Function ID of the function that is being queried.\n \t * 0xFF... (All Fs) if the query is for the requesting\n \t * function.\n+\t * A privileged PF can query for other function's statistics.\n \t */\n \tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n+\t/* This flags indicates the type of statistics request. */\n+\tuint8_t\tflags;\n+\t/* This value is not used to avoid backward compatibility issues. */\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED    UINT32_C(0x0)\n+\t/*\n+\t * flags should be set to 1 when request is for only RoCE statistics.\n+\t * This will be honored only if the caller_fid is a privileged PF.\n+\t * In all other cases FID and caller_fid should be the same.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \\\n+\t\tHWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY\n+\tuint8_t\tunused_0[5];\n } __attribute__((packed));\n \n /* hwrm_func_qstats_output (size:1408b/176B) */\n@@ -8928,12 +9052,11 @@ struct hwrm_func_drv_rgtr_input {\n \t\tUINT32_C(0x20)\n \t/*\n \t * When this bit is 1, the function is indicating the support of the\n-\t * Master capability. The Firmware will use this capability to select\n-\t * the Master function. The master function will be used to initiate\n-\t * designated functionality like error recovery etc. If none of the\n-\t * registered PFs or trusted VFs indicate this support, then\n-\t * firmware will select the 1st registered PF as Master capable\n-\t * instance.\n+\t * Master capability. The Firmware will use this capability to select the\n+\t * Master function. The master function will be used to initiate\n+\t * designated functionality like error recovery etc… If none of the\n+\t * registered PF’s or trusted VF’s indicate this support, then\n+\t * firmware will select the 1st registered PF as Master capable instance.\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \\\n \t\tUINT32_C(0x40)\n@@ -9621,7 +9744,7 @@ struct hwrm_func_backing_store_qcaps_input {\n \tuint64_t\tresp_addr;\n } __attribute__((packed));\n \n-/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */\n+/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */\n struct hwrm_func_backing_store_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -9729,6 +9852,19 @@ struct hwrm_func_backing_store_qcaps_output {\n \t */\n \tuint8_t\ttqm_entries_multiple;\n \t/*\n+\t * Initializer to be used by drivers\n+\t * to initialize context memory to ensure\n+\t * context subsystem flags an error for an attack\n+\t * before the first time context load.\n+\t */\n+\tuint8_t\tctx_kind_initializer;\n+\t/* Reserved for future. */\n+\tuint32_t\trsvd;\n+\t/* Reserved for future. */\n+\tuint16_t\trsvd1;\n+\t/* Reserved for future. */\n+\tuint8_t\trsvd2;\n+\t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n \t * to indicate that the output has been completely written.\n@@ -13369,7 +13505,7 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE   UINT32_C(0x2)\n \t/*\n \t * The HW will be configured with external loopback such that\n-\t * host data is sent on the trasmitter and based on the external\n+\t * host data is sent on the transmitter and based on the external\n \t * loopback connection the data will be received without modification.\n \t */\n \t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)\n@@ -13431,7 +13567,7 @@ struct hwrm_port_phy_cfg_input {\n \t\tUINT32_C(0x40)\n \tuint8_t\tunused_2[2];\n \t/*\n-\t * Reuested setting of TX LPI timer in microseconds.\n+\t * Requested setting of TX LPI timer in microseconds.\n \t * This field is valid only when EEE is enabled and TX LPI is\n \t * enabled.\n \t */\n@@ -13861,7 +13997,7 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE   UINT32_C(0x2)\n \t/*\n \t * The HW will be configured with external loopback such that\n-\t * host data is sent on the trasmitter and based on the external\n+\t * host data is sent on the transmitter and based on the external\n \t * loopback connection the data will be received without modification.\n \t */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)\n@@ -14500,7 +14636,7 @@ struct hwrm_port_mac_cfg_input {\n \t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * When this bit is '1', the the Out-Of-Box WoL is requested to\n+\t * When this bit is '1', the Out-Of-Box WoL is requested to\n \t * be disabled on this port.\n \t */\n \t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \\\n@@ -14670,7 +14806,7 @@ struct hwrm_port_mac_cfg_input {\n \t * This field shall be ignored if the ptp_tx_ts_capture_enable\n \t * flag is not set in this command.\n \t * Otherwise, if bit 'i' is set, then the HWRM is being\n-\t * requested to configure the transmit sied of the port to\n+\t * requested to configure the transmit side of the port to\n \t * capture the time stamp of every transmitted PTP message\n \t * with messageType field value set to i.\n \t */\n@@ -16169,12 +16305,27 @@ struct hwrm_port_phy_qcaps_output {\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \\\n \t\tUINT32_C(0x2)\n \t/*\n+\t * If set to 1, then this field indicates that the\n+\t * PHY is capable of supporting loopback in autoneg mode.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Indicates if the configuration of shared PHY settings is supported.\n+\t * In cases where a physical port is shared by multiple functions\n+\t * (e.g. NPAR, multihost, etc), the configuration of PHY\n+\t * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will\n+\t * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n \t * Reserved field. The HWRM shall set this field to 0.\n \t * An HWRM client shall ignore this field.\n \t */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n-\t\tUINT32_C(0xfc)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT                   2\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT                    4\n \t/* Number of front panel ports for this device. */\n \tuint8_t\tport_cnt;\n \t/* Not supported or unknown */\n@@ -17726,6 +17877,553 @@ struct hwrm_port_prbs_test_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/**********************\n+ * hwrm_port_dsc_dump *\n+ **********************/\n+\n+\n+/* hwrm_port_dsc_dump_input (size:320b/40B) */\n+struct hwrm_port_dsc_dump_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Host address where response diagnostic data is returned. */\n+\tuint64_t\tresp_data_addr;\n+\t/*\n+\t * Size of the buffer pointed to by resp_data_addr. The firmware\n+\t * may use this entire buffer or less than the entire buffer, but\n+\t * never more.\n+\t */\n+\tuint16_t\tdata_len;\n+\tuint16_t\tunused_0;\n+\tuint32_t\tunused_1;\n+\t/* Port ID of port where dsc dump to be collected. */\n+\tuint16_t\tport_id;\n+\t/* Diag level specified by the user */\n+\tuint16_t\tdiag_level;\n+\t/* SRDS_DIAG_LANE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \\\n+\t\tUINT32_C(0x0)\n+\t/* SRDS_DIAG_CORE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \\\n+\t\tUINT32_C(0x1)\n+\t/* SRDS_DIAG_EVENT */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \\\n+\t\tUINT32_C(0x2)\n+\t/* SRDS_DIAG_EYE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \\\n+\t\tUINT32_C(0x3)\n+\t/* SRDS_DIAG_REG_CORE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \\\n+\t\tUINT32_C(0x4)\n+\t/* SRDS_DIAG_REG_LANE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \\\n+\t\tUINT32_C(0x5)\n+\t/* SRDS_DIAG_UC_CORE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \\\n+\t\tUINT32_C(0x6)\n+\t/* SRDS_DIAG_UC_LANE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \\\n+\t\tUINT32_C(0x7)\n+\t/* SRDS_DIAG_LANE_DEBUG */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \\\n+\t\tUINT32_C(0x8)\n+\t/* SRDS_DIAG_BER_VERT */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \\\n+\t\tUINT32_C(0x9)\n+\t/* SRDS_DIAG_BER_HORZ */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \\\n+\t\tUINT32_C(0xa)\n+\t/* SRDS_DIAG_EVENT_SAFE */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \\\n+\t\tUINT32_C(0xb)\n+\t/* SRDS_DIAG_TIMESTAMP */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \\\n+\t\tHWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP\n+\t/*\n+\t * This field is a lane number\n+\t * on which to collect the dsc dump\n+\t */\n+\tuint16_t\tlane_number;\n+\t/*\n+\t * Configuration bits.\n+\t * Use enable bit to start dsc dump or retrieve dump\n+\t */\n+\tuint16_t\tdsc_dump_config;\n+\t/*\n+\t * Set 0 to retrieve the dsc dump\n+\t * Set 1 to start the dsc dump\n+\t */\n+\t#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \\\n+\t\tUINT32_C(0x1)\n+} __attribute__((packed));\n+\n+/* hwrm_port_dsc_dump_output (size:128b/16B) */\n+struct hwrm_port_dsc_dump_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Total length of stored data. */\n+\tuint16_t\ttotal_data_len;\n+\tuint16_t\tunused_0;\n+\tuint8_t\tunused_1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_port_sfp_sideband_cfg *\n+ ******************************/\n+\n+\n+/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */\n+struct hwrm_port_sfp_sideband_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is to be queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+\t/*\n+\t * This bitfield is used to specify which bits from the 'flags'\n+\t * fields are being configured by the caller.\n+\t */\n+\tuint32_t\tenables;\n+\t/* This bit must be '1' for rs0 to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \\\n+\t\tUINT32_C(0x1)\n+\t/* This bit must be '1' for rs1 to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \\\n+\t\tUINT32_C(0x2)\n+\t/* This bit must be '1' for tx_disable to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for mod_sel to be configured.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \\\n+\t\tUINT32_C(0x8)\n+\t/* This bit must be '1' for reset_l to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \\\n+\t\tUINT32_C(0x10)\n+\t/* This bit must be '1' for lp_mode to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \\\n+\t\tUINT32_C(0x20)\n+\t/* This bit must be '1' for pwr_disable to be configured. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * Only bits that have corresponding bits in the 'enables'\n+\t * bitfield are processed by the firmware, all other bits\n+\t * of 'flags' are ignored.\n+\t */\n+\tuint32_t\tflags;\n+\t/*\n+\t * This bit along with rs1 configures the current speed of the dual\n+\t * rate module. If these pins are GNDed then the speed can be changed\n+\t * by driectly writing to EEPROM.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit along with rs0 configures the current speed of the dual\n+\t * rate module. If these pins are GNDed then the speed can be changed\n+\t * by driectly writing to EEPROM.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is set to '1', tx_disable is set.\n+\t * On a 1G BASE-T module, if this bit is set,\n+\t * module PHY registers will not be accessible.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is set to '1', this module is selected.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If reset_l is set to 0, Module will be taken out of reset\n+\t * and other signals will be set to their requested state once\n+\t * the module is out of reset.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is set to '1', the module will be configured\n+\t * in low power mode.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \\\n+\t\tUINT32_C(0x20)\n+\t/* When this bit is set to '1', the module will be powered down. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \\\n+\t\tUINT32_C(0x40)\n+} __attribute__((packed));\n+\n+/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */\n+struct hwrm_port_sfp_sideband_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written. When\n+\t * writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_port_sfp_sideband_qcfg *\n+ *******************************/\n+\n+\n+/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */\n+struct hwrm_port_sfp_sideband_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is to be queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */\n+struct hwrm_port_sfp_sideband_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Bitmask indicating which sideband signals are valid.\n+\t * This is based on the board and nvm cfg that is present on the board.\n+\t */\n+\tuint32_t\tsupported_mask;\n+\tuint32_t\tsideband_signals;\n+\t/* When this bit is set to '1', the Module is absent. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', there is no valid signal on RX.\n+\t * This signal is a filtered version of Signal Detect.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit along with rs1 indiactes the current speed of the dual\n+\t * rate module.If these pins are grounded then the speed can be\n+\t * changed by driectky writing to EEPROM.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit along with rs0 indiactes the current speed of the dual\n+\t * rate module.If these pins are grounded then the speed can be\n+\t * changed by driectky writing to EEPROM.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is set to '1', tx_disable is set.\n+\t * On a 1G BASE-T module, if this bit is set, module PHY\n+\t * registers will not be accessible.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \\\n+\t\tUINT32_C(0x10)\n+\t/* When this bit is set to '1', tx_fault is set. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is set to '1', module is selected.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is set to '0', the module is held in reset.\n+\t * if reset_l is set to 1,first module is taken out of reset\n+\t * and other signals will be set to their requested state.\n+\t * Valid only on QSFP modules.\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is set to '1', the module is in low power mode.\n+\t * Valid only on QSFP modules\n+\t */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \\\n+\t\tUINT32_C(0x100)\n+\t/* When this bit is set to '1', module is in power down state. */\n+\t#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \\\n+\t\tUINT32_C(0x200)\n+\tuint8_t\tunused[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written. When\n+\t * writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************************\n+ * hwrm_port_phy_mdio_bus_acquire *\n+ **********************************/\n+\n+\n+/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */\n+struct hwrm_port_phy_mdio_bus_acquire_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of the port. */\n+\tuint16_t\tport_id;\n+\t/*\n+\t * client_id of the client requesting BUS access.\n+\t * Any value from 0x10 to 0xFFFF can be used.\n+\t * Client should make sure that the returned client_id\n+\t * in response matches the client_id in request.\n+\t * 0-0xF are reserved for internal use.\n+\t */\n+\tuint16_t\tclient_id;\n+\t/*\n+\t * Timeout in milli seconds, MDIO BUS will be released automatically\n+\t * after this time, if another mdio acquire command is not received\n+\t * within the timeout window from the same client.\n+\t * A 0xFFFF will hold the bus untill this bus is released.\n+\t */\n+\tuint16_t\tmdio_bus_timeout;\n+\tuint8_t\tunused_0[2];\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */\n+struct hwrm_port_phy_mdio_bus_acquire_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint16_t\tunused_0;\n+\t/*\n+\t * client_id of the module holding the BUS.\n+\t * 0-0xF are reserved for internal use.\n+\t */\n+\tuint16_t\tclient_id;\n+\tuint8_t\tunused_1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************************\n+ * hwrm_port_phy_mdio_bus_release *\n+ **********************************/\n+\n+\n+/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */\n+struct hwrm_port_phy_mdio_bus_release_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of the port. */\n+\tuint16_t\tport_id;\n+\t/*\n+\t * client_id of the client requesting BUS release.\n+\t * A client should not release any other clients BUS.\n+\t */\n+\tuint16_t\tclient_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */\n+struct hwrm_port_phy_mdio_bus_release_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint16_t\tunused_0;\n+\t/* The BUS is released if client_id matches the client_id in request. */\n+\tuint16_t\tclients_id;\n+\tuint8_t\tunused_1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /***********************\n  * hwrm_queue_qportcfg *\n  ***********************/\n@@ -17776,7 +18474,7 @@ struct hwrm_queue_qportcfg_input {\n \t\tHWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX\n \t/*\n \t * Port ID of port for which the queue configuration is being\n-\t * queried.  This field is only required when sent by IPC.\n+\t * queried. This field is only required when sent by IPC.\n \t */\n \tuint16_t\tport_id;\n \t/*\n@@ -18171,7 +18869,7 @@ struct hwrm_queue_qportcfg_output {\n \t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18242,7 +18940,7 @@ struct hwrm_queue_qcfg_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * This value is a the estimate packet length used in the\n+\t * This value is the estimate packet length used in the\n \t * TX arbiter.\n \t */\n \tuint32_t\tqueue_len;\n@@ -18269,7 +18967,7 @@ struct hwrm_queue_qcfg_output {\n \tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18373,7 +19071,7 @@ struct hwrm_queue_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18463,7 +19161,7 @@ struct hwrm_queue_pfcenable_qcfg_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18513,22 +19211,22 @@ struct hwrm_queue_pfcenable_cfg_input {\n \t/* If set to 1, then PFC is requested to be enabled on PRI 1. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \\\n \t\tUINT32_C(0x2)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 2. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 2. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \\\n \t\tUINT32_C(0x4)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 3. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 3. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \\\n \t\tUINT32_C(0x8)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 4. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 4. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \\\n \t\tUINT32_C(0x10)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 5. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 5. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \\\n \t\tUINT32_C(0x20)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 6. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 6. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \\\n \t\tUINT32_C(0x40)\n-\t/* If set to 1, then PFC is requested to  be enabled on PRI 7. */\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 7. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \\\n \t\tUINT32_C(0x80)\n \t/*\n@@ -18553,7 +19251,7 @@ struct hwrm_queue_pfcenable_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18611,9 +19309,9 @@ struct hwrm_queue_pri2cos_qcfg_input {\n \t\tHWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX\n \t/*\n \t * When this bit is set to '0', the query is\n-\t * for VLAN PRI field in tunnel headers.\n+\t * for PRI from tunnel headers.\n \t * When this bit is set to '1', the query is\n-\t * for VLAN PRI field in inner packet headers.\n+\t * for PRI from inner packet headers.\n \t */\n \t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN     UINT32_C(0x2)\n \t/*\n@@ -18636,56 +19334,56 @@ struct hwrm_queue_pri2cos_qcfg_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * CoS Queue assigned to priority 0.  This value can only\n+\t * CoS Queue assigned to priority 0. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri0_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 1.  This value can only\n+\t * CoS Queue assigned to priority 1. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri1_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 2  This value can only\n+\t * CoS Queue assigned to priority 2. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri2_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 3.  This value can only\n+\t * CoS Queue assigned to priority 3. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri3_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 4.  This value can only\n+\t * CoS Queue assigned to priority 4. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri4_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 5.  This value can only\n+\t * CoS Queue assigned to priority 5. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri5_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 6.  This value can only\n+\t * CoS Queue assigned to priority 6. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n \t */\n \tuint8_t\tpri6_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 7.  This value can only\n+\t * CoS Queue assigned to priority 7. This value can only\n \t * be changed before traffic has started.\n \t * A value of 0xff indicates that no CoS queue is assigned to the\n \t * specified priority.\n@@ -18704,7 +19402,7 @@ struct hwrm_queue_pri2cos_qcfg_output {\n \tuint8_t\tunused_0[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -18765,9 +19463,9 @@ struct hwrm_queue_pri2cos_cfg_input {\n \t\tHWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR\n \t/*\n \t * When this bit is set to '0', the mapping is requested\n-\t * for VLAN PRI field in tunnel headers.\n+\t * for PRI from tunnel headers.\n \t * When this bit is set to '1', the mapping is requested\n-\t * for VLAN PRI field in inner packet headers.\n+\t * for PRI from inner packet headers.\n \t */\n \t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN     UINT32_C(0x4)\n \tuint32_t\tenables;\n@@ -18826,12 +19524,12 @@ struct hwrm_queue_pri2cos_cfg_input {\n \t */\n \tuint8_t\tport_id;\n \t/*\n-\t * CoS Queue assigned to priority 0.  This value can only\n+\t * CoS Queue assigned to priority 0. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri0_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 1.  This value can only\n+\t * CoS Queue assigned to priority 1. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri1_cos_queue_id;\n@@ -18841,27 +19539,27 @@ struct hwrm_queue_pri2cos_cfg_input {\n \t */\n \tuint8_t\tpri2_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 3.  This value can only\n+\t * CoS Queue assigned to priority 3. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri3_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 4.  This value can only\n+\t * CoS Queue assigned to priority 4. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri4_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 5.  This value can only\n+\t * CoS Queue assigned to priority 5. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri5_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 6.  This value can only\n+\t * CoS Queue assigned to priority 6. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri6_cos_queue_id;\n \t/*\n-\t * CoS Queue assigned to priority 7.  This value can only\n+\t * CoS Queue assigned to priority 7. This value can only\n \t * be changed before traffic has started.\n \t */\n \tuint8_t\tpri7_cos_queue_id;\n@@ -18881,7 +19579,7 @@ struct hwrm_queue_pri2cos_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -19924,7 +20622,7 @@ struct hwrm_queue_cos2bw_qcfg_output {\n \tuint8_t\tunused_2[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -21016,7 +21714,609 @@ struct hwrm_queue_cos2bw_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_queue_dscp_qcaps *\n+ *************************/\n+\n+\n+/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */\n+struct hwrm_queue_dscp_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[7];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */\n+struct hwrm_queue_dscp_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The number of bits provided by the hardware for the DSCP value. */\n+\tuint8_t\tnum_dscp_bits;\n+\tuint8_t\tunused_0;\n+\t/* Max number of DSCP-MASK-PRI entries supported. */\n+\tuint16_t\tmax_entries;\n+\tuint8_t\tunused_1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/****************************\n+ * hwrm_queue_dscp2pri_qcfg *\n+ ****************************/\n+\n+\n+/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */\n+struct hwrm_queue_dscp2pri_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * This is the host address where the 24-bits DSCP-MASK-PRI\n+\t * tuple(s) will be copied to.\n+\t */\n+\tuint64_t\tdest_data_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0;\n+\t/* Size of the buffer pointed to by dest_data_addr. */\n+\tuint16_t\tdest_data_buffer_size;\n+\tuint8_t\tunused_1[4];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */\n+struct hwrm_queue_dscp2pri_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * A count of the number of DSCP-MASK-PRI tuple(s) pointed to\n+\t * by the dest_data_addr.\n+\t */\n+\tuint16_t\tentry_cnt;\n+\t/*\n+\t * This is the default PRI which un-initialized DSCP values are\n+\t * mapped to.\n+\t */\n+\tuint8_t\tdefault_pri;\n+\tuint8_t\tunused_0[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_queue_dscp2pri_cfg *\n+ ***************************/\n+\n+\n+/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */\n+struct hwrm_queue_dscp2pri_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * This is the host address where the 24-bits DSCP-MASK-PRI tuple\n+\t * will be copied from.\n+\t */\n+\tuint64_t\tsrc_data_addr;\n+\tuint32_t\tflags;\n+\t/* use_hw_default_pri is 1 b */\n+\t#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \\\n+\t\tUINT32_C(0x1)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the default_pri field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\t/*\n+\t * This is the default PRI which un-initialized DSCP values will be\n+\t * mapped to.\n+\t */\n+\tuint8_t\tdefault_pri;\n+\t/*\n+\t * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed\n+\t * to by src_data_addr.\n+\t */\n+\tuint16_t\tentry_cnt;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */\n+struct hwrm_queue_dscp2pri_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_queue_mpls_qcaps *\n+ *************************/\n+\n+\n+/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */\n+struct hwrm_queue_mpls_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure MPLS TC(EXP) to pri mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[7];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */\n+struct hwrm_queue_mpls_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Bitmask indicating which queues can be configured by the\n+\t * hwrm_queue_mplstc2pri_cfg command.\n+\t *\n+\t * Each bit represents a specific pri where bit 0 represents\n+\t * pri 0 and bit 7 represents pri 7.\n+\t * # A value of 0 indicates that the pri is not configurable\n+\t * by the hwrm_queue_mplstc2pri_cfg command.\n+\t * # A value of 1 indicates that the pri is configurable.\n+\t * # A hwrm_queue_mplstc2pri_cfg command shall return error when\n+\t * trying to configure a pri that is not configurable.\n+\t */\n+\tuint8_t\tqueue_mplstc2pri_cfg_allowed;\n+\t/*\n+\t * This is the default PRI which un-initialized MPLS values will be\n+\t * mapped to.\n+\t */\n+\tuint8_t\thw_default_pri;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_queue_mplstc2pri_qcfg *\n+ ******************************/\n+\n+\n+/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_mplstc2pri_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure MPLS TC(EXP) to pri mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[7];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */\n+struct hwrm_queue_mplstc2pri_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 0. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 0.\n+\t */\n+\tuint8_t\ttc0_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 1. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 1.\n+\t */\n+\tuint8_t\ttc1_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 2. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 2.\n+\t */\n+\tuint8_t\ttc2_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 3. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 3.\n+\t */\n+\tuint8_t\ttc3_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 4. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 4.\n+\t */\n+\tuint8_t\ttc4_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 5. This value can only be changed\n+\t * before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 5.\n+\t */\n+\tuint8_t\ttc5_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 6. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 6.\n+\t */\n+\tuint8_t\ttc6_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 7. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no pri is assigned to the\n+\t * MPLS TC(EXP) 7.\n+\t */\n+\tuint8_t\ttc7_pri_queue_id;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*****************************\n+ * hwrm_queue_mplstc2pri_cfg *\n+ *****************************/\n+\n+\n+/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */\n+struct hwrm_queue_mplstc2pri_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the mplstc0_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the mplstc1_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the mplstc2_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the mplstc3_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the mplstc4_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the mplstc5_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the mplstc6_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the mplstc7_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure MPLS TC(EXP)to pri mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 0. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc0_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 1. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc1_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 2  This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc2_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 3. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc3_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 4. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc4_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 5. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc5_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 6. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc6_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 7. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc7_pri_queue_id;\n+} __attribute__((packed));\n+\n+/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */\n+struct hwrm_queue_mplstc2pri_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -21529,7 +22829,13 @@ struct hwrm_vnic_qcfg_output {\n \t */\n \t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n \t\tUINT32_C(0x40)\n-\tuint8_t\tunused_1[7];\n+\t/*\n+\t * When returned with a valid CoS Queue id, the CoS Queue/VNIC association\n+\t * is valid.  Otherwise it will return 0xFFFF to indicate no VNIC/CoS\n+\t * queue association.\n+\t */\n+\tuint16_t\tqueue_id;\n+\tuint8_t\tunused_1[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -22040,6 +23346,27 @@ struct hwrm_vnic_rss_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */\n+struct hwrm_vnic_rss_cfg_cmd_err {\n+\t/*\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n+\t */\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * Unable to change global RSS mode to outer due to all active\n+\t * interfaces are not ready to support outer RSS hashing.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY\n+\tuint8_t\tunused_0[7];\n+} __attribute__((packed));\n+\n /**********************\n  * hwrm_vnic_rss_qcfg *\n  **********************/\n@@ -22308,7 +23635,7 @@ struct hwrm_vnic_plcmodes_cfg_input {\n \t/*\n \t * This value is used to determine the offset into\n \t * packet buffer where the split data (payload) will be\n-\t * placed according to one of of HDS placement algorithm.\n+\t * placed according to one of HDS placement algorithm.\n \t *\n \t * The lengths of packet buffers provided for split data\n \t * shall be larger than this value.\n@@ -22450,7 +23777,7 @@ struct hwrm_vnic_plcmodes_qcfg_output {\n \t/*\n \t * This value is used to determine the offset into\n \t * packet buffer where the split data (payload) will be\n-\t * placed according to one of of HDS placement algorithm.\n+\t * placed according to one of HDS placement algorithm.\n \t *\n \t * The lengths of packet buffers provided for split data\n \t * shall be larger than this value.\n@@ -23768,7 +25095,7 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t\tUINT32_C(0x40)\n \t/*\n \t * Setting this flag to 1 indicate the L2 fields in this command\n-\t * pertain to source fields.  Setting this flag to 0 indicate the\n+\t * pertain to source fields. Setting this flag to 0 indicate the\n \t * L2 fields in this command pertain to the destination fields\n \t * and this is the default/legacy behavior.\n \t */\n@@ -24010,7 +25337,7 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -24142,7 +25469,7 @@ struct hwrm_cfa_l2_filter_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24205,7 +25532,7 @@ struct hwrm_cfa_l2_filter_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24333,7 +25660,7 @@ struct hwrm_cfa_l2_filter_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24515,7 +25842,7 @@ struct hwrm_cfa_l2_set_rx_mask_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24608,7 +25935,7 @@ struct hwrm_cfa_vlan_antispoof_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24688,7 +26015,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -24863,7 +26190,7 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -24998,7 +26325,7 @@ struct hwrm_cfa_tunnel_filter_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25058,7 +26385,7 @@ struct hwrm_cfa_tunnel_filter_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25123,7 +26450,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -25170,7 +26497,7 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25235,7 +26562,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -25277,7 +26604,7 @@ struct hwrm_cfa_redirect_tunnel_type_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25342,7 +26669,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -25386,7 +26713,7 @@ struct hwrm_cfa_redirect_tunnel_type_info_output {\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25564,7 +26891,7 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* VLAN */\n@@ -25607,7 +26934,7 @@ struct hwrm_cfa_encap_record_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25668,7 +26995,7 @@ struct hwrm_cfa_encap_record_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -25681,7 +27008,7 @@ struct hwrm_cfa_encap_record_free_output {\n  ********************************/\n \n \n-/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */\n+/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */\n struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -25729,11 +27056,25 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * Setting of this flag indicates that the dest_id field contains function ID.\n+\t * Setting of this flag indicates that the dst_id field contains function ID.\n \t * If this is not set it indicates dest_id is VNIC or VPORT.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * Setting of this flag indicates match on arp reply when ethertype is 0x0806.\n+\t * If this is not set it indicates no specific arp opcode matching.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * Setting of this flag indicates that the dst_id field contains RFS ring\n+\t * table index. If this is not set it indicates dst_id is VNIC or VPORT\n+\t * or function ID.  Note dest_fid and dest_rfs_ring_idx can’t be set at\n+\t * the same time.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \\\n+\t\tUINT32_C(0x20)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the l2_filter_id field to be\n@@ -25849,10 +27190,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n \t\tUINT32_C(0x40000)\n-\t/*\n-\t * This bit must be '1' for the rfs_ring_tbl_idx field to be\n-\t * configured.\n-\t */\n+\t/* This flag is deprecated. */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \\\n \t\tUINT32_C(0x80000)\n \t/*\n@@ -25942,7 +27280,7 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -26038,13 +27376,6 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t * the pri_hint.\n \t */\n \tuint64_t\tntuple_filter_id_hint;\n-\t/*\n-\t * The value of rfs_ring_tbl_idx to be used for RFS for this filter.\n-\t * This index is used in lieu of the RSS hash when selecting the\n-\t * index into the RSS table to determine the rx ring.\n-\t */\n-\tuint16_t\trfs_ring_tbl_idx;\n-\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */\n@@ -26102,7 +27433,7 @@ struct hwrm_cfa_ntuple_filter_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -26180,7 +27511,7 @@ struct hwrm_cfa_ntuple_filter_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -26249,6 +27580,14 @@ struct hwrm_cfa_ntuple_filter_cfg_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * Setting of this flag indicates that the new_dst_id field contains\n+\t * RFS ring table index. If this is not set it indicates new_dst_id is\n+\t * VNIC or VPORT or function ID.  Note dest_fid and dest_rfs_ring_idx\n+\t * can’t be set at the same time.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \\\n+\t\tUINT32_C(0x2)\n \t/* This value is an opaque id into CFA data structures. */\n \tuint64_t\tntuple_filter_id;\n \t/*\n@@ -26293,7 +27632,7 @@ struct hwrm_cfa_ntuple_filter_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -26508,7 +27847,7 @@ struct hwrm_cfa_em_flow_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -26699,7 +28038,7 @@ struct hwrm_cfa_em_flow_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -26759,7 +28098,7 @@ struct hwrm_cfa_em_flow_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -26872,7 +28211,7 @@ struct hwrm_cfa_meter_qcaps_output {\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27150,7 +28489,7 @@ struct hwrm_cfa_meter_profile_alloc_output {\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27235,7 +28574,7 @@ struct hwrm_cfa_meter_profile_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27506,7 +28845,7 @@ struct hwrm_cfa_meter_profile_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27602,7 +28941,7 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27695,7 +29034,7 @@ struct hwrm_cfa_meter_instance_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27780,7 +29119,7 @@ struct hwrm_cfa_meter_instance_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -27958,7 +29297,7 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -28105,7 +29444,7 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -28166,7 +29505,7 @@ struct hwrm_cfa_decap_filter_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -28326,7 +29665,7 @@ struct hwrm_cfa_flow_alloc_input {\n \t\tUINT32_C(0x800)\n \t/*\n \t * If set to 1 an attempt will be made to try to offload this flow to the\n-\t * most optimal flow table resource.  If set to 0, the flow will be\n+\t * most optimal flow table resource. If set to 0, the flow will be\n \t * placed to the default flow table resource.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \\\n@@ -28335,7 +29674,7 @@ struct hwrm_cfa_flow_alloc_input {\n \t * If set to 1 there will be no attempt to allocate an on-chip try to\n \t * offload this flow. If set to 0, which will keep compatibility with the\n \t * older drivers, will cause the FW to attempt to allocate an on-chip flow\n-\t * counter for the newly created flow.  This will keep the existing behavior\n+\t * counter for the newly created flow. This will keep the existing behavior\n \t * with EM flows which always had an associated flow counter.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \\\n@@ -28428,7 +29767,7 @@ struct hwrm_cfa_flow_alloc_input {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -28515,7 +29854,7 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -28612,7 +29951,7 @@ struct hwrm_cfa_flow_free_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -28651,10 +29990,10 @@ struct hwrm_cfa_flow_action_data {\n \t/* If set to 1, flow aging is enabled for this flow. */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \\\n \t\tUINT32_C(0x80)\n-\t/* Setting of this flag indicates encap action.. */\n+\t/* Setting of this flag indicates encap action. */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \\\n \t\tUINT32_C(0x100)\n-\t/* Setting of this flag indicates decap action.. */\n+\t/* Setting of this flag indicates decap action. */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \\\n \t\tUINT32_C(0x200)\n \t/* Meter id. */\n@@ -28680,7 +30019,7 @@ struct hwrm_cfa_flow_action_data {\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP         UINT32_C(0x4)\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE       UINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS         UINT32_C(0x6)\n \t/* VLAN */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN         UINT32_C(0x7)\n@@ -28723,7 +30062,7 @@ struct hwrm_cfa_flow_tunnel_hdr_data {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -28946,7 +30285,7 @@ struct hwrm_cfa_flow_info_output {\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29001,7 +30340,7 @@ struct hwrm_cfa_flow_flush_input {\n \t\tUINT32_C(0x1)\n \t/*\n \t * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA\n-\t * context memory tables..etc.  This flag is set to 0 by older driver. For older firmware,\n+\t * context memory tables etc. This flag is set to 0 by older driver. For older firmware,\n \t * setting this flag has no effect.\n \t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \\\n@@ -29080,7 +30419,7 @@ struct hwrm_cfa_flow_flush_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29221,7 +30560,7 @@ struct hwrm_cfa_flow_stats_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29289,7 +30628,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29414,7 +30753,7 @@ struct hwrm_cfa_flow_aging_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29499,7 +30838,7 @@ struct hwrm_cfa_flow_aging_qcfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29576,7 +30915,7 @@ struct hwrm_cfa_flow_aging_qcaps_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29642,7 +30981,7 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29763,7 +31102,7 @@ struct hwrm_cfa_pair_info_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29841,7 +31180,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n \t\tUINT32_C(0x20)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t/* Multi-Protocol Label Switching (MPLS) */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n \t\tUINT32_C(0x40)\n \t/* Stateless Transport Tunnel (STT) */\n@@ -29868,7 +31207,7 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -29958,14 +31297,14 @@ struct hwrm_cfa_ctx_mem_rgtr_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Id/Handle to the recently register context memory.  This handle is passed\n+\t * Id/Handle to the recently register context memory. This handle is passed\n \t * to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30009,7 +31348,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Id/Handle to the recently register context memory.  This handle is passed\n+\t * Id/Handle to the recently register context memory. This handle is passed\n \t * to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n@@ -30029,7 +31368,7 @@ struct hwrm_cfa_ctx_mem_unrgtr_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30073,7 +31412,7 @@ struct hwrm_cfa_ctx_mem_qctx_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Id/Handle to the recently register context memory.  This handle is passed\n+\t * Id/Handle to the recently register context memory. This handle is passed\n \t * to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n@@ -30127,7 +31466,7 @@ struct hwrm_cfa_ctx_mem_qctx_output {\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30187,7 +31526,7 @@ struct hwrm_cfa_ctx_mem_qcaps_output {\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30278,15 +31617,15 @@ struct hwrm_cfa_eem_qcaps_output {\n \t\tUINT32_C(0x2)\n \t/*\n \t * When set to 1, indicates the the FW supports the Centralized\n-\t * Memory Model.  The concept designates one entity for the\n+\t * Memory Model. The concept designates one entity for the\n \t * memory allocation while all others ‘subscribe’ to it.\n \t */\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n \t\tUINT32_C(0x4)\n \t/*\n \t * When set to 1, indicates the the FW supports the Detached\n-\t * Centralized Memory Model.  The memory is allocated and managed\n-\t * as a separate entity.  All PFs and VFs will be granted direct\n+\t * Centralized Memory Model. The memory is allocated and managed\n+\t * as a separate entity. All PFs and VFs will be granted direct\n \t * or semi-direct access to the allocated memory while none of\n \t * which can interfere with the management of the memory.\n \t */\n@@ -30326,7 +31665,7 @@ struct hwrm_cfa_eem_qcaps_output {\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * The maximum number of entries supported by EEM.   When configuring the host memory\n+\t * The maximum number of entries supported by EEM. When configuring the host memory\n \t * the number of numbers of entries that can supported are -\n \t *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.\n \t * Any value that are not these values, the FW will round down to the closest support\n@@ -30344,7 +31683,7 @@ struct hwrm_cfa_eem_qcaps_output {\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30415,9 +31754,9 @@ struct hwrm_cfa_eem_cfg_input {\n \tuint16_t\tgroup_id;\n \tuint16_t\tunused_0;\n \t/*\n-\t * Configured EEM with the given number of entries.  All the EEM tables KEY0, KEY1,\n+\t * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,\n \t * RECORD, EFC all have the same number of entries and all tables will be configured\n-\t * using this value.  Current minimum value is 32k. Current maximum value is 128M.\n+\t * using this value. Current minimum value is 32k. Current maximum value is 128M.\n \t */\n \tuint32_t\tnum_entries;\n \tuint32_t\tunused_1;\n@@ -30448,7 +31787,7 @@ struct hwrm_cfa_eem_cfg_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30534,7 +31873,7 @@ struct hwrm_cfa_eem_qcfg_output {\n \tuint8_t\tunused_2[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30597,7 +31936,7 @@ struct hwrm_cfa_eem_op_input {\n \t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED    UINT32_C(0x0)\n \t/*\n \t * To properly stop EEM and ensure there are no DMA's, the caller\n-\t * must disable EEM for the given PF, using this call.  This will\n+\t * must disable EEM for the given PF, using this call. This will\n \t * safely disable EEM and ensure that all DMA'ed to the\n \t * keys/records/efc have been completed.\n \t */\n@@ -30605,7 +31944,7 @@ struct hwrm_cfa_eem_op_input {\n \t/*\n \t * Once the EEM host memory has been configured, EEM options have\n \t * been configured. Then the caller should enable EEM for the given\n-\t * PF.  Note once this call has been made, then the EEM mechanism\n+\t * PF. Note once this call has been made, then the EEM mechanism\n \t * will be active and DMA's will occur as packets are processed.\n \t */\n \t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)\n@@ -30631,7 +31970,7 @@ struct hwrm_cfa_eem_op_output {\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30770,10 +32109,34 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \\\n \t\tUINT32_C(0x800)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting ARP ethertype as\n+\t * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the\n+\t * RX direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC\n+\t * command. Value of 0 indicates firmware does not support\n+\t * rfs_ring_tbl_idx in dst_id field.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting IPv4/IPv6 as\n+\t * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX\n+\t * direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -30848,7 +32211,7 @@ struct hwrm_cfa_tflib_output {\n \tuint8_t\tunused1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n@@ -31792,11 +33155,11 @@ struct pcie_ctx_hw_stats {\n \tuint64_t\tpcie_tl_signal_integrity;\n \t/* Number of times LTSSM entered Recovery state */\n \tuint64_t\tpcie_link_integrity;\n-\t/* Number of TLP bytes that have been trasmitted */\n+\t/* Number of TLP bytes that have been transmitted */\n \tuint64_t\tpcie_tx_traffic_rate;\n \t/* Number of TLP bytes that have been received */\n \tuint64_t\tpcie_rx_traffic_rate;\n-\t/* Number of DLLP bytes that have been trasmitted */\n+\t/* Number of DLLP bytes that have been transmitted */\n \tuint64_t\tpcie_tx_dllp_statistics;\n \t/* Number of DLLP bytes that have been received */\n \tuint64_t\tpcie_rx_dllp_statistics;\n@@ -32158,7 +33521,7 @@ struct hwrm_nvm_raw_write_blk_input {\n \tuint64_t\tresp_addr;\n \t/*\n \t * 64-bit Host Source Address.\n-\t * This is the loation of the source data to be written.\n+\t * This is the location of the source data to be written.\n \t */\n \tuint64_t\thost_src_addr;\n \t/*\n@@ -32523,7 +33886,7 @@ struct hwrm_nvm_write_input {\n \t * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).\n \t * If this value is less than the specified data length, it will be ignored.\n \t * The response will contain the actual allocated item length, which may be greater than the requested item length.\n-\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate\n+\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate\n \t * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).\n \t */\n \tuint32_t\tdir_item_length;\n@@ -33105,7 +34468,7 @@ struct hwrm_nvm_install_update_input {\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.\n+\t * If set to 1, then unspecified images, images not in the package file, will be safely deleted.\n \t * When combined with erase_unused_space then unspecified images will be securely erased.\n \t */\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \\\n",
    "prefixes": [
        "06/17"
    ]
}