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{
    "id": 61238,
    "url": "http://patches.dpdk.org/api/patches/61238/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1571130263-120863-6-git-send-email-orika@mellanox.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1571130263-120863-6-git-send-email-orika@mellanox.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1571130263-120863-6-git-send-email-orika@mellanox.com",
    "date": "2019-10-15T09:04:13",
    "name": "[v3,05/14] net/mlx5: support Tx hairpin queues",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2e87cec07ae7ac17fabbcfbf35b753a586c857f8",
    "submitter": {
        "id": 795,
        "url": "http://patches.dpdk.org/api/people/795/?format=api",
        "name": "Ori Kam",
        "email": "orika@mellanox.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1571130263-120863-6-git-send-email-orika@mellanox.com/mbox/",
    "series": [
        {
            "id": 6855,
            "url": "http://patches.dpdk.org/api/series/6855/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6855",
            "date": "2019-10-15T09:04:08",
            "name": "add hairpin feature",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/6855/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/61238/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/61238/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 14B661E89A;\n\tTue, 15 Oct 2019 11:05:27 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id E5B761E889\n\tfor <dev@dpdk.org>; Tue, 15 Oct 2019 11:05:25 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n\torika@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 15 Oct 2019 11:05:22 +0200",
            "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n\t[10.210.16.126])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x9F94hcg029891;\n\tTue, 15 Oct 2019 12:05:22 +0300"
        ],
        "From": "Ori Kam <orika@mellanox.com>",
        "To": "Matan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>",
        "Cc": "dev@dpdk.org, orika@mellanox.com, jingjing.wu@intel.com,\n\tstephen@networkplumber.org",
        "Date": "Tue, 15 Oct 2019 09:04:13 +0000",
        "Message-Id": "<1571130263-120863-6-git-send-email-orika@mellanox.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1571130263-120863-1-git-send-email-orika@mellanox.com>",
        "References": "<1569479349-36962-1-git-send-email-orika@mellanox.com>\n\t<1571130263-120863-1-git-send-email-orika@mellanox.com>",
        "Subject": "[dpdk-dev] [PATCH v3 05/14] net/mlx5: support Tx hairpin queues",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This commit adds the support for creating Tx hairpin queues.\nHairpin queue is a queue that is created using DevX and only used\nby the HW.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n\n---\n drivers/net/mlx5/mlx5.c           |  36 +++++-\n drivers/net/mlx5/mlx5.h           |  46 ++++++++\n drivers/net/mlx5/mlx5_devx_cmds.c | 186 ++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_prm.h       | 118 +++++++++++++++++++\n drivers/net/mlx5/mlx5_rxtx.h      |  18 ++-\n drivers/net/mlx5/mlx5_trigger.c   |  10 +-\n drivers/net/mlx5/mlx5_txq.c       | 230 +++++++++++++++++++++++++++++++++++---\n 7 files changed, 620 insertions(+), 24 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 2431a55..c53a9c6 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -325,6 +325,9 @@ struct mlx5_dev_spawn_data {\n \tstruct mlx5_ibv_shared *sh;\n \tint err = 0;\n \tuint32_t i;\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tstruct mlx5_devx_tis_attr tis_attr = { 0 };\n+#endif\n \n \tassert(spawn);\n \t/* Secondary process should not create the shared context. */\n@@ -389,10 +392,25 @@ struct mlx5_dev_spawn_data {\n \t\tgoto error;\n \t}\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\terr = mlx5_get_pdn(sh->pd, &sh->pdn);\n-\tif (err) {\n-\t\tDRV_LOG(ERR, \"Fail to extract pdn from PD\");\n-\t\tgoto error;\n+\tif (sh->devx) {\n+\t\terr = mlx5_get_pdn(sh->pd, &sh->pdn);\n+\t\tif (err) {\n+\t\t\tDRV_LOG(ERR, \"Fail to extract pdn from PD\");\n+\t\t\tgoto error;\n+\t\t}\n+\t\tsh->td = mlx5_devx_cmd_create_td(sh->ctx);\n+\t\tif (!sh->td) {\n+\t\t\tDRV_LOG(ERR, \"TD allocation failure\");\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n+\t\ttis_attr.transport_domain = sh->td->id;\n+\t\tsh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);\n+\t\tif (!sh->tis) {\n+\t\t\tDRV_LOG(ERR, \"TIS allocation failure\");\n+\t\t\terr = ENOMEM;\n+\t\t\tgoto error;\n+\t\t}\n \t}\n #endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n \t/*\n@@ -425,6 +443,10 @@ struct mlx5_dev_spawn_data {\n error:\n \tpthread_mutex_unlock(&mlx5_ibv_list_mutex);\n \tassert(sh);\n+\tif (sh->tis)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sh->tis));\n+\tif (sh->td)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sh->td));\n \tif (sh->pd)\n \t\tclaim_zero(mlx5_glue->dealloc_pd(sh->pd));\n \tif (sh->ctx)\n@@ -485,6 +507,10 @@ struct mlx5_dev_spawn_data {\n \tpthread_mutex_destroy(&sh->intr_mutex);\n \tif (sh->pd)\n \t\tclaim_zero(mlx5_glue->dealloc_pd(sh->pd));\n+\tif (sh->tis)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sh->tis));\n+\tif (sh->td)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(sh->td));\n \tif (sh->ctx)\n \t\tclaim_zero(mlx5_glue->close_device(sh->ctx));\n \trte_free(sh);\n@@ -976,6 +1002,7 @@ struct mlx5_dev_spawn_data {\n \t.rx_queue_setup = mlx5_rx_queue_setup,\n \t.rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,\n \t.tx_queue_setup = mlx5_tx_queue_setup,\n+\t.tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,\n \t.rx_queue_release = mlx5_rx_queue_release,\n \t.tx_queue_release = mlx5_tx_queue_release,\n \t.flow_ctrl_get = mlx5_dev_get_flow_ctrl,\n@@ -1043,6 +1070,7 @@ struct mlx5_dev_spawn_data {\n \t.rx_queue_setup = mlx5_rx_queue_setup,\n \t.rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,\n \t.tx_queue_setup = mlx5_tx_queue_setup,\n+\t.tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,\n \t.rx_queue_release = mlx5_rx_queue_release,\n \t.tx_queue_release = mlx5_tx_queue_release,\n \t.flow_ctrl_get = mlx5_dev_get_flow_ctrl,\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 36cced9..7ea4950 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -350,6 +350,43 @@ struct mlx5_devx_rqt_attr {\n \tuint32_t rq_list[];\n };\n \n+/* TIS attributes structure. */\n+struct mlx5_devx_tis_attr {\n+\tuint32_t strict_lag_tx_port_affinity:1;\n+\tuint32_t tls_en:1;\n+\tuint32_t lag_tx_port_affinity:4;\n+\tuint32_t prio:4;\n+\tuint32_t transport_domain:24;\n+};\n+\n+/* SQ attributes structure, used by SQ create operation. */\n+struct mlx5_devx_create_sq_attr {\n+\tuint32_t rlky:1;\n+\tuint32_t cd_master:1;\n+\tuint32_t fre:1;\n+\tuint32_t flush_in_error_en:1;\n+\tuint32_t allow_multi_pkt_send_wqe:1;\n+\tuint32_t min_wqe_inline_mode:3;\n+\tuint32_t state:4;\n+\tuint32_t reg_umr:1;\n+\tuint32_t allow_swp:1;\n+\tuint32_t hairpin:1;\n+\tuint32_t user_index:24;\n+\tuint32_t cqn:24;\n+\tuint32_t packet_pacing_rate_limit_index:16;\n+\tuint32_t tis_lst_sz:16;\n+\tuint32_t tis_num:24;\n+\tstruct mlx5_devx_wq_attr wq_attr;\n+};\n+\n+/* SQ attributes structure, used by SQ modify operation. */\n+struct mlx5_devx_modify_sq_attr {\n+\tuint32_t sq_state:4;\n+\tuint32_t state:4;\n+\tuint32_t hairpin_peer_rq:24;\n+\tuint32_t hairpin_peer_vhca:16;\n+};\n+\n /**\n  * Type of object being allocated.\n  */\n@@ -591,6 +628,8 @@ struct mlx5_ibv_shared {\n \tstruct rte_intr_handle intr_handle; /* Interrupt handler for device. */\n \tstruct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */\n \tstruct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */\n+\tstruct mlx5_devx_obj *tis; /* TIS object. */\n+\tstruct mlx5_devx_obj *td; /* Transport domain. */\n \tstruct mlx5_ibv_shared_port port[]; /* per device port data array. */\n };\n \n@@ -911,5 +950,12 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,\n \t\t\t\t\tstruct mlx5_devx_tir_attr *tir_attr);\n struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,\n \t\t\t\t\tstruct mlx5_devx_rqt_attr *rqt_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_sq\n+\t(struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);\n+int mlx5_devx_cmd_modify_sq\n+\t(struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_tis\n+\t(struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex b072c37..917bbf9 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -709,3 +709,189 @@ struct mlx5_devx_obj *\n \trqt->id = MLX5_GET(create_rqt_out, out, rqtn);\n \treturn rqt;\n }\n+\n+/**\n+ * Create SQ using DevX API.\n+ *\n+ * @param[in] ctx\n+ *   ibv_context returned from mlx5dv_open_device.\n+ * @param [in] sq_attr\n+ *   Pointer to SQ attributes structure.\n+ * @param [in] socket\n+ *   CPU socket ID for allocations.\n+ *\n+ * @return\n+ *   The DevX object created, NULL otherwise and rte_errno is set.\n+ **/\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_sq(struct ibv_context *ctx,\n+\t\t\tstruct mlx5_devx_create_sq_attr *sq_attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};\n+\tvoid *sq_ctx;\n+\tvoid *wq_ctx;\n+\tstruct mlx5_devx_wq_attr *wq_attr;\n+\tstruct mlx5_devx_obj *sq = NULL;\n+\n+\tsq = rte_calloc(__func__, 1, sizeof(*sq), 0);\n+\tif (!sq) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate SQ data\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);\n+\tsq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);\n+\tMLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);\n+\tMLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);\n+\tMLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);\n+\tMLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);\n+\tMLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,\n+\t\t sq_attr->flush_in_error_en);\n+\tMLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,\n+\t\t sq_attr->min_wqe_inline_mode);\n+\tMLX5_SET(sqc, sq_ctx, state, sq_attr->state);\n+\tMLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);\n+\tMLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);\n+\tMLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);\n+\tMLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);\n+\tMLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);\n+\tMLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,\n+\t\t sq_attr->packet_pacing_rate_limit_index);\n+\tMLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);\n+\tMLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);\n+\twq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);\n+\twq_attr = &sq_attr->wq_attr;\n+\tdevx_cmd_fill_wq_data(wq_ctx, wq_attr);\n+\tsq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t     out, sizeof(out));\n+\tif (!sq->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create SQ using DevX\");\n+\t\trte_errno = errno;\n+\t\trte_free(sq);\n+\t\treturn NULL;\n+\t}\n+\tsq->id = MLX5_GET(create_sq_out, out, sqn);\n+\treturn sq;\n+}\n+\n+/**\n+ * Modify SQ using DevX API.\n+ *\n+ * @param[in] sq\n+ *   Pointer to SQ object structure.\n+ * @param [in] sq_attr\n+ *   Pointer to SQ attributes structure.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,\n+\t\t\tstruct mlx5_devx_modify_sq_attr *sq_attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};\n+\tvoid *sq_ctx;\n+\tint ret;\n+\n+\tMLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);\n+\tMLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);\n+\tMLX5_SET(modify_sq_in, in, sqn, sq->id);\n+\tsq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);\n+\tMLX5_SET(sqc, sq_ctx, state, sq_attr->state);\n+\tMLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);\n+\tMLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);\n+\tret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to modify SQ using DevX\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * Create TIS using DevX API.\n+ *\n+ * @param[in] ctx\n+ *   ibv_context returned from mlx5dv_open_device.\n+ * @param [in] tis_attr\n+ *   Pointer to TIS attributes structure.\n+ *\n+ * @return\n+ *   The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_tis(struct ibv_context *ctx,\n+\t\t\t struct mlx5_devx_tis_attr *tis_attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};\n+\tstruct mlx5_devx_obj *tis = NULL;\n+\tvoid *tis_ctx;\n+\n+\ttis = rte_calloc(__func__, 1, sizeof(*tis), 0);\n+\tif (!tis) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate TIS object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);\n+\ttis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);\n+\tMLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,\n+\t\t tis_attr->strict_lag_tx_port_affinity);\n+\tMLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,\n+\t\t tis_attr->strict_lag_tx_port_affinity);\n+\tMLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);\n+\tMLX5_SET(tisc, tis_ctx, transport_domain,\n+\t\t tis_attr->transport_domain);\n+\ttis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t      out, sizeof(out));\n+\tif (!tis->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create TIS using DevX\");\n+\t\trte_errno = errno;\n+\t\trte_free(tis);\n+\t\treturn NULL;\n+\t}\n+\ttis->id = MLX5_GET(create_tis_out, out, tisn);\n+\treturn tis;\n+}\n+\n+/**\n+ * Create transport domain using DevX API.\n+ *\n+ * @param[in] ctx\n+ *   ibv_context returned from mlx5dv_open_device.\n+ *\n+ * @return\n+ *   The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_td(struct ibv_context *ctx)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};\n+\tstruct mlx5_devx_obj *td = NULL;\n+\n+\ttd = rte_calloc(__func__, 1, sizeof(*td), 0);\n+\tif (!td) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate TD object\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(alloc_transport_domain_in, in, opcode,\n+\t\t MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);\n+\ttd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t     out, sizeof(out));\n+\tif (!td->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create TIS using DevX\");\n+\t\trte_errno = errno;\n+\t\trte_free(td);\n+\t\treturn NULL;\n+\t}\n+\ttd->id = MLX5_GET(alloc_transport_domain_out, out,\n+\t\t\t   transport_domain);\n+\treturn td;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 3765df0..faa7996 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -666,9 +666,13 @@ enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_CREATE_MKEY = 0x200,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n+\tMLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,\n \tMLX5_CMD_OP_CREATE_TIR = 0x900,\n+\tMLX5_CMD_OP_CREATE_SQ = 0X904,\n+\tMLX5_CMD_OP_MODIFY_SQ = 0X905,\n \tMLX5_CMD_OP_CREATE_RQ = 0x908,\n \tMLX5_CMD_OP_MODIFY_RQ = 0x909,\n+\tMLX5_CMD_OP_CREATE_TIS = 0x912,\n \tMLX5_CMD_OP_QUERY_TIS = 0x915,\n \tMLX5_CMD_OP_CREATE_RQT = 0x916,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n@@ -1311,6 +1315,23 @@ struct mlx5_ifc_query_tis_in_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+struct mlx5_ifc_alloc_transport_domain_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 transport_domain[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_alloc_transport_domain_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n enum {\n \tMLX5_WQ_TYPE_LINKED_LIST                = 0x0,\n \tMLX5_WQ_TYPE_CYCLIC                     = 0x1,\n@@ -1427,6 +1448,24 @@ struct mlx5_ifc_modify_rq_out_bits {\n \tu8 reserved_at_40[0x40];\n };\n \n+struct mlx5_ifc_create_tis_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 tisn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_tis_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_tisc_bits ctx;\n+};\n+\n enum {\n \tMLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,\n \tMLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,\n@@ -1572,6 +1611,85 @@ struct mlx5_ifc_create_rqt_in_bits {\n #pragma GCC diagnostic error \"-Wpedantic\"\n #endif\n \n+struct mlx5_ifc_sqc_bits {\n+\tu8 rlky[0x1];\n+\tu8 cd_master[0x1];\n+\tu8 fre[0x1];\n+\tu8 flush_in_error_en[0x1];\n+\tu8 allow_multi_pkt_send_wqe[0x1];\n+\tu8 min_wqe_inline_mode[0x3];\n+\tu8 state[0x4];\n+\tu8 reg_umr[0x1];\n+\tu8 allow_swp[0x1];\n+\tu8 hairpin[0x1];\n+\tu8 reserved_at_f[0x11];\n+\tu8 reserved_at_20[0x8];\n+\tu8 user_index[0x18];\n+\tu8 reserved_at_40[0x8];\n+\tu8 cqn[0x18];\n+\tu8 reserved_at_60[0x8];\n+\tu8 hairpin_peer_rq[0x18];\n+\tu8 reserved_at_80[0x10];\n+\tu8 hairpin_peer_vhca[0x10];\n+\tu8 reserved_at_a0[0x50];\n+\tu8 packet_pacing_rate_limit_index[0x10];\n+\tu8 tis_lst_sz[0x10];\n+\tu8 reserved_at_110[0x10];\n+\tu8 reserved_at_120[0x40];\n+\tu8 reserved_at_160[0x8];\n+\tu8 tis_num_0[0x18];\n+\tstruct mlx5_ifc_wq_bits wq;\n+};\n+\n+struct mlx5_ifc_query_sq_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 sqn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_modify_sq_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n+struct mlx5_ifc_modify_sq_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 sq_state[0x4];\n+\tu8 reserved_at_44[0x4];\n+\tu8 sqn[0x18];\n+\tu8 reserved_at_60[0x20];\n+\tu8 modify_bitmask[0x40];\n+\tu8 reserved_at_c0[0x40];\n+\tstruct mlx5_ifc_sqc_bits ctx;\n+};\n+\n+struct mlx5_ifc_create_sq_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 sqn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_sq_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_sqc_bits ctx;\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 12f9bfb..271b648 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -324,14 +324,18 @@ struct mlx5_txq_obj {\n \tLIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */\n \trte_atomic32_t refcnt; /* Reference counter. */\n \tstruct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */\n-\tenum mlx5_rxq_obj_type type; /* The txq object type. */\n+\tenum mlx5_txq_obj_type type; /* The txq object type. */\n \tRTE_STD_C11\n \tunion {\n \t\tstruct {\n \t\t\tstruct ibv_cq *cq; /* Completion Queue. */\n \t\t\tstruct ibv_qp *qp; /* Queue Pair. */\n \t\t};\n-\t\tstruct mlx5_devx_obj *sq; /* DevX object for Sx queue. */\n+\t\tstruct {\n+\t\t\tstruct mlx5_devx_obj *sq;\n+\t\t\t/* DevX object for Sx queue. */\n+\t\t\tstruct mlx5_devx_obj *tis; /* The TIS object. */\n+\t\t};\n \t};\n };\n \n@@ -348,6 +352,7 @@ struct mlx5_txq_ctrl {\n \toff_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */\n \tvoid *bf_reg; /* BlueFlame register from Verbs. */\n \tuint16_t dump_file_n; /* Number of dump files. */\n+\tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n \tstruct mlx5_txq_data txq; /* Data path structure. */\n \t/* Must be the last field in the structure, contains elts[]. */\n };\n@@ -410,15 +415,22 @@ struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,\n \n int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t\tunsigned int socket, const struct rte_eth_txconf *conf);\n+int mlx5_tx_hairpin_queue_setup\n+\t(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t const struct rte_eth_hairpin_conf *hairpin_conf);\n void mlx5_tx_queue_release(void *dpdk_txq);\n int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);\n-struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,\n+\t\t\t\t      enum mlx5_txq_obj_type type);\n struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);\n int mlx5_txq_obj_verify(struct rte_eth_dev *dev);\n struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,\n \t\t\t\t   uint16_t desc, unsigned int socket,\n \t\t\t\t   const struct rte_eth_txconf *conf);\n+struct mlx5_txq_ctrl *mlx5_txq_hairpin_new\n+\t(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t const struct rte_eth_hairpin_conf *hairpin_conf);\n struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 50c4df5..3ec86c4 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -51,8 +51,14 @@\n \n \t\tif (!txq_ctrl)\n \t\t\tcontinue;\n-\t\ttxq_alloc_elts(txq_ctrl);\n-\t\ttxq_ctrl->obj = mlx5_txq_obj_new(dev, i);\n+\t\tif (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {\n+\t\t\ttxq_ctrl->obj = mlx5_txq_obj_new\n+\t\t\t\t(dev, i, MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN);\n+\t\t} else {\n+\t\t\ttxq_alloc_elts(txq_ctrl);\n+\t\t\ttxq_ctrl->obj = mlx5_txq_obj_new\n+\t\t\t\t(dev, i, MLX5_TXQ_OBJ_TYPE_IBV);\n+\t\t}\n \t\tif (!txq_ctrl->obj) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tgoto error;\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex a6e2563..f9bfe31 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -136,30 +136,22 @@\n }\n \n /**\n- * DPDK callback to configure a TX queue.\n+ * Tx queue presetup checks.\n  *\n  * @param dev\n  *   Pointer to Ethernet device structure.\n  * @param idx\n- *   TX queue index.\n+ *   Tx queue index.\n  * @param desc\n  *   Number of descriptors to configure in queue.\n- * @param socket\n- *   NUMA socket on which memory must be allocated.\n- * @param[in] conf\n- *   Thresholds parameters.\n  *\n  * @return\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n-int\n-mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n-\t\t    unsigned int socket, const struct rte_eth_txconf *conf)\n+static int\n+mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_txq_data *txq = (*priv->txqs)[idx];\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n \n \tif (desc <= MLX5_TX_COMP_THRESH) {\n \t\tDRV_LOG(WARNING,\n@@ -191,6 +183,38 @@\n \t\treturn -rte_errno;\n \t}\n \tmlx5_txq_release(dev, idx);\n+\treturn 0;\n+}\n+/**\n+ * DPDK callback to configure a TX queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param idx\n+ *   TX queue index.\n+ * @param desc\n+ *   Number of descriptors to configure in queue.\n+ * @param socket\n+ *   NUMA socket on which memory must be allocated.\n+ * @param[in] conf\n+ *   Thresholds parameters.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t\t    unsigned int socket, const struct rte_eth_txconf *conf)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_data *txq = (*priv->txqs)[idx];\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n+\tint res;\n+\n+\tres = mlx5_tx_queue_pre_setup(dev, idx, desc);\n+\tif (res)\n+\t\treturn res;\n \ttxq_ctrl = mlx5_txq_new(dev, idx, desc, socket, conf);\n \tif (!txq_ctrl) {\n \t\tDRV_LOG(ERR, \"port %u unable to allocate queue index %u\",\n@@ -204,6 +228,57 @@\n }\n \n /**\n+ * DPDK callback to configure a TX hairpin queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param idx\n+ *   TX queue index.\n+ * @param desc\n+ *   Number of descriptors to configure in queue.\n+ * @param[in] hairpin_conf\n+ *   The hairpin binding configuration.\n+ *\n+ * @return\n+ *   0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,\n+\t\t\t    uint16_t desc,\n+\t\t\t    const struct rte_eth_hairpin_conf *hairpin_conf)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_data *txq = (*priv->txqs)[idx];\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\tcontainer_of(txq, struct mlx5_txq_ctrl, txq);\n+\tint res;\n+\n+\tres = mlx5_tx_queue_pre_setup(dev, idx, desc);\n+\tif (res)\n+\t\treturn res;\n+\tif (hairpin_conf->peer_n != 1 ||\n+\t    hairpin_conf->peers[0].port != dev->data->port_id ||\n+\t    hairpin_conf->peers[0].queue >= priv->rxqs_n) {\n+\t\tDRV_LOG(ERR, \"port %u unable to setup hairpin queue index %u \"\n+\t\t\t\" invalid hairpind configuration\", dev->data->port_id,\n+\t\t\tidx);\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\ttxq_ctrl = mlx5_txq_hairpin_new(dev, idx, desc,\thairpin_conf);\n+\tif (!txq_ctrl) {\n+\t\tDRV_LOG(ERR, \"port %u unable to allocate queue index %u\",\n+\t\t\tdev->data->port_id, idx);\n+\t\treturn -rte_errno;\n+\t}\n+\tDRV_LOG(DEBUG, \"port %u adding Tx queue %u to list\",\n+\t\tdev->data->port_id, idx);\n+\t(*priv->txqs)[idx] = &txq_ctrl->txq;\n+\ttxq_ctrl->type = MLX5_TXQ_TYPE_HAIRPIN;\n+\treturn 0;\n+}\n+\n+/**\n  * DPDK callback to release a TX queue.\n  *\n  * @param dpdk_txq\n@@ -246,6 +321,8 @@\n \tconst size_t page_size = sysconf(_SC_PAGESIZE);\n #endif\n \n+\tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n+\t\treturn;\n \tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \tassert(ppriv);\n \tppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;\n@@ -282,6 +359,8 @@\n \tuintptr_t offset;\n \tconst size_t page_size = sysconf(_SC_PAGESIZE);\n \n+\tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n+\t\treturn 0;\n \tassert(ppriv);\n \t/*\n \t * As rdma-core, UARs are mapped in size of OS page\n@@ -316,6 +395,8 @@\n \tconst size_t page_size = sysconf(_SC_PAGESIZE);\n \tvoid *addr;\n \n+\tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n+\t\treturn;\n \taddr = ppriv->uar_table[txq_ctrl->txq.idx];\n \tmunmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size);\n }\n@@ -346,6 +427,8 @@\n \t\t\tcontinue;\n \t\ttxq = (*priv->txqs)[i];\n \t\ttxq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq);\n+\t\tif (txq_ctrl->type != MLX5_TXQ_TYPE_STANDARD)\n+\t\t\tcontinue;\n \t\tassert(txq->idx == (uint16_t)i);\n \t\tret = txq_uar_init_secondary(txq_ctrl, fd);\n \t\tif (ret)\n@@ -365,18 +448,87 @@\n }\n \n /**\n+ * Create the Tx hairpin queue object.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   Queue index in DPDK Tx queue array\n+ *\n+ * @return\n+ *   The hairpin DevX object initialised, NULL otherwise and rte_errno is set.\n+ */\n+static struct mlx5_txq_obj *\n+mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n+\tstruct mlx5_txq_ctrl *txq_ctrl =\n+\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n+\tstruct mlx5_devx_create_sq_attr attr = { 0 };\n+\tstruct mlx5_txq_obj *tmpl = NULL;\n+\tint ret = 0;\n+\n+\tassert(txq_data);\n+\tassert(!txq_ctrl->obj);\n+\ttmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,\n+\t\t\t\t txq_ctrl->socket);\n+\tif (!tmpl) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"port %u Tx queue %u cannot allocate memory resources\",\n+\t\t\tdev->data->port_id, txq_data->idx);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\ttmpl->type = MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN;\n+\ttmpl->txq_ctrl = txq_ctrl;\n+\tattr.hairpin = 1;\n+\tattr.tis_lst_sz = 1;\n+\t/* Workaround for hairpin startup */\n+\tattr.wq_attr.log_hairpin_num_packets = log2above(32);\n+\t/* Workaround for packets larger than 1KB */\n+\tattr.wq_attr.log_hairpin_data_sz =\n+\t\t\tpriv->config.hca_attr.log_max_hairpin_wq_data_sz;\n+\tattr.tis_num = priv->sh->tis->id;\n+\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->ctx, &attr);\n+\tif (!tmpl->sq) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"port %u tx hairpin queue %u can't create sq object\",\n+\t\t\tdev->data->port_id, idx);\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\tDRV_LOG(DEBUG, \"port %u sxq %u updated with %p\", dev->data->port_id,\n+\t\tidx, (void *)&tmpl);\n+\trte_atomic32_inc(&tmpl->refcnt);\n+\tLIST_INSERT_HEAD(&priv->txqsobj, tmpl, next);\n+\treturn tmpl;\n+error:\n+\tret = rte_errno; /* Save rte_errno before cleanup. */\n+\tif (tmpl->tis)\n+\t\tmlx5_devx_cmd_destroy(tmpl->tis);\n+\tif (tmpl->sq)\n+\t\tmlx5_devx_cmd_destroy(tmpl->sq);\n+\trte_errno = ret; /* Restore rte_errno. */\n+\treturn NULL;\n+}\n+\n+/**\n  * Create the Tx queue Verbs object.\n  *\n  * @param dev\n  *   Pointer to Ethernet device.\n  * @param idx\n  *   Queue index in DPDK Tx queue array.\n+ * @param type\n+ *   Type of the Tx queue object to create.\n  *\n  * @return\n  *   The Verbs object initialised, NULL otherwise and rte_errno is set.\n  */\n struct mlx5_txq_obj *\n-mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n+mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,\n+\t\t enum mlx5_txq_obj_type type)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n@@ -396,6 +548,8 @@ struct mlx5_txq_obj *\n \tconst int desc = 1 << txq_data->elts_n;\n \tint ret = 0;\n \n+\tif (type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN)\n+\t\treturn mlx5_txq_obj_hairpin_new(dev, idx);\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/* If using DevX, need additional mask to read tisn value. */\n \tif (priv->config.devx && !priv->sh->tdn)\n@@ -643,8 +797,13 @@ struct mlx5_txq_obj *\n {\n \tassert(txq_obj);\n \tif (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {\n-\t\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n-\t\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+\t\tif (txq_obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN) {\n+\t\t\tif (txq_obj->tis)\n+\t\t\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));\n+\t\t} else {\n+\t\t\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n+\t\t\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+\t\t}\n \t\tLIST_REMOVE(txq_obj, next);\n \t\trte_free(txq_obj);\n \t\treturn 0;\n@@ -1100,6 +1259,7 @@ struct mlx5_txq_ctrl *\n \t\tgoto error;\n \t}\n \trte_atomic32_inc(&tmpl->refcnt);\n+\ttmpl->type = MLX5_TXQ_TYPE_STANDARD;\n \tLIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);\n \treturn tmpl;\n error:\n@@ -1108,6 +1268,46 @@ struct mlx5_txq_ctrl *\n }\n \n /**\n+ * Create a DPDK Tx hairpin queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param idx\n+ *   TX queue index.\n+ * @param desc\n+ *   Number of descriptors to configure in queue.\n+ * @param hairpin_conf\n+ *  The hairpin configuration.\n+ *\n+ * @return\n+ *   A DPDK queue object on success, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_txq_ctrl *\n+mlx5_txq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t\t     const struct rte_eth_hairpin_conf *hairpin_conf)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_txq_ctrl *tmpl;\n+\n+\ttmpl = rte_calloc_socket(\"TXQ\", 1,\n+\t\t\t\t sizeof(*tmpl), 0, SOCKET_ID_ANY);\n+\tif (!tmpl) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\ttmpl->priv = priv;\n+\ttmpl->socket = SOCKET_ID_ANY;\n+\ttmpl->txq.elts_n = log2above(desc);\n+\ttmpl->txq.port_id = dev->data->port_id;\n+\ttmpl->txq.idx = idx;\n+\ttmpl->hairpin_conf = *hairpin_conf;\n+\ttmpl->type = MLX5_TXQ_TYPE_HAIRPIN;\n+\trte_atomic32_inc(&tmpl->refcnt);\n+\tLIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);\n+\treturn tmpl;\n+}\n+\n+/**\n  * Get a Tx queue.\n  *\n  * @param dev\n",
    "prefixes": [
        "v3",
        "05/14"
    ]
}