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GET /api/patches/61237/?format=api
{ "id": 61237, "url": "http://patches.dpdk.org/api/patches/61237/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1571130263-120863-5-git-send-email-orika@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1571130263-120863-5-git-send-email-orika@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1571130263-120863-5-git-send-email-orika@mellanox.com", "date": "2019-10-15T09:04:12", "name": "[v3,04/14] net/mlx5: prepare txq to work with different types", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "feac65fcf4cc197d26ed78f960fabb583b8047ab", "submitter": { "id": 795, "url": "http://patches.dpdk.org/api/people/795/?format=api", "name": "Ori Kam", "email": "orika@mellanox.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1571130263-120863-5-git-send-email-orika@mellanox.com/mbox/", "series": [ { "id": 6855, "url": "http://patches.dpdk.org/api/series/6855/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6855", "date": "2019-10-15T09:04:08", "name": "add hairpin feature", "version": 3, "mbox": "http://patches.dpdk.org/series/6855/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/61237/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/61237/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2AFB21E555;\n\tTue, 15 Oct 2019 11:05:22 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id E78D41E54A\n\tfor <dev@dpdk.org>; Tue, 15 Oct 2019 11:05:20 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\torika@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 15 Oct 2019 11:05:16 +0200", "from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx\n\t[10.210.16.126])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x9F94hcf029891;\n\tTue, 15 Oct 2019 12:05:16 +0300" ], "From": "Ori Kam <orika@mellanox.com>", "To": "Matan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, orika@mellanox.com, jingjing.wu@intel.com,\n\tstephen@networkplumber.org", "Date": "Tue, 15 Oct 2019 09:04:12 +0000", "Message-Id": "<1571130263-120863-5-git-send-email-orika@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1571130263-120863-1-git-send-email-orika@mellanox.com>", "References": "<1569479349-36962-1-git-send-email-orika@mellanox.com>\n\t<1571130263-120863-1-git-send-email-orika@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v3 04/14] net/mlx5: prepare txq to work with\n\tdifferent types", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currenlty all Tx queues are created using Verbs.\nThis commit modify the naming so it will not include verbs,\nsince in next commit a new type will be introduce (hairpin)\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n\n---\n drivers/net/mlx5/mlx5.c | 2 +-\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_rxtx.c | 2 +-\n drivers/net/mlx5/mlx5_rxtx.h | 39 +++++++++++++++++------\n drivers/net/mlx5/mlx5_trigger.c | 4 +--\n drivers/net/mlx5/mlx5_txq.c | 70 ++++++++++++++++++++---------------------\n 6 files changed, 69 insertions(+), 50 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 49edb7e..2431a55 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -911,7 +911,7 @@ struct mlx5_dev_spawn_data {\n \tif (ret)\n \t\tDRV_LOG(WARNING, \"port %u some Rx queues still remain\",\n \t\t\tdev->data->port_id);\n-\tret = mlx5_txq_ibv_verify(dev);\n+\tret = mlx5_txq_obj_verify(dev);\n \tif (ret)\n \t\tDRV_LOG(WARNING, \"port %u some Verbs Tx queue still remain\",\n \t\t\tdev->data->port_id);\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4d14e9e..36cced9 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -645,7 +645,7 @@ struct mlx5_priv {\n \tLIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */\n \tLIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */\n \tLIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */\n-\tLIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */\n+\tLIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */\n \t/* Indirection tables. */\n \tLIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;\n \t/* Pointer to next element. */\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 10d0ca1..f23708c 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -863,7 +863,7 @@ enum mlx5_txcmp_code {\n \t\t\t.qp_state = IBV_QPS_RESET,\n \t\t\t.port_num = (uint8_t)priv->ibv_port,\n \t\t};\n-\t\tstruct ibv_qp *qp = txq_ctrl->ibv->qp;\n+\t\tstruct ibv_qp *qp = txq_ctrl->obj->qp;\n \n \t\tret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);\n \t\tif (ret) {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex 13fdc38..12f9bfb 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -308,13 +308,31 @@ struct mlx5_txq_data {\n \t/* Storage for queued packets, must be the last field. */\n } __rte_cache_aligned;\n \n-/* Verbs Rx queue elements. */\n-struct mlx5_txq_ibv {\n-\tLIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */\n+enum mlx5_txq_obj_type {\n+\tMLX5_TXQ_OBJ_TYPE_IBV,\t\t/* mlx5_txq_obj with ibv_wq. */\n+\tMLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,\n+\t/* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */\n+};\n+\n+enum mlx5_txq_type {\n+\tMLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */\n+\tMLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */\n+};\n+\n+/* Verbs/DevX Tx queue elements. */\n+struct mlx5_txq_obj {\n+\tLIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */\n \trte_atomic32_t refcnt; /* Reference counter. */\n \tstruct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */\n-\tstruct ibv_cq *cq; /* Completion Queue. */\n-\tstruct ibv_qp *qp; /* Queue Pair. */\n+\tenum mlx5_rxq_obj_type type; /* The txq object type. */\n+\tRTE_STD_C11\n+\tunion {\n+\t\tstruct {\n+\t\t\tstruct ibv_cq *cq; /* Completion Queue. */\n+\t\t\tstruct ibv_qp *qp; /* Queue Pair. */\n+\t\t};\n+\t\tstruct mlx5_devx_obj *sq; /* DevX object for Sx queue. */\n+\t};\n };\n \n /* TX queue control descriptor. */\n@@ -322,9 +340,10 @@ struct mlx5_txq_ctrl {\n \tLIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */\n \trte_atomic32_t refcnt; /* Reference counter. */\n \tunsigned int socket; /* CPU socket ID for allocations. */\n+\tenum mlx5_txq_type type; /* The txq ctrl type. */\n \tunsigned int max_inline_data; /* Max inline data. */\n \tunsigned int max_tso_header; /* Max TSO header size. */\n-\tstruct mlx5_txq_ibv *ibv; /* Verbs queue object. */\n+\tstruct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */\n \tstruct mlx5_priv *priv; /* Back pointer to private data. */\n \toff_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */\n \tvoid *bf_reg; /* BlueFlame register from Verbs. */\n@@ -393,10 +412,10 @@ int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t\t\tunsigned int socket, const struct rte_eth_txconf *conf);\n void mlx5_tx_queue_release(void *dpdk_txq);\n int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);\n-struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);\n-struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);\n-int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);\n-int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);\n+struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx);\n+struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);\n+int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);\n+int mlx5_txq_obj_verify(struct rte_eth_dev *dev);\n struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,\n \t\t\t\t uint16_t desc, unsigned int socket,\n \t\t\t\t const struct rte_eth_txconf *conf);\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex cb31ae2..50c4df5 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -52,8 +52,8 @@\n \t\tif (!txq_ctrl)\n \t\t\tcontinue;\n \t\ttxq_alloc_elts(txq_ctrl);\n-\t\ttxq_ctrl->ibv = mlx5_txq_ibv_new(dev, i);\n-\t\tif (!txq_ctrl->ibv) {\n+\t\ttxq_ctrl->obj = mlx5_txq_obj_new(dev, i);\n+\t\tif (!txq_ctrl->obj) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tgoto error;\n \t\t}\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 53d45e7..a6e2563 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -375,15 +375,15 @@\n * @return\n * The Verbs object initialised, NULL otherwise and rte_errno is set.\n */\n-struct mlx5_txq_ibv *\n-mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)\n+struct mlx5_txq_obj *\n+mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_txq_ibv tmpl;\n-\tstruct mlx5_txq_ibv *txq_ibv = NULL;\n+\tstruct mlx5_txq_obj tmpl;\n+\tstruct mlx5_txq_obj *txq_obj = NULL;\n \tunion {\n \t\tstruct ibv_qp_init_attr_ex init;\n \t\tstruct ibv_cq_init_attr_ex cq;\n@@ -411,7 +411,7 @@ struct mlx5_txq_ibv *\n \t\trte_errno = EINVAL;\n \t\treturn NULL;\n \t}\n-\tmemset(&tmpl, 0, sizeof(struct mlx5_txq_ibv));\n+\tmemset(&tmpl, 0, sizeof(struct mlx5_txq_obj));\n \tattr.cq = (struct ibv_cq_init_attr_ex){\n \t\t.comp_mask = 0,\n \t};\n@@ -502,9 +502,9 @@ struct mlx5_txq_ibv *\n \t\trte_errno = errno;\n \t\tgoto error;\n \t}\n-\ttxq_ibv = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_ibv), 0,\n+\ttxq_obj = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_txq_obj), 0,\n \t\t\t\t txq_ctrl->socket);\n-\tif (!txq_ibv) {\n+\tif (!txq_obj) {\n \t\tDRV_LOG(ERR, \"port %u Tx queue %u cannot allocate memory\",\n \t\t\tdev->data->port_id, idx);\n \t\trte_errno = ENOMEM;\n@@ -568,9 +568,9 @@ struct mlx5_txq_ibv *\n \t\t}\n \t}\n #endif\n-\ttxq_ibv->qp = tmpl.qp;\n-\ttxq_ibv->cq = tmpl.cq;\n-\trte_atomic32_inc(&txq_ibv->refcnt);\n+\ttxq_obj->qp = tmpl.qp;\n+\ttxq_obj->cq = tmpl.cq;\n+\trte_atomic32_inc(&txq_obj->refcnt);\n \ttxq_ctrl->bf_reg = qp.bf.reg;\n \tif (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {\n \t\ttxq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;\n@@ -585,18 +585,18 @@ struct mlx5_txq_ibv *\n \t\tgoto error;\n \t}\n \ttxq_uar_init(txq_ctrl);\n-\tLIST_INSERT_HEAD(&priv->txqsibv, txq_ibv, next);\n-\ttxq_ibv->txq_ctrl = txq_ctrl;\n+\tLIST_INSERT_HEAD(&priv->txqsobj, txq_obj, next);\n+\ttxq_obj->txq_ctrl = txq_ctrl;\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n-\treturn txq_ibv;\n+\treturn txq_obj;\n error:\n \tret = rte_errno; /* Save rte_errno before cleanup. */\n \tif (tmpl.cq)\n \t\tclaim_zero(mlx5_glue->destroy_cq(tmpl.cq));\n \tif (tmpl.qp)\n \t\tclaim_zero(mlx5_glue->destroy_qp(tmpl.qp));\n-\tif (txq_ibv)\n-\t\trte_free(txq_ibv);\n+\tif (txq_obj)\n+\t\trte_free(txq_obj);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;\n \trte_errno = ret; /* Restore rte_errno. */\n \treturn NULL;\n@@ -613,8 +613,8 @@ struct mlx5_txq_ibv *\n * @return\n * The Verbs object if it exists.\n */\n-struct mlx5_txq_ibv *\n-mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)\n+struct mlx5_txq_obj *\n+mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_txq_ctrl *txq_ctrl;\n@@ -624,29 +624,29 @@ struct mlx5_txq_ibv *\n \tif (!(*priv->txqs)[idx])\n \t\treturn NULL;\n \ttxq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);\n-\tif (txq_ctrl->ibv)\n-\t\trte_atomic32_inc(&txq_ctrl->ibv->refcnt);\n-\treturn txq_ctrl->ibv;\n+\tif (txq_ctrl->obj)\n+\t\trte_atomic32_inc(&txq_ctrl->obj->refcnt);\n+\treturn txq_ctrl->obj;\n }\n \n /**\n * Release an Tx verbs queue object.\n *\n- * @param txq_ibv\n+ * @param txq_obj\n * Verbs Tx queue object.\n *\n * @return\n * 1 while a reference on it exists, 0 when freed.\n */\n int\n-mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv)\n+mlx5_txq_obj_release(struct mlx5_txq_obj *txq_obj)\n {\n-\tassert(txq_ibv);\n-\tif (rte_atomic32_dec_and_test(&txq_ibv->refcnt)) {\n-\t\tclaim_zero(mlx5_glue->destroy_qp(txq_ibv->qp));\n-\t\tclaim_zero(mlx5_glue->destroy_cq(txq_ibv->cq));\n-\t\tLIST_REMOVE(txq_ibv, next);\n-\t\trte_free(txq_ibv);\n+\tassert(txq_obj);\n+\tif (rte_atomic32_dec_and_test(&txq_obj->refcnt)) {\n+\t\tclaim_zero(mlx5_glue->destroy_qp(txq_obj->qp));\n+\t\tclaim_zero(mlx5_glue->destroy_cq(txq_obj->cq));\n+\t\tLIST_REMOVE(txq_obj, next);\n+\t\trte_free(txq_obj);\n \t\treturn 0;\n \t}\n \treturn 1;\n@@ -662,15 +662,15 @@ struct mlx5_txq_ibv *\n * The number of object not released.\n */\n int\n-mlx5_txq_ibv_verify(struct rte_eth_dev *dev)\n+mlx5_txq_obj_verify(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tint ret = 0;\n-\tstruct mlx5_txq_ibv *txq_ibv;\n+\tstruct mlx5_txq_obj *txq_obj;\n \n-\tLIST_FOREACH(txq_ibv, &priv->txqsibv, next) {\n+\tLIST_FOREACH(txq_obj, &priv->txqsobj, next) {\n \t\tDRV_LOG(DEBUG, \"port %u Verbs Tx queue %u still referenced\",\n-\t\t\tdev->data->port_id, txq_ibv->txq_ctrl->txq.idx);\n+\t\t\tdev->data->port_id, txq_obj->txq_ctrl->txq.idx);\n \t\t++ret;\n \t}\n \treturn ret;\n@@ -1127,7 +1127,7 @@ struct mlx5_txq_ctrl *\n \tif ((*priv->txqs)[idx]) {\n \t\tctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl,\n \t\t\t\t txq);\n-\t\tmlx5_txq_ibv_get(dev, idx);\n+\t\tmlx5_txq_obj_get(dev, idx);\n \t\trte_atomic32_inc(&ctrl->refcnt);\n \t}\n \treturn ctrl;\n@@ -1153,8 +1153,8 @@ struct mlx5_txq_ctrl *\n \tif (!(*priv->txqs)[idx])\n \t\treturn 0;\n \ttxq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);\n-\tif (txq->ibv && !mlx5_txq_ibv_release(txq->ibv))\n-\t\ttxq->ibv = NULL;\n+\tif (txq->obj && !mlx5_txq_obj_release(txq->obj))\n+\t\ttxq->obj = NULL;\n \tif (rte_atomic32_dec_and_test(&txq->refcnt)) {\n \t\ttxq_free_elts(txq);\n \t\tmlx5_mr_btree_free(&txq->txq.mr_ctrl.cache_bh);\n", "prefixes": [ "v3", "04/14" ] }