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GET /api/patches/60823/?format=api
{ "id": 60823, "url": "http://patches.dpdk.org/api/patches/60823/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191009152006.5768-4-harry.van.haaren@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191009152006.5768-4-harry.van.haaren@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191009152006.5768-4-harry.van.haaren@intel.com", "date": "2019-10-09T15:20:06", "name": "[v2,3/3] net/i40e: add flow director support to avx rx path", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6b72234c412d799c891ea6d0131fa2fdbcdc5d00", "submitter": { "id": 317, "url": "http://patches.dpdk.org/api/people/317/?format=api", "name": "Van Haaren, Harry", "email": "harry.van.haaren@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191009152006.5768-4-harry.van.haaren@intel.com/mbox/", "series": [ { "id": 6770, "url": "http://patches.dpdk.org/api/series/6770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6770", "date": "2019-10-09T15:20:03", "name": "net/i40e: add FDIR ID to vector rx", "version": 2, "mbox": "http://patches.dpdk.org/series/6770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/60823/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/60823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3673C1E959;\n\tWed, 9 Oct 2019 17:20:53 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id DD6861E93C\n\tfor <dev@dpdk.org>; Wed, 9 Oct 2019 17:20:46 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t09 Oct 2019 08:20:46 -0700", "from silpixa00399779.ir.intel.com (HELO\n\tsilpixa00399779.ger.corp.intel.com) ([10.237.222.100])\n\tby fmsmga004.fm.intel.com with ESMTP; 09 Oct 2019 08:20:45 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.67,276,1566889200\"; d=\"scan'208\";a=\"218659809\"", "From": "Harry van Haaren <harry.van.haaren@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, mesut.a.ergin@intel.com,\n\tHarry van Haaren <harry.van.haaren@intel.com>", "Date": "Wed, 9 Oct 2019 16:20:06 +0100", "Message-Id": "<20191009152006.5768-4-harry.van.haaren@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20191009152006.5768-1-harry.van.haaren@intel.com>", "References": "<20191007090731.90073-1-harry.van.haaren@intel.com>\n\t<20191009152006.5768-1-harry.van.haaren@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 3/3] net/i40e: add flow director support to\n\tavx rx path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds FDIR ID support to the AVX2 based recieve\npath routine. Support for both 16B and 32B descriptors is\nimplemented.\n\nSigned-off-by: Harry van Haaren <harry.van.haaren@intel.com>\n\n---\n\nv2:\n- Fixup AVX2 RSS clearing to not pollute register\n---\n drivers/net/i40e/i40e_rxtx_vec_avx2.c | 193 +++++++++++++++++++++++++-\n 1 file changed, 189 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\nindex 6f3278960..53c0d7810 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c\n@@ -137,9 +137,90 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq)\n \tI40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n }\n \n+#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+/* Handles 32B descriptor FDIR ID processing:\n+ * rxdp: recieve descriptor ring, required to load 2nd 16B half of each desc\n+ * rx_pkts: required to store metadata back to mbufs\n+ * pkt_idx: offset into the burst, increments in vector widths\n+ * desc_idx: required to select the correct shift at compile time\n+ */\n+static inline __m256i\n+desc_fdir_processing_32b(volatile union i40e_rx_desc *rxdp,\n+\t\t\t struct rte_mbuf **rx_pkts,\n+\t\t\t const uint32_t pkt_idx,\n+\t\t\t const uint32_t desc_idx)\n+{\n+\t/* 32B desc path: load rxdp.wb.qword2 for EXT_STATUS and FLEXBH_STAT */\n+\t__m128i *rxdp_desc_0 = (void *)(&rxdp[desc_idx + 0].wb.qword2);\n+\t__m128i *rxdp_desc_1 = (void *)(&rxdp[desc_idx + 1].wb.qword2);\n+\tconst __m128i desc_qw2_0 = _mm_load_si128(rxdp_desc_0);\n+\tconst __m128i desc_qw2_1 = _mm_load_si128(rxdp_desc_1);\n+\n+\t/* Mask for FLEXBH_STAT, and the FDIR_ID value to compare against. The\n+\t * remaining data is set to all 1's to pass through data.\n+\t */\n+\tconst __m256i flexbh_mask = _mm256_set_epi32(-1, -1, -1, 3 << 4,\n+\t\t\t\t\t\t -1, -1, -1, 3 << 4);\n+\tconst __m256i flexbh_id = _mm256_set_epi32(-1, -1, -1, 1 << 4,\n+\t\t\t\t\t\t -1, -1, -1, 1 << 4);\n+\n+\t/* Load descriptor, check for FLEXBH bits, generate a mask for both\n+\t * packets in the register.\n+\t */\n+\t__m256i desc_qw2_0_1 =\n+\t\t_mm256_inserti128_si256(_mm256_castsi128_si256(desc_qw2_0),\n+\t\t\t\t\tdesc_qw2_1, 1);\n+\t__m256i desc_tmp_msk = _mm256_and_si256(flexbh_mask, desc_qw2_0_1);\n+\t__m256i fdir_mask = _mm256_cmpeq_epi32(flexbh_id, desc_tmp_msk);\n+\t__m256i fdir_data = _mm256_alignr_epi8(desc_qw2_0_1, desc_qw2_0_1, 12);\n+\t__m256i desc_fdir_data = _mm256_and_si256(fdir_mask, fdir_data);\n+\n+\t/* Write data out to the mbuf. There is no store to this area of the\n+\t * mbuf today, so we cannot combine it with another store.\n+\t */\n+\tconst uint32_t idx_0 = pkt_idx + desc_idx;\n+\tconst uint32_t idx_1 = pkt_idx + desc_idx + 1;\n+\trx_pkts[idx_0]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 0);\n+\trx_pkts[idx_1]->hash.fdir.hi = _mm256_extract_epi32(desc_fdir_data, 4);\n+\n+\t/* Create mbuf flags as required for mbuf_flags layout\n+\t * (That's high lane [1,3,5,7, 0,2,4,6] as u32 lanes).\n+\t * Approach:\n+\t * - Mask away bits not required from the fdir_mask\n+\t * - Leave the PKT_FDIR_ID bit (1 << 13)\n+\t * - Position that bit correctly based on packet number\n+\t * - OR in the resulting bit to mbuf_flags\n+\t */\n+\tRTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));\n+\t__m256i mbuf_flag_mask = _mm256_set_epi32(0, 0, 0, 1 << 13,\n+\t\t\t\t\t\t 0, 0, 0, 1 << 13);\n+\t__m256i desc_flag_bit = _mm256_and_si256(mbuf_flag_mask, fdir_mask);\n+\n+\t/* For static-inline function, this will be stripped out\n+\t * as the desc_idx is a hard-coded constant.\n+\t */\n+\tswitch (desc_idx) {\n+\tcase 0:\n+\t\treturn _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 4);\n+\tcase 2:\n+\t\treturn _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 8);\n+\tcase 4:\n+\t\treturn _mm256_alignr_epi8(desc_flag_bit, desc_flag_bit, 12);\n+\tcase 6:\n+\t\treturn desc_flag_bit;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* NOT REACHED, see above switch returns */\n+\treturn _mm256_setzero_si256();\n+}\n+#endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */\n+\n #define PKTLEN_SHIFT 10\n \n-static inline uint16_t\n+/* Force inline as some compilers will not inline by default. */\n+static __rte_always_inline uint16_t\n _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\tuint16_t nb_pkts, uint8_t *split_packet)\n {\n@@ -419,8 +500,10 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* set vlan and rss flags */\n \t\tconst __m256i vlan_flags = _mm256_shuffle_epi8(\n \t\t\t\tvlan_flags_shuf, flag_bits);\n-\t\tconst __m256i rss_flags = _mm256_shuffle_epi8(\n-\t\t\t\trss_flags_shuf, _mm256_srli_epi32(flag_bits, 11));\n+\t\tconst __m256i rss_fdir_bits = _mm256_srli_epi32(flag_bits, 11);\n+\t\tconst __m256i rss_flags = _mm256_shuffle_epi8(rss_flags_shuf,\n+\t\t\t\t\t\t\t rss_fdir_bits);\n+\n \t\t/*\n \t\t * l3_l4_error flags, shuffle, then shift to correct adjustment\n \t\t * of flags in flags_shuf, and finally mask out extra bits\n@@ -431,8 +514,110 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\tl3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);\n \n \t\t/* merge flags */\n-\t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n+\t\t__m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n \t\t\t\t_mm256_or_si256(rss_flags, vlan_flags));\n+\n+\t\t/* If the rxq has FDIR enabled, read and process the FDIR info\n+\t\t * from the descriptor. This can cause more loads/stores, so is\n+\t\t * not always performed. Branch over the code when not enabled.\n+\t\t */\n+\t\tif (rxq->fdir_enabled) {\n+#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n+\t\t\t/* 16B descriptor code path:\n+\t\t\t * RSS and FDIR ID use the same offset in the desc, so\n+\t\t\t * only one can be present at a time. The code below\n+\t\t\t * identifies an FDIR ID match, and zeros the RSS value\n+\t\t\t * in the mbuf on FDIR match to keep mbuf data clean.\n+\t\t\t */\n+\n+\t\t\t/* Flags:\n+\t\t\t * - Take flags, shift bits to null out\n+\t\t\t * - CMPEQ with known FDIR ID, to get 0xFFFF or 0 mask\n+\t\t\t * - Strip bits from mask, leaving 0 or 1 for FDIR ID\n+\t\t\t * - Merge with mbuf_flags\n+\t\t\t */\n+\t\t\t/* FLM = 1, FLTSTAT = 0b01, (FLM | FLTSTAT) == 3.\n+\t\t\t * Shift left by 28 to avoid having to mask.\n+\t\t\t */\n+\t\t\tconst __m256i fdir = _mm256_slli_epi32(rss_fdir_bits, 28);\n+\t\t\tconst __m256i fdir_id = _mm256_set1_epi32(3 << 28);\n+\n+\t\t\t/* As above, the fdir_mask to packet mapping is this:\n+\t\t\t * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]\n+\t\t\t * Then OR FDIR flags to mbuf_flags on FDIR ID hit.\n+\t\t\t */\n+\t\t\tRTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));\n+\t\t\tconst __m256i pkt_fdir_bit = _mm256_set1_epi32(1 << 13);\n+\t\t\tconst __m256i fdir_mask = _mm256_cmpeq_epi32(fdir, fdir_id);\n+\t\t\t__m256i fdir_bits = _mm256_and_si256(fdir_mask, pkt_fdir_bit);\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_bits);\n+\n+\t\t\t/* Based on FDIR_MASK, clear the RSS or FDIR value.\n+\t\t\t * The FDIR ID value is masked to zero if not a hit,\n+\t\t\t * otherwise the mb0_1 register RSS field is zeroed.\n+\t\t\t */\n+\t\t\tconst __m256i fdir_zero_mask = _mm256_setzero_si256();\n+\t\t\tconst uint32_t fdir_blend_mask = (1 << 3) | (1 << 7);\n+\t\t\t__m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask,\n+\t\t\t\t\t\tfdir_mask, fdir_blend_mask);\n+\t\t\t__m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask);\n+\t\t\tmb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1);\n+\n+\t\t\t/* Write to mbuf: no stores to combine with, so just a\n+\t\t\t * scalar store to push data here.\n+\t\t\t */\n+\t\t\trx_pkts[i + 0]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb0_1, 3);\n+\t\t\trx_pkts[i + 1]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb0_1, 7);\n+\n+\t\t\t/* Same as above, only shift the fdir_mask to align\n+\t\t\t * the packet FDIR mask with the FDIR_ID desc lane.\n+\t\t\t */\n+\t\t\t__m256i tmp2_3 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 12);\n+\t\t\t__m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3);\n+\t\t\ttmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3,\n+\t\t\t\t\t\t fdir_blend_mask);\n+\t\t\tmb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3);\n+\t\t\trx_pkts[i + 2]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 3);\n+\t\t\trx_pkts[i + 3]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 7);\n+\n+\t\t\t__m256i tmp4_5 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 8);\n+\t\t\t__m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5);\n+\t\t\ttmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5,\n+\t\t\t\t\t\t fdir_blend_mask);\n+\t\t\tmb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5);\n+\t\t\trx_pkts[i + 4]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 3);\n+\t\t\trx_pkts[i + 5]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 7);\n+\n+\t\t\t__m256i tmp6_7 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 4);\n+\t\t\t__m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7);\n+\t\t\ttmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7,\n+\t\t\t\t\t\t fdir_blend_mask);\n+\t\t\tmb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7);\n+\t\t\trx_pkts[i + 6]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 3);\n+\t\t\trx_pkts[i + 7]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 7);\n+\n+\t\t\t/* End of 16B descriptor handling */\n+#else\n+\t\t\t/* 32B descriptor FDIR ID mark handling. Returns bits\n+\t\t\t * to be OR-ed into the mbuf olflags.\n+\t\t\t */\n+\t\t\t__m256i fdir_add_flags;\n+\t\t\tfdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 0);\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);\n+\n+\t\t\tfdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 2);\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);\n+\n+\t\t\tfdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 4);\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);\n+\n+\t\t\tfdir_add_flags = desc_fdir_processing_32b(rxdp, rx_pkts, i, 6);\n+\t\t\tmbuf_flags = _mm256_or_si256(mbuf_flags, fdir_add_flags);\n+\t\t\t/* End 32B desc handling */\n+#endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */\n+\n+\t\t} /* if() on FDIR enabled */\n+\n \t\t/*\n \t\t * At this point, we have the 8 sets of flags in the low 16-bits\n \t\t * of each 32-bit value in vlan0.\n", "prefixes": [ "v2", "3/3" ] }