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GET /api/patches/60376/?format=api
{ "id": 60376, "url": "http://patches.dpdk.org/api/patches/60376/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191002012335.85324-2-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191002012335.85324-2-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191002012335.85324-2-ajit.khaparde@broadcom.com", "date": "2019-10-02T01:23:21", "name": "[v3,01/15] net/bnxt: add FW reset HWRM command", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bb4fe89475f5c353564f84a51ba684e4c2c8da19", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191002012335.85324-2-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 6660, "url": "http://patches.dpdk.org/api/series/6660/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6660", "date": "2019-10-02T01:23:24", "name": "bnxt patchset to support device error recovery", "version": 3, "mbox": "http://patches.dpdk.org/series/6660/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/60376/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/60376/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BE3B71BE8A;\n\tWed, 2 Oct 2019 03:23:53 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (unknown [192.19.229.170])\n\tby dpdk.org (Postfix) with ESMTP id BC6041B203\n\tfor <dev@dpdk.org>; Wed, 2 Oct 2019 03:23:46 +0200 (CEST)", "from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net\n\t[10.75.242.48])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 8468230CC49;\n\tTue, 1 Oct 2019 18:22:29 -0700 (PDT)", "from localhost.localdomain (unknown [10.230.30.225])\n\tby mail-irv-17.broadcom.com (Postfix) with ESMTP id 1292C14008C;\n\tTue, 1 Oct 2019 18:23:39 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 8468230CC49", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1569979349;\n\tbh=vfwDWEovH4ZT4gESJ/99YM2Y/5JM84x2gwWtUAzF4sk=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=a32mPrmC/yJGfiqftywaGNNs5Fggnv2egCy8yZe4wlKDbcyf4J5Fu+RLNCaAD3daS\n\t7BMsOW+Ft0JcVmsuWMQFqZeeDhlGMYkjjFmifPE+J3txloY6vhmXnJ0I9e6THhYUOx\n\treIV+ZEVxAVtRF/638lIhaSByf2w1UqUKhh/I34o=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, Kalesh AP <kalesh-anakkur.purayil@broadcom.com>, \n\tSomnath Kotur <somnath.kotur@broadcom.com>", "Date": "Tue, 1 Oct 2019 18:23:21 -0700", "Message-Id": "<20191002012335.85324-2-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.20.1 (Apple Git-117)", "In-Reply-To": "<20191002012335.85324-1-ajit.khaparde@broadcom.com>", "References": "<7c08999f-13f3-5fb6-39a2-557a0884bfde@intel.com>\n\t<20191002012335.85324-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 01/15] net/bnxt: add FW reset HWRM command", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\n\nThis patch adds new FW reset HWRM command.\nCode using this command will be added in future patch.\n\nSigned-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\nReviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 137 +++++++++++++++++++++++++\n 1 file changed, 137 insertions(+)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 6c98c1d6dd..0095717254 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -33621,4 +33621,141 @@ struct hwrm_nvm_validate_option_cmd_err {\n \tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n+/*****************\n+ * hwrm_fw_reset *\n+ ******************/\n+\n+\n+/* hwrm_fw_reset_input (size:192b/24B) */\n+struct hwrm_fw_reset_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t req_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t cmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t seq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t target_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t resp_addr;\n+\t/* Type of embedded processor. */\n+\tuint8_t embedded_proc_type;\n+\t/* Boot Processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \\\n+\t\tUINT32_C(0x0)\n+\t/* Management Processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \\\n+\t\tUINT32_C(0x1)\n+\t/* Network control processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \\\n+\t\tUINT32_C(0x2)\n+\t/* RoCE control processor */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \\\n+\t\tUINT32_C(0x3)\n+\t/*\n+\t * Host (in multi-host environment): This is only valid if requester is IPC.\n+\t * Reinit host hardware resources and PCIe.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \\\n+\t\tUINT32_C(0x4)\n+\t/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \\\n+\t\tUINT32_C(0x5)\n+\t/* Reset all blocks of the chip (including all processors) */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \\\n+\t\tUINT32_C(0x6)\n+\t/*\n+\t * Host (in multi-host environment): This is only valid if requester is IPC.\n+\t * Reinit host hardware resources.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \\\n+\t\tUINT32_C(0x7)\n+\t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \\\n+\t\tHWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT\n+\t/* Type of self reset. */\n+\tuint8_t selfrst_status;\n+\t/* No Self Reset */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Self Reset as soon as possible to do so safely */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \\\n+\t\tUINT32_C(0x1)\n+\t/* Self Reset on PCIe Reset */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n+\t\tUINT32_C(0x2)\n+\t/* Self Reset immediately after notification to all clients. */\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \\\n+\t\tHWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n+\t/*\n+\t * Indicate which host is being reset. 0 means first host.\n+\t * Only valid when embedded_proc_type is host in multihost\n+\t * environment\n+\t */\n+\tuint8_t host_idx;\n+\tuint8_t flags;\n+\t/*\n+\t * When this bit is '1', then the core firmware initiates\n+\t * the reset only after graceful shut down of all registered instances.\n+\t * If not, the device will continue with the existing firmware.\n+\t */\n+\t#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)\n+\tuint8_t unused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_fw_reset_output (size:128b/16B) */\n+struct hwrm_fw_reset_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t error_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t req_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t seq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t resp_len;\n+\t/* Type of self reset. */\n+\tuint8_t selfrst_status;\n+\t/* No Self Reset */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Self Reset as soon as possible to do so safely */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \\\n+\t\tUINT32_C(0x1)\n+\t/* Self Reset on PCIe Reset */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \\\n+\t\tUINT32_C(0x2)\n+\t/* Self Reset immediately after notification to all clients. */\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \\\n+\t\tHWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE\n+\tuint8_t unused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t valid;\n+} __attribute__((packed));\n+\n #endif /* _HSI_STRUCT_DEF_DPDK_H_ */\n", "prefixes": [ "v3", "01/15" ] }