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GET /api/patches/60319/?format=api
{ "id": 60319, "url": "http://patches.dpdk.org/api/patches/60319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191001110209.6047-9-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191001110209.6047-9-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191001110209.6047-9-g.singh@nxp.com", "date": "2019-10-01T11:02:03", "name": "[v3,08/14] net/ppfe: add queue setup and release operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8ec510a7a26d46b906e22e7749f7ff2fbbbbb748", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191001110209.6047-9-g.singh@nxp.com/mbox/", "series": [ { "id": 6647, "url": "http://patches.dpdk.org/api/series/6647/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6647", "date": "2019-10-01T11:01:55", "name": "introduces ppfe network PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/6647/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/60319/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/60319/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4FA261BEB0;\n\tTue, 1 Oct 2019 13:17:43 +0200 (CEST)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby dpdk.org (Postfix) with ESMTP id 33E581BE3D\n\tfor <dev@dpdk.org>; Tue, 1 Oct 2019 13:17:34 +0200 (CEST)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0E0C91A02BC;\n\tTue, 1 Oct 2019 13:17:34 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A61471A0096;\n\tTue, 1 Oct 2019 13:17:31 +0200 (CEST)", "from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 2878C4029A;\n\tTue, 1 Oct 2019 19:17:28 +0800 (SGT)" ], "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "dev@dpdk.org,\n\tferruh.yigit@intel.com", "Cc": "thomas@monjalon.net,\n\tGagandeep Singh <g.singh@nxp.com>", "Date": "Tue, 1 Oct 2019 16:32:03 +0530", "Message-Id": "<20191001110209.6047-9-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20191001110209.6047-1-g.singh@nxp.com>", "References": "<20190826130246.30485-1-g.singh@nxp.com>\n\t<20191001110209.6047-1-g.singh@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[dpdk-dev] [PATCH v3 08/14] net/ppfe: add queue setup and release\n\toperations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch add RX/TX queue setup operations\nand supported checksum offloads.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\nAcked-by: Nipun Gupta <nipun.gupta@nxp.com>\nAcked-by: Akhil Goyal <akhil.goyal@nxp.com>\n---\n doc/guides/nics/features/ppfe.ini | 2 +\n doc/guides/nics/ppfe.rst | 1 +\n drivers/net/ppfe/pfe_hif.c | 115 ++++++++++++++++++++++++++++++\n drivers/net/ppfe/pfe_hif.h | 1 +\n drivers/net/ppfe/pfe_hif_lib.c | 50 +++++++++++++\n drivers/net/ppfe/ppfe_ethdev.c | 93 ++++++++++++++++++++++++\n 6 files changed, 262 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/ppfe.ini b/doc/guides/nics/features/ppfe.ini\nindex cd5f836a3..4e38ffd24 100644\n--- a/doc/guides/nics/features/ppfe.ini\n+++ b/doc/guides/nics/features/ppfe.ini\n@@ -4,6 +4,8 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n Linux VFIO = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/doc/guides/nics/ppfe.rst b/doc/guides/nics/ppfe.rst\nindex 29b02957f..c95525e5b 100644\n--- a/doc/guides/nics/ppfe.rst\n+++ b/doc/guides/nics/ppfe.rst\n@@ -93,6 +93,7 @@ the kernel layer for link status.\n PPFE Features\n ~~~~~~~~~~~~~~\n \n+- L3/L4 checksum offload\n - ARMv8\n \n Supported PPFE SoCs\ndiff --git a/drivers/net/ppfe/pfe_hif.c b/drivers/net/ppfe/pfe_hif.c\nindex 940f7419f..024ca3d77 100644\n--- a/drivers/net/ppfe/pfe_hif.c\n+++ b/drivers/net/ppfe/pfe_hif.c\n@@ -43,6 +43,121 @@ pfe_hif_free_descr(struct pfe_hif *hif)\n \trte_free(hif->descr_baseaddr_v);\n }\n \n+/*\n+ * pfe_hif_init_buffers\n+ * This function initializes the HIF Rx/Tx ring descriptors and\n+ * initialize Rx queue with buffers.\n+ */\n+int\n+pfe_hif_init_buffers(struct pfe_hif *hif)\n+{\n+\tstruct hif_desc\t*desc, *first_desc_p;\n+\tuint32_t i = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Check enough Rx buffers available in the shared memory */\n+\tif (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size)\n+\t\treturn -ENOMEM;\n+\n+\thif->rx_base = hif->descr_baseaddr_v;\n+\tmemset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc));\n+\n+\t/*Initialize Rx descriptors */\n+\tdesc = hif->rx_base;\n+\tfirst_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;\n+\n+\tfor (i = 0; i < hif->rx_ring_size; i++) {\n+\t\t/* Initialize Rx buffers from the shared memory */\n+\t\tstruct rte_mbuf *mbuf =\n+\t\t\t(struct rte_mbuf *)hif->shm->rx_buf_pool[i];\n+\n+\t\t/* PPFE mbuf structure is as follow:\n+\t\t * ----------------------------------------------------------+\n+\t\t * | mbuf | priv | headroom (annotation + PPFE data) | data |\n+\t\t * ----------------------------------------------------------+\n+\t\t *\n+\t\t * As we are expecting additional information like parse\n+\t\t * results, eth id, queue id from PPFE block along with data.\n+\t\t * so we have to provide additional memory for each packet to\n+\t\t * HIF rx rings so that PPFE block can write its headers.\n+\t\t * so, we are giving the data pointor to HIF rings whose\n+\t\t * calculation is as below:\n+\t\t * mbuf->data_pointor - Required_header_size\n+\t\t *\n+\t\t * We are utilizing the HEADROOM area to receive the PPFE\n+\t\t * block headers. On packet reception, HIF driver will use\n+\t\t * PPFE headers information based on which it will decide\n+\t\t * the clients and fill the parse results.\n+\t\t * after that application can use/overwrite the HEADROOM area.\n+\t\t */\n+\t\thif->rx_buf_vaddr[i] =\n+\t\t\t(void *)((size_t)mbuf->buf_addr + mbuf->data_off -\n+\t\t\t\t\tPFE_PKT_HEADER_SZ);\n+\t\thif->rx_buf_addr[i] =\n+\t\t\t(void *)(size_t)(rte_pktmbuf_iova(mbuf) -\n+\t\t\t\t\tPFE_PKT_HEADER_SZ);\n+\t\thif->rx_buf_len[i] = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;\n+\n+\t\thif->shm->rx_buf_pool[i] = NULL;\n+\n+\t\twritel(DDR_PHYS_TO_PFE(hif->rx_buf_addr[i]),\n+\t\t\t\t\t&desc->data);\n+\t\twritel(0, &desc->status);\n+\n+\t\t/*\n+\t\t * Ensure everything else is written to DDR before\n+\t\t * writing bd->ctrl\n+\t\t */\n+\t\trte_wmb();\n+\n+\t\twritel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM\n+\t\t\t| BD_CTRL_DIR | BD_CTRL_DESC_EN\n+\t\t\t| BD_BUF_LEN(hif->rx_buf_len[i])), &desc->ctrl);\n+\n+\t\t/* Chain descriptors */\n+\t\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);\n+\t\tdesc++;\n+\t}\n+\n+\t/* Overwrite last descriptor to chain it to first one*/\n+\tdesc--;\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);\n+\n+\thif->rxtoclean_index = 0;\n+\n+\t/*Initialize Rx buffer descriptor ring base address */\n+\twritel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);\n+\n+\thif->tx_base = hif->rx_base + hif->rx_ring_size;\n+\tfirst_desc_p = (struct hif_desc *)hif->descr_baseaddr_p +\n+\t\t\t\thif->rx_ring_size;\n+\tmemset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc));\n+\n+\t/*Initialize tx descriptors */\n+\tdesc = hif->tx_base;\n+\n+\tfor (i = 0; i < hif->tx_ring_size; i++) {\n+\t\t/* Chain descriptors */\n+\t\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);\n+\t\twritel(0, &desc->ctrl);\n+\t\tdesc++;\n+\t}\n+\n+\t/* Overwrite last descriptor to chain it to first one */\n+\tdesc--;\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);\n+\thif->txavail = hif->tx_ring_size;\n+\thif->txtosend = 0;\n+\thif->txtoclean = 0;\n+\thif->txtoflush = 0;\n+\n+\t/*Initialize Tx buffer descriptor ring base address */\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);\n+\n+\treturn 0;\n+}\n+\n /*\n * pfe_hif_client_register\n *\ndiff --git a/drivers/net/ppfe/pfe_hif.h b/drivers/net/ppfe/pfe_hif.h\nindex 483db75da..80f78551c 100644\n--- a/drivers/net/ppfe/pfe_hif.h\n+++ b/drivers/net/ppfe/pfe_hif.h\n@@ -143,5 +143,6 @@ void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int\n int pfe_hif_init(struct pfe *pfe);\n void pfe_hif_exit(struct pfe *pfe);\n void pfe_hif_rx_idle(struct pfe_hif *hif);\n+int pfe_hif_init_buffers(struct pfe_hif *hif);\n \n #endif /* _PFE_HIF_H_ */\ndiff --git a/drivers/net/ppfe/pfe_hif_lib.c b/drivers/net/ppfe/pfe_hif_lib.c\nindex 2012d896a..f5e290f27 100644\n--- a/drivers/net/ppfe/pfe_hif_lib.c\n+++ b/drivers/net/ppfe/pfe_hif_lib.c\n@@ -15,6 +15,56 @@ unsigned int emac_txq_cnt;\n /*HIF shared memory Global variable */\n struct hif_shm ghif_shm;\n \n+/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.\n+ * This function should be called after pfe_hif_exit\n+ *\n+ * @param[in] hif_shm\t\tShared memory address location in DDR\n+ */\n+void\n+pfe_hif_shm_clean(struct hif_shm *hif_shm)\n+{\n+\tunsigned int i;\n+\tvoid *pkt;\n+\n+\tfor (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {\n+\t\tpkt = hif_shm->rx_buf_pool[i];\n+\t\tif (pkt)\n+\t\t\trte_pktmbuf_free((struct rte_mbuf *)pkt);\n+\t}\n+}\n+\n+/* Initialize shared memory used between HIF driver and clients,\n+ * allocate rx_buffer_pool required for HIF Rx descriptors.\n+ * This function should be called before initializing HIF driver.\n+ *\n+ * @param[in] hif_shm\t\tShared memory address location in DDR\n+ * @rerurn\t\t\t0 - on succes, <0 on fail to initialize\n+ */\n+int\n+pfe_hif_shm_init(struct hif_shm *hif_shm, struct rte_mempool *mb_pool)\n+{\n+\tunsigned int i;\n+\tstruct rte_mbuf *mbuf;\n+\n+\tmemset(hif_shm, 0, sizeof(struct hif_shm));\n+\thif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;\n+\n+\tfor (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {\n+\t\tmbuf = rte_cpu_to_le_64(rte_pktmbuf_alloc(mb_pool));\n+\t\tif (mbuf)\n+\t\t\thif_shm->rx_buf_pool[i] = mbuf;\n+\t\telse\n+\t\t\tgoto err0;\n+\t}\n+\n+\treturn 0;\n+\n+err0:\n+\tPFE_PMD_ERR(\"Low memory\");\n+\tpfe_hif_shm_clean(hif_shm);\n+\treturn -ENOMEM;\n+}\n+\n /*This function sends indication to HIF driver\n *\n * @param[in] hif\thif context\ndiff --git a/drivers/net/ppfe/ppfe_ethdev.c b/drivers/net/ppfe/ppfe_ethdev.c\nindex 19467b90d..4619a9d28 100644\n--- a/drivers/net/ppfe/ppfe_ethdev.c\n+++ b/drivers/net/ppfe/ppfe_ethdev.c\n@@ -17,6 +17,17 @@ struct pfe_vdev_init_params {\n \tint8_t\tgem_id;\n };\n static struct pfe *g_pfe;\n+/* Supported Rx offloads */\n+static uint64_t dev_rx_offloads_sup =\n+\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n+\n+/* Supported Tx offloads */\n+static uint64_t dev_tx_offloads_sup =\n+\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\tDEV_TX_OFFLOAD_TCP_CKSUM;\n \n /* TODO: make pfe_svr a runtime option.\n * Driver should be able to get the SVR\n@@ -285,16 +296,98 @@ pfe_eth_info(struct rte_eth_dev *dev,\n \tdev_info->max_rx_queues = dev->data->nb_rx_queues;\n \tdev_info->max_tx_queues = dev->data->nb_tx_queues;\n \tdev_info->min_rx_bufsize = HIF_RX_PKT_MIN_SIZE;\n+\tdev_info->rx_offload_capa = dev_rx_offloads_sup;\n+\tdev_info->tx_offload_capa = dev_tx_offloads_sup;\n \n \treturn 0;\n }\n \n+/* Only first mb_pool given on first call of this API will be used\n+ * in whole system, also nb_rx_desc and rx_conf are unused params\n+ */\n+static int\n+pfe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t__rte_unused uint16_t nb_rx_desc,\n+\t\t__rte_unused unsigned int socket_id,\n+\t\t__rte_unused const struct rte_eth_rxconf *rx_conf,\n+\t\tstruct rte_mempool *mb_pool)\n+{\n+\tint rc = 0;\n+\tstruct pfe *pfe;\n+\tstruct pfe_eth_priv_s *priv = dev->data->dev_private;\n+\n+\tpfe = priv->pfe;\n+\n+\tif (queue_idx >= EMAC_RXQ_CNT) {\n+\t\tPFE_PMD_ERR(\"Invalid queue idx = %d, Max queues = %d\",\n+\t\t\t\tqueue_idx, EMAC_RXQ_CNT);\n+\t\treturn -1;\n+\t}\n+\n+\tif (!pfe->hif.setuped) {\n+\t\trc = pfe_hif_shm_init(pfe->hif.shm, mb_pool);\n+\t\tif (rc) {\n+\t\t\tPFE_PMD_ERR(\"Could not allocate buffer descriptors\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tpfe->hif.shm->pool = mb_pool;\n+\t\tif (pfe_hif_init_buffers(&pfe->hif)) {\n+\t\t\tPFE_PMD_ERR(\"Could not initialize buffer descriptors\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\thif_init();\n+\t\thif_rx_enable();\n+\t\thif_tx_enable();\n+\t\tpfe->hif.setuped = 1;\n+\t}\n+\tdev->data->rx_queues[queue_idx] = &priv->client.rx_q[queue_idx];\n+\tpriv->client.rx_q[queue_idx].queue_id = queue_idx;\n+\n+\treturn 0;\n+}\n+\n+static void\n+pfe_rx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static void\n+pfe_tx_queue_release(void *q __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+static int\n+pfe_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t uint16_t queue_idx,\n+\t\t __rte_unused uint16_t nb_desc,\n+\t\t __rte_unused unsigned int socket_id,\n+\t\t __rte_unused const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct pfe_eth_priv_s *priv = dev->data->dev_private;\n+\n+\tif (queue_idx >= emac_txq_cnt) {\n+\t\tPFE_PMD_ERR(\"Invalid queue idx = %d, Max queues = %d\",\n+\t\t\t\tqueue_idx, emac_txq_cnt);\n+\t\treturn -1;\n+\t}\n+\tdev->data->tx_queues[queue_idx] = &priv->client.tx_q[queue_idx];\n+\tpriv->client.tx_q[queue_idx].queue_id = queue_idx;\n+\treturn 0;\n+}\n+\n static const struct eth_dev_ops ops = {\n \t.dev_start = pfe_eth_open,\n \t.dev_stop = pfe_eth_stop,\n \t.dev_close = pfe_eth_close,\n \t.dev_configure = pfe_eth_configure,\n \t.dev_infos_get = pfe_eth_info,\n+\t.rx_queue_setup = pfe_rx_queue_setup,\n+\t.rx_queue_release = pfe_rx_queue_release,\n+\t.tx_queue_setup = pfe_tx_queue_setup,\n+\t.tx_queue_release = pfe_tx_queue_release,\n };\n \n static int\n", "prefixes": [ "v3", "08/14" ] }