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{
    "id": 60316,
    "url": "http://patches.dpdk.org/api/patches/60316/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191001110209.6047-6-g.singh@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191001110209.6047-6-g.singh@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191001110209.6047-6-g.singh@nxp.com",
    "date": "2019-10-01T11:02:00",
    "name": "[v3,05/14] net/ppfe: add HW specific macros and operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b6bd055d2114359d19e88fc2358425308f0399ef",
    "submitter": {
        "id": 1068,
        "url": "http://patches.dpdk.org/api/people/1068/?format=api",
        "name": "Gagandeep Singh",
        "email": "g.singh@nxp.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191001110209.6047-6-g.singh@nxp.com/mbox/",
    "series": [
        {
            "id": 6647,
            "url": "http://patches.dpdk.org/api/series/6647/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6647",
            "date": "2019-10-01T11:01:55",
            "name": "introduces ppfe network PMD",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/6647/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/60316/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/60316/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 371F01BE86;\n\tTue,  1 Oct 2019 13:17:37 +0200 (CEST)",
            "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby dpdk.org (Postfix) with ESMTP id 9EBA71B948\n\tfor <dev@dpdk.org>; Tue,  1 Oct 2019 13:17:31 +0200 (CEST)",
            "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 79AA51A01DE;\n\tTue,  1 Oct 2019 13:17:31 +0200 (CEST)",
            "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 4C6D11A0096;\n\tTue,  1 Oct 2019 13:17:28 +0200 (CEST)",
            "from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 2096340318;\n\tTue,  1 Oct 2019 19:17:24 +0800 (SGT)"
        ],
        "From": "Gagandeep Singh <g.singh@nxp.com>",
        "To": "dev@dpdk.org,\n\tferruh.yigit@intel.com",
        "Cc": "thomas@monjalon.net, Gagandeep Singh <g.singh@nxp.com>,\n\tAkhil Goyal <akhil.goyal@nxp.com>",
        "Date": "Tue,  1 Oct 2019 16:32:00 +0530",
        "Message-Id": "<20191001110209.6047-6-g.singh@nxp.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20191001110209.6047-1-g.singh@nxp.com>",
        "References": "<20190826130246.30485-1-g.singh@nxp.com>\n\t<20191001110209.6047-1-g.singh@nxp.com>",
        "X-Virus-Scanned": "ClamAV using ClamSMTP",
        "Subject": "[dpdk-dev] [PATCH v3 05/14] net/ppfe: add HW specific macros and\n\toperations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch add some hardware specific macros\nand functions that will be used by the driver.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\nSigned-off-by: Akhil Goyal <akhil.goyal@nxp.com>\nAcked-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/net/ppfe/base/cbus.h           |  66 +++++\n drivers/net/ppfe/base/cbus/bmu.h       |  41 +++\n drivers/net/ppfe/base/cbus/class_csr.h | 277 ++++++++++++++++++++\n drivers/net/ppfe/base/cbus/emac_mtip.h | 231 +++++++++++++++++\n drivers/net/ppfe/base/cbus/gpi.h       |  77 ++++++\n drivers/net/ppfe/base/cbus/hif.h       |  86 +++++++\n drivers/net/ppfe/base/cbus/hif_nocpy.h |  36 +++\n drivers/net/ppfe/base/cbus/tmu_csr.h   | 154 +++++++++++\n drivers/net/ppfe/base/cbus/util_csr.h  |  47 ++++\n drivers/net/ppfe/base/pfe.h            | 339 +++++++++++++++++++++++++\n 10 files changed, 1354 insertions(+)\n create mode 100644 drivers/net/ppfe/base/cbus.h\n create mode 100644 drivers/net/ppfe/base/cbus/bmu.h\n create mode 100644 drivers/net/ppfe/base/cbus/class_csr.h\n create mode 100644 drivers/net/ppfe/base/cbus/emac_mtip.h\n create mode 100644 drivers/net/ppfe/base/cbus/gpi.h\n create mode 100644 drivers/net/ppfe/base/cbus/hif.h\n create mode 100644 drivers/net/ppfe/base/cbus/hif_nocpy.h\n create mode 100644 drivers/net/ppfe/base/cbus/tmu_csr.h\n create mode 100644 drivers/net/ppfe/base/cbus/util_csr.h\n create mode 100644 drivers/net/ppfe/base/pfe.h",
    "diff": "diff --git a/drivers/net/ppfe/base/cbus.h b/drivers/net/ppfe/base/cbus.h\nnew file mode 100644\nindex 000000000..2de2bfa5d\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus.h\n@@ -0,0 +1,66 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _CBUS_H_\n+#define _CBUS_H_\n+\n+#include <compat.h>\n+\n+#define EMAC1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x200000)\n+#define EGPI1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x210000)\n+#define EMAC2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x220000)\n+#define EGPI2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x230000)\n+#define BMU1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x240000)\n+#define BMU2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x250000)\n+#define ARB_BASE_ADDR\t(CBUS_BASE_ADDR + 0x260000)\n+#define DDR_CONFIG_BASE_ADDR\t(CBUS_BASE_ADDR + 0x270000)\n+#define HIF_BASE_ADDR\t(CBUS_BASE_ADDR + 0x280000)\n+#define HGPI_BASE_ADDR\t(CBUS_BASE_ADDR + 0x290000)\n+#define LMEM_BASE_ADDR\t(CBUS_BASE_ADDR + 0x300000)\n+#define LMEM_SIZE\t0x10000\n+#define LMEM_END\t(LMEM_BASE_ADDR + LMEM_SIZE)\n+#define TMU_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x310000)\n+#define CLASS_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x320000)\n+#define HIF_NOCPY_BASE_ADDR\t(CBUS_BASE_ADDR + 0x350000)\n+#define UTIL_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x360000)\n+#define CBUS_GPT_BASE_ADDR\t(CBUS_BASE_ADDR + 0x370000)\n+\n+/*\n+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR\n+ * XXX_MEM_ACCESS_ADDR register bit definitions.\n+ */\n+#define PE_MEM_ACCESS_WRITE\tBIT(31)\t/* Internal Memory Write. */\n+#define PE_MEM_ACCESS_IMEM\tBIT(15)\n+#define PE_MEM_ACCESS_DMEM\tBIT(16)\n+\n+/* Byte Enables of the Internal memory access. These are interpred in BE */\n+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)\t\\\n+\t({ typeof(size) size_ = (size);\t\t\\\n+\t(((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })\n+\n+#include \"cbus/emac_mtip.h\"\n+#include \"cbus/gpi.h\"\n+#include \"cbus/bmu.h\"\n+#include \"cbus/hif.h\"\n+#include \"cbus/tmu_csr.h\"\n+#include \"cbus/class_csr.h\"\n+#include \"cbus/hif_nocpy.h\"\n+#include \"cbus/util_csr.h\"\n+\n+/* PFE cores states */\n+#define CORE_DISABLE\t0x00000000\n+#define CORE_ENABLE\t0x00000001\n+#define CORE_SW_RESET\t0x00000002\n+\n+/* LMEM defines */\n+#define LMEM_HDR_SIZE\t0x0010\n+#define LMEM_BUF_SIZE_LN2\t0x7\n+#define LMEM_BUF_SIZE\tBIT(LMEM_BUF_SIZE_LN2)\n+\n+/* DDR defines */\n+#define DDR_HDR_SIZE\t0x0100\n+#define DDR_BUF_SIZE_LN2\t0xb\n+#define DDR_BUF_SIZE\tBIT(DDR_BUF_SIZE_LN2)\n+\n+#endif /* _CBUS_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/bmu.h b/drivers/net/ppfe/base/cbus/bmu.h\nnew file mode 100644\nindex 000000000..c2a4a2813\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/bmu.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _BMU_H_\n+#define _BMU_H_\n+\n+#define BMU_VERSION\t0x000\n+#define BMU_CTRL\t0x004\n+#define BMU_UCAST_CONFIG\t0x008\n+#define BMU_UCAST_BASE_ADDR\t0x00c\n+#define BMU_BUF_SIZE\t0x010\n+#define BMU_BUF_CNT\t0x014\n+#define BMU_THRES\t0x018\n+#define BMU_INT_SRC\t0x020\n+#define BMU_INT_ENABLE\t0x024\n+#define BMU_ALLOC_CTRL\t0x030\n+#define BMU_FREE_CTRL\t0x034\n+#define BMU_FREE_ERR_ADDR\t0x038\n+#define BMU_CURR_BUF_CNT\t0x03c\n+#define BMU_MCAST_CNT\t0x040\n+#define BMU_MCAST_ALLOC_CTRL\t0x044\n+#define BMU_REM_BUF_CNT\t0x048\n+#define BMU_LOW_WATERMARK\t0x050\n+#define BMU_HIGH_WATERMARK\t0x054\n+#define BMU_INT_MEM_ACCESS\t0x100\n+\n+struct BMU_CFG {\n+\tunsigned long baseaddr;\n+\tu32 count;\n+\tu32 size;\n+\tu32 low_watermark;\n+\tu32 high_watermark;\n+};\n+\n+#define BMU1_BUF_SIZE\tLMEM_BUF_SIZE_LN2\n+#define BMU2_BUF_SIZE\tDDR_BUF_SIZE_LN2\n+\n+#define BMU2_MCAST_ALLOC_CTRL\t(BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)\n+\n+#endif /* _BMU_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/class_csr.h b/drivers/net/ppfe/base/cbus/class_csr.h\nnew file mode 100644\nindex 000000000..70af01a27\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/class_csr.h\n@@ -0,0 +1,277 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _CLASS_CSR_H_\n+#define _CLASS_CSR_H_\n+\n+#include <compat.h>\n+\n+/* @file class_csr.h.\n+ * class_csr - block containing all the classifier control and status register.\n+ * Mapped on CBUS and accessible from all PE's and ARM.\n+ */\n+#define CLASS_VERSION\t(CLASS_CSR_BASE_ADDR + 0x000)\n+#define CLASS_TX_CTRL\t(CLASS_CSR_BASE_ADDR + 0x004)\n+#define CLASS_INQ_PKTPTR\t(CLASS_CSR_BASE_ADDR + 0x010)\n+\n+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */\n+#define CLASS_HDR_SIZE\t(CLASS_CSR_BASE_ADDR + 0x014)\n+\n+/* LMEM header size for the Classifier block.\\ Data in the LMEM\n+ * is written from this offset.\n+ */\n+#define CLASS_HDR_SIZE_LMEM(off)\t((off) & 0x3f)\n+\n+/* DDR header size for the Classifier block.\\ Data in the DDR\n+ * is written from this offset.\n+ */\n+#define CLASS_HDR_SIZE_DDR(off)\t(((off) & 0x1ff) << 16)\n+\n+#define CLASS_PE0_QB_DM_ADDR0\t(CLASS_CSR_BASE_ADDR + 0x020)\n+\n+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */\n+#define CLASS_PE0_QB_DM_ADDR1\t(CLASS_CSR_BASE_ADDR + 0x024)\n+\n+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */\n+#define CLASS_PE0_RO_DM_ADDR0\t(CLASS_CSR_BASE_ADDR + 0x060)\n+\n+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */\n+#define CLASS_PE0_RO_DM_ADDR1\t(CLASS_CSR_BASE_ADDR + 0x064)\n+\n+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */\n+\n+/* @name Class PE memory access. Allows external PE's and HOST to\n+ * read/write PMEM/DMEM memory ranges for each classifier PE.\n+ */\n+/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},\n+ * See \\ref XXX_MEM_ACCESS_ADDR for details.\n+ */\n+#define CLASS_MEM_ACCESS_ADDR\t(CLASS_CSR_BASE_ADDR + 0x100)\n+\n+/* Internal Memory Access Write Data [31:0] */\n+#define CLASS_MEM_ACCESS_WDATA\t(CLASS_CSR_BASE_ADDR + 0x104)\n+\n+/* Internal Memory Access Read Data [31:0] */\n+#define CLASS_MEM_ACCESS_RDATA\t(CLASS_CSR_BASE_ADDR + 0x108)\n+#define CLASS_TM_INQ_ADDR\t(CLASS_CSR_BASE_ADDR + 0x114)\n+#define CLASS_PE_STATUS\t(CLASS_CSR_BASE_ADDR + 0x118)\n+\n+#define CLASS_PHY1_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x11c)\n+#define CLASS_PHY1_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x120)\n+#define CLASS_PHY1_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x124)\n+#define CLASS_PHY1_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x128)\n+#define CLASS_PHY1_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x12c)\n+#define CLASS_PHY1_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x130)\n+#define CLASS_PHY1_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x134)\n+#define CLASS_PHY1_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x138)\n+#define CLASS_PHY1_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x13c)\n+#define CLASS_PHY1_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x140)\n+#define CLASS_PHY2_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x144)\n+#define CLASS_PHY2_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x148)\n+#define CLASS_PHY2_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x14c)\n+#define CLASS_PHY2_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x150)\n+#define CLASS_PHY2_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x154)\n+#define CLASS_PHY2_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x158)\n+#define CLASS_PHY2_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x15c)\n+#define CLASS_PHY2_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x160)\n+#define CLASS_PHY2_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x164)\n+#define CLASS_PHY2_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x168)\n+#define CLASS_PHY3_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x16c)\n+#define CLASS_PHY3_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x170)\n+#define CLASS_PHY3_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x174)\n+#define CLASS_PHY3_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x178)\n+#define CLASS_PHY3_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x17c)\n+#define CLASS_PHY3_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x180)\n+#define CLASS_PHY3_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x184)\n+#define CLASS_PHY3_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x188)\n+#define CLASS_PHY3_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x18c)\n+#define CLASS_PHY3_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x190)\n+#define CLASS_PHY1_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x194)\n+#define CLASS_PHY1_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x198)\n+#define CLASS_PHY1_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x19c)\n+#define CLASS_PHY1_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a0)\n+#define CLASS_PHY2_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a4)\n+#define CLASS_PHY2_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a8)\n+#define CLASS_PHY2_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1ac)\n+#define CLASS_PHY2_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b0)\n+#define CLASS_PHY3_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b4)\n+#define CLASS_PHY3_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b8)\n+#define CLASS_PHY3_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1bc)\n+#define CLASS_PHY3_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c0)\n+#define CLASS_PHY4_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c4)\n+#define CLASS_PHY4_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c8)\n+#define CLASS_PHY4_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1cc)\n+#define CLASS_PHY4_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d0)\n+#define CLASS_PHY4_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d4)\n+#define CLASS_PHY4_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d8)\n+#define CLASS_PHY4_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1dc)\n+#define CLASS_PHY4_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e0)\n+#define CLASS_PHY4_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e4)\n+#define CLASS_PHY4_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e8)\n+#define CLASS_PHY4_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1ec)\n+#define CLASS_PHY4_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f0)\n+#define CLASS_PHY4_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f4)\n+#define CLASS_PHY4_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f8)\n+\n+#define CLASS_PE_SYS_CLK_RATIO\t(CLASS_CSR_BASE_ADDR + 0x200)\n+#define CLASS_AFULL_THRES\t(CLASS_CSR_BASE_ADDR + 0x204)\n+#define CLASS_GAP_BETWEEN_READS\t(CLASS_CSR_BASE_ADDR + 0x208)\n+#define CLASS_MAX_BUF_CNT\t(CLASS_CSR_BASE_ADDR + 0x20c)\n+#define CLASS_TSQ_FIFO_THRES\t(CLASS_CSR_BASE_ADDR + 0x210)\n+#define CLASS_TSQ_MAX_CNT\t(CLASS_CSR_BASE_ADDR + 0x214)\n+#define CLASS_IRAM_DATA_0\t(CLASS_CSR_BASE_ADDR + 0x218)\n+#define CLASS_IRAM_DATA_1\t(CLASS_CSR_BASE_ADDR + 0x21c)\n+#define CLASS_IRAM_DATA_2\t(CLASS_CSR_BASE_ADDR + 0x220)\n+#define CLASS_IRAM_DATA_3\t(CLASS_CSR_BASE_ADDR + 0x224)\n+\n+#define CLASS_BUS_ACCESS_ADDR\t(CLASS_CSR_BASE_ADDR + 0x228)\n+\n+#define CLASS_BUS_ACCESS_WDATA\t(CLASS_CSR_BASE_ADDR + 0x22c)\n+#define CLASS_BUS_ACCESS_RDATA\t(CLASS_CSR_BASE_ADDR + 0x230)\n+\n+/* (route_entry_size[9:0], route_hash_size[23:16]\n+ * (this is actually ln2(size)))\n+ */\n+#define CLASS_ROUTE_HASH_ENTRY_SIZE\t(CLASS_CSR_BASE_ADDR + 0x234)\n+\n+#define CLASS_ROUTE_ENTRY_SIZE(size)\t ((size) & 0x1ff)\n+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)\n+\n+#define CLASS_ROUTE_TABLE_BASE\t(CLASS_CSR_BASE_ADDR + 0x238)\n+\n+#define CLASS_ROUTE_MULTI\t(CLASS_CSR_BASE_ADDR + 0x23c)\n+#define CLASS_SMEM_OFFSET\t(CLASS_CSR_BASE_ADDR + 0x240)\n+#define CLASS_LMEM_BUF_SIZE\t(CLASS_CSR_BASE_ADDR + 0x244)\n+#define CLASS_VLAN_ID\t(CLASS_CSR_BASE_ADDR + 0x248)\n+#define CLASS_BMU1_BUF_FREE\t(CLASS_CSR_BASE_ADDR + 0x24c)\n+#define CLASS_USE_TMU_INQ\t(CLASS_CSR_BASE_ADDR + 0x250)\n+#define CLASS_VLAN_ID1\t(CLASS_CSR_BASE_ADDR + 0x254)\n+\n+#define CLASS_BUS_ACCESS_BASE\t(CLASS_CSR_BASE_ADDR + 0x258)\n+#define CLASS_BUS_ACCESS_BASE_MASK\t(0xFF000000)\n+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */\n+\n+#define CLASS_HIF_PARSE\t(CLASS_CSR_BASE_ADDR + 0x25c)\n+\n+#define CLASS_HOST_PE0_GP\t(CLASS_CSR_BASE_ADDR + 0x260)\n+#define CLASS_PE0_GP\t(CLASS_CSR_BASE_ADDR + 0x264)\n+#define CLASS_HOST_PE1_GP\t(CLASS_CSR_BASE_ADDR + 0x268)\n+#define CLASS_PE1_GP\t(CLASS_CSR_BASE_ADDR + 0x26c)\n+#define CLASS_HOST_PE2_GP\t(CLASS_CSR_BASE_ADDR + 0x270)\n+#define CLASS_PE2_GP\t(CLASS_CSR_BASE_ADDR + 0x274)\n+#define CLASS_HOST_PE3_GP\t(CLASS_CSR_BASE_ADDR + 0x278)\n+#define CLASS_PE3_GP\t(CLASS_CSR_BASE_ADDR + 0x27c)\n+#define CLASS_HOST_PE4_GP\t(CLASS_CSR_BASE_ADDR + 0x280)\n+#define CLASS_PE4_GP\t(CLASS_CSR_BASE_ADDR + 0x284)\n+#define CLASS_HOST_PE5_GP\t(CLASS_CSR_BASE_ADDR + 0x288)\n+#define CLASS_PE5_GP\t(CLASS_CSR_BASE_ADDR + 0x28c)\n+\n+#define CLASS_PE_INT_SRC\t(CLASS_CSR_BASE_ADDR + 0x290)\n+#define CLASS_PE_INT_ENABLE\t(CLASS_CSR_BASE_ADDR + 0x294)\n+\n+#define CLASS_TPID0_TPID1\t(CLASS_CSR_BASE_ADDR + 0x298)\n+#define CLASS_TPID2\t(CLASS_CSR_BASE_ADDR + 0x29c)\n+\n+#define CLASS_L4_CHKSUM_ADDR\t(CLASS_CSR_BASE_ADDR + 0x2a0)\n+\n+#define CLASS_PE0_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2a4)\n+#define CLASS_PE1_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2a8)\n+#define CLASS_PE2_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2ac)\n+#define CLASS_PE3_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b0)\n+#define CLASS_PE4_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b4)\n+#define CLASS_PE5_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b8)\n+\n+#define CLASS_STATE\t(CLASS_CSR_BASE_ADDR + 0x2bc)\n+\n+/* CLASS defines */\n+#define CLASS_PBUF_SIZE\t0x100\t/* Fixed by hardware */\n+#define CLASS_PBUF_HEADER_OFFSET\t0x80\t/* Can be configured */\n+\n+/* Can be configured */\n+#define CLASS_PBUF0_BASE_ADDR\t0x000\n+/* Can be configured */\n+#define CLASS_PBUF1_BASE_ADDR\t(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)\n+/* Can be configured */\n+#define CLASS_PBUF2_BASE_ADDR\t(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)\n+/* Can be configured */\n+#define CLASS_PBUF3_BASE_ADDR\t(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)\n+\n+#define CLASS_PBUF0_HEADER_BASE_ADDR\t(CLASS_PBUF0_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF1_HEADER_BASE_ADDR\t(CLASS_PBUF1_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF2_HEADER_BASE_ADDR\t(CLASS_PBUF2_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF3_HEADER_BASE_ADDR\t(CLASS_PBUF3_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+\n+#define CLASS_PE0_RO_DM_ADDR0_VAL\t((CLASS_PBUF1_BASE_ADDR << 16) | \\\n+\t\t\t\t\t\tCLASS_PBUF0_BASE_ADDR)\n+#define CLASS_PE0_RO_DM_ADDR1_VAL\t((CLASS_PBUF3_BASE_ADDR << 16) | \\\n+\t\t\t\t\t\tCLASS_PBUF2_BASE_ADDR)\n+\n+#define CLASS_PE0_QB_DM_ADDR0_VAL\t((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\\\n+\t\t\t\t\t\tCLASS_PBUF0_HEADER_BASE_ADDR)\n+#define CLASS_PE0_QB_DM_ADDR1_VAL\t((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\\\n+\t\t\t\t\t\tCLASS_PBUF2_HEADER_BASE_ADDR)\n+\n+#define CLASS_ROUTE_SIZE\t128\n+#define CLASS_MAX_ROUTE_SIZE\t256\n+#define CLASS_ROUTE_HASH_BITS\t20\n+#define CLASS_ROUTE_HASH_MASK\t(BIT(CLASS_ROUTE_HASH_BITS) - 1)\n+\n+/* Can be configured */\n+#define\tCLASS_ROUTE0_BASE_ADDR\t0x400\n+/* Can be configured */\n+#define CLASS_ROUTE1_BASE_ADDR\t(CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)\n+/* Can be configured */\n+#define CLASS_ROUTE2_BASE_ADDR\t(CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)\n+/* Can be configured */\n+#define CLASS_ROUTE3_BASE_ADDR\t(CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)\n+\n+#define CLASS_SA_SIZE\t128\n+#define CLASS_IPSEC_SA0_BASE_ADDR\t0x600\n+/* not used */\n+#define CLASS_IPSEC_SA1_BASE_ADDR  (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)\n+/* not used */\n+#define CLASS_IPSEC_SA2_BASE_ADDR  (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)\n+/* not used */\n+#define CLASS_IPSEC_SA3_BASE_ADDR  (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)\n+\n+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */\n+#define CLASS_GP_DMEM_BUF_SIZE\t(2048 - (CLASS_PBUF_SIZE * 4) - \\\n+\t\t\t\t(CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))\n+#define CLASS_GP_DMEM_BUF\t((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \\\n+\t\t\t\t\tCLASS_SA_SIZE))\n+\n+#define TWO_LEVEL_ROUTE\t\tBIT(0)\n+#define PHYNO_IN_HASH\t\tBIT(1)\n+#define HW_ROUTE_FETCH\t\tBIT(3)\n+#define HW_BRIDGE_FETCH\t\tBIT(5)\n+#define IP_ALIGNED\t\tBIT(6)\n+#define ARC_HIT_CHECK_EN\tBIT(7)\n+#define CLASS_TOE\t\tBIT(11)\n+#define HASH_NORMAL\t\t(0 << 12)\n+#define HASH_CRC_PORT\t\tBIT(12)\n+#define HASH_CRC_IP\t\t(2 << 12)\n+#define HASH_CRC_PORT_IP\t(3 << 12)\n+#define QB2BUS_LE\t\tBIT(15)\n+\n+#define TCP_CHKSUM_DROP\t\tBIT(0)\n+#define UDP_CHKSUM_DROP\t\tBIT(1)\n+#define IPV4_CHKSUM_DROP\tBIT(9)\n+\n+/*CLASS_HIF_PARSE bits*/\n+#define HIF_PKT_CLASS_EN\tBIT(0)\n+#define HIF_PKT_OFFSET(ofst)\t(((ofst) & 0xF) << 1)\n+\n+struct class_cfg {\n+\tu32 toe_mode;\n+\tunsigned long route_table_baseaddr;\n+\tu32 route_table_hash_bits;\n+\tu32 pe_sys_clk_ratio;\n+\tu32 resume;\n+};\n+\n+#endif /* _CLASS_CSR_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/emac_mtip.h b/drivers/net/ppfe/base/cbus/emac_mtip.h\nnew file mode 100644\nindex 000000000..ea54e2ee5\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/emac_mtip.h\n@@ -0,0 +1,231 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _EMAC_H_\n+#define _EMAC_H_\n+\n+/* This file is for Ethernet MAC registers and offsets\n+ */\n+\n+#include <linux/ethtool.h>\n+\n+#define EMAC_IEVENT_REG\t\t0x004\n+#define EMAC_IMASK_REG\t\t0x008\n+#define EMAC_R_DES_ACTIVE_REG\t0x010\n+#define EMAC_X_DES_ACTIVE_REG\t0x014\n+#define EMAC_ECNTRL_REG\t\t0x024\n+#define EMAC_MII_DATA_REG\t0x040\n+#define EMAC_MII_CTRL_REG\t0x044\n+#define EMAC_MIB_CTRL_STS_REG\t0x064\n+#define EMAC_RCNTRL_REG\t\t0x084\n+#define EMAC_TCNTRL_REG\t\t0x0C4\n+#define EMAC_PHY_ADDR_LOW\t0x0E4\n+#define EMAC_PHY_ADDR_HIGH\t0x0E8\n+#define EMAC_GAUR\t\t0x120\n+#define EMAC_GALR\t\t0x124\n+#define EMAC_TFWR_STR_FWD\t0x144\n+#define EMAC_RX_SECTION_FULL\t0x190\n+#define EMAC_RX_SECTION_EMPTY\t0x194\n+#define EMAC_TX_SECTION_EMPTY\t0x1A0\n+#define EMAC_TRUNC_FL\t\t0x1B0\n+\n+#define RMON_T_DROP\t0x200 /* Count of frames not cntd correctly */\n+#define RMON_T_PACKETS\t0x204 /* RMON TX packet count */\n+#define RMON_T_BC_PKT\t0x208 /* RMON TX broadcast pkts */\n+#define RMON_T_MC_PKT\t0x20c /* RMON TX multicast pkts */\n+#define RMON_T_CRC_ALIGN\t0x210 /* RMON TX pkts with CRC align err */\n+#define RMON_T_UNDERSIZE\t0x214 /* RMON TX pkts < 64 bytes, good CRC */\n+#define RMON_T_OVERSIZE\t0x218 /* RMON TX pkts > MAX_FL bytes good CRC */\n+#define RMON_T_FRAG\t0x21c /* RMON TX pkts < 64 bytes, bad CRC */\n+#define RMON_T_JAB\t0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */\n+#define RMON_T_COL\t0x224 /* RMON TX collision count */\n+#define RMON_T_P64\t0x228 /* RMON TX 64 byte pkts */\n+#define RMON_T_P65TO127\t0x22c /* RMON TX 65 to 127 byte pkts */\n+#define RMON_T_P128TO255\t0x230 /* RMON TX 128 to 255 byte pkts */\n+#define RMON_T_P256TO511\t0x234 /* RMON TX 256 to 511 byte pkts */\n+#define RMON_T_P512TO1023\t0x238 /* RMON TX 512 to 1023 byte pkts */\n+#define RMON_T_P1024TO2047\t0x23c /* RMON TX 1024 to 2047 byte pkts */\n+#define RMON_T_P_GTE2048\t0x240 /* RMON TX pkts > 2048 bytes */\n+#define RMON_T_OCTETS\t0x244 /* RMON TX octets */\n+#define IEEE_T_DROP\t0x248 /* Count of frames not counted crtly */\n+#define IEEE_T_FRAME_OK\t0x24c /* Frames tx'd OK */\n+#define IEEE_T_1COL\t0x250 /* Frames tx'd with single collision */\n+#define IEEE_T_MCOL\t0x254 /* Frames tx'd with multiple collision */\n+#define IEEE_T_DEF\t0x258 /* Frames tx'd after deferral delay */\n+#define IEEE_T_LCOL\t0x25c /* Frames tx'd with late collision */\n+#define IEEE_T_EXCOL\t0x260 /* Frames tx'd with excesv collisions */\n+#define IEEE_T_MACERR\t0x264 /* Frames tx'd with TX FIFO underrun */\n+#define IEEE_T_CSERR\t0x268 /* Frames tx'd with carrier sense err */\n+#define IEEE_T_SQE\t0x26c /* Frames tx'd with SQE err */\n+#define IEEE_T_FDXFC\t0x270 /* Flow control pause frames tx'd */\n+#define IEEE_T_OCTETS_OK\t0x274 /* Octet count for frames tx'd w/o err */\n+#define RMON_R_PACKETS\t0x284 /* RMON RX packet count */\n+#define RMON_R_BC_PKT\t0x288 /* RMON RX broadcast pkts */\n+#define RMON_R_MC_PKT\t0x28c /* RMON RX multicast pkts */\n+#define RMON_R_CRC_ALIGN\t0x290 /* RMON RX pkts with CRC alignment err */\n+#define RMON_R_UNDERSIZE\t0x294 /* RMON RX pkts < 64 bytes, good CRC */\n+#define RMON_R_OVERSIZE\t0x298 /* RMON RX pkts > MAX_FL bytes good CRC */\n+#define RMON_R_FRAG\t0x29c /* RMON RX pkts < 64 bytes, bad CRC */\n+#define RMON_R_JAB\t0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */\n+#define RMON_R_RESVD_O\t0x2a4 /* Reserved */\n+#define RMON_R_P64\t0x2a8 /* RMON RX 64 byte pkts */\n+#define RMON_R_P65TO127\t0x2ac /* RMON RX 65 to 127 byte pkts */\n+#define RMON_R_P128TO255\t0x2b0 /* RMON RX 128 to 255 byte pkts */\n+#define RMON_R_P256TO511\t0x2b4 /* RMON RX 256 to 511 byte pkts */\n+#define RMON_R_P512TO1023\t0x2b8 /* RMON RX 512 to 1023 byte pkts */\n+#define RMON_R_P1024TO2047\t0x2bc /* RMON RX 1024 to 2047 byte pkts */\n+#define RMON_R_P_GTE2048\t0x2c0 /* RMON RX pkts > 2048 bytes */\n+#define RMON_R_OCTETS\t0x2c4 /* RMON RX octets */\n+#define IEEE_R_DROP\t0x2c8 /* Count frames not counted correctly */\n+#define IEEE_R_FRAME_OK\t0x2cc /* Frames rx'd OK */\n+#define IEEE_R_CRC\t0x2d0 /* Frames rx'd with CRC err */\n+#define IEEE_R_ALIGN\t0x2d4 /* Frames rx'd with alignment err */\n+#define IEEE_R_MACERR\t0x2d8 /* Receive FIFO overflow count */\n+#define IEEE_R_FDXFC\t0x2dc /* Flow control pause frames rx'd */\n+#define IEEE_R_OCTETS_OK\t0x2e0 /* Octet cnt for frames rx'd w/o err */\n+\n+#define EMAC_SMAC_0_0\t0x500 /*Supplemental MAC Address 0 (RW).*/\n+#define EMAC_SMAC_0_1\t0x504 /*Supplemental MAC Address 0 (RW).*/\n+\n+/* GEMAC definitions and settings */\n+\n+#define EMAC_PORT_0\t0\n+#define EMAC_PORT_1\t1\n+\n+/* GEMAC Bit definitions */\n+#define EMAC_IEVENT_HBERR\t\t 0x80000000\n+#define EMAC_IEVENT_BABR\t\t 0x40000000\n+#define EMAC_IEVENT_BABT\t\t 0x20000000\n+#define EMAC_IEVENT_GRA\t\t\t 0x10000000\n+#define EMAC_IEVENT_TXF\t\t\t 0x08000000\n+#define EMAC_IEVENT_TXB\t\t\t 0x04000000\n+#define EMAC_IEVENT_RXF\t\t\t 0x02000000\n+#define EMAC_IEVENT_RXB\t\t\t 0x01000000\n+#define EMAC_IEVENT_MII\t\t\t 0x00800000\n+#define EMAC_IEVENT_EBERR\t\t 0x00400000\n+#define EMAC_IEVENT_LC\t\t\t 0x00200000\n+#define EMAC_IEVENT_RL\t\t\t 0x00100000\n+#define EMAC_IEVENT_UN\t\t\t 0x00080000\n+\n+#define EMAC_IMASK_HBERR                 0x80000000\n+#define EMAC_IMASK_BABR                  0x40000000\n+#define EMAC_IMASKT_BABT                 0x20000000\n+#define EMAC_IMASK_GRA                   0x10000000\n+#define EMAC_IMASKT_TXF                  0x08000000\n+#define EMAC_IMASK_TXB                   0x04000000\n+#define EMAC_IMASKT_RXF                  0x02000000\n+#define EMAC_IMASK_RXB                   0x01000000\n+#define EMAC_IMASK_MII                   0x00800000\n+#define EMAC_IMASK_EBERR                 0x00400000\n+#define EMAC_IMASK_LC                    0x00200000\n+#define EMAC_IMASKT_RL                   0x00100000\n+#define EMAC_IMASK_UN                    0x00080000\n+\n+#define EMAC_RCNTRL_MAX_FL_SHIFT         16\n+#define EMAC_RCNTRL_LOOP                 0x00000001\n+#define EMAC_RCNTRL_DRT                  0x00000002\n+#define EMAC_RCNTRL_MII_MODE             0x00000004\n+#define EMAC_RCNTRL_PROM                 0x00000008\n+#define EMAC_RCNTRL_BC_REJ               0x00000010\n+#define EMAC_RCNTRL_FCE                  0x00000020\n+#define EMAC_RCNTRL_RGMII                0x00000040\n+#define EMAC_RCNTRL_SGMII                0x00000080\n+#define EMAC_RCNTRL_RMII                 0x00000100\n+#define EMAC_RCNTRL_RMII_10T             0x00000200\n+#define EMAC_RCNTRL_CRC_FWD\t\t 0x00004000\n+\n+#define EMAC_TCNTRL_GTS                  0x00000001\n+#define EMAC_TCNTRL_HBC                  0x00000002\n+#define EMAC_TCNTRL_FDEN                 0x00000004\n+#define EMAC_TCNTRL_TFC_PAUSE            0x00000008\n+#define EMAC_TCNTRL_RFC_PAUSE            0x00000010\n+\n+#define EMAC_ECNTRL_RESET                0x00000001      /* reset the EMAC */\n+#define EMAC_ECNTRL_ETHER_EN             0x00000002      /* enable the EMAC */\n+#define EMAC_ECNTRL_MAGIC_ENA\t\t 0x00000004\n+#define EMAC_ECNTRL_SLEEP\t\t 0x00000008\n+#define EMAC_ECNTRL_SPEED                0x00000020\n+#define EMAC_ECNTRL_DBSWAP               0x00000100\n+\n+#define EMAC_X_WMRK_STRFWD               0x00000100\n+\n+#define EMAC_X_DES_ACTIVE_TDAR           0x01000000\n+#define EMAC_R_DES_ACTIVE_RDAR           0x01000000\n+\n+#define EMAC_RX_SECTION_EMPTY_V\t\t0x00010006\n+/*\n+ * The possible operating speeds of the MAC, currently supporting 10, 100 and\n+ * 1000Mb modes.\n+ */\n+enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};\n+\n+/* MII-related definitios */\n+#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */\n+#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */\n+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */\n+#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */\n+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */\n+#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */\n+#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */\n+#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */\n+#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */\n+\n+#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */\n+#define EMAC_MII_DATA_RA_MASK\t 0x1F      /* MII Register address mask */\n+#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */\n+#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */\n+\n+#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \\\n+\t\t\t\tEMAC_MII_DATA_RA_SHIFT)\n+#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \\\n+\t\t\t\tEMAC_MII_DATA_PA_SHIFT)\n+#define EMAC_MII_DATA(v)    ((v) & 0xffff)\n+\n+#define EMAC_MII_SPEED_SHIFT\t1\n+#define EMAC_HOLDTIME_SHIFT\t8\n+#define EMAC_HOLDTIME_MASK\t0x7\n+#define EMAC_HOLDTIME(v)\t(((v) & EMAC_HOLDTIME_MASK) << \\\n+\t\t\t\t\tEMAC_HOLDTIME_SHIFT)\n+\n+/*\n+ * The Address organisation for the MAC device.  All addresses are split into\n+ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of\n+ * the address and the other field are the high order bits - this may be 16-bits\n+ * in the case of MAC addresses, or 32-bits for the hash address.\n+ * In terms of memory storage, the first item (bottom) is assumed to be at a\n+ * lower address location than 'top'. i.e. top should be at address location of\n+ * 'bottom' + 4 bytes.\n+ */\n+struct pfe_mac_addr {\n+\tu32 bottom;     /* Lower 32-bits of address. */\n+\tu32 top;        /* Upper 32-bits of address. */\n+};\n+\n+/*\n+ * The following is the organisation of the address filters section of the MAC\n+ * registers.  The Cadence MAC contains four possible specific address match\n+ * addresses, if an incoming frame corresponds to any one of these four\n+ * addresses then the frame will be copied to memory.\n+ * It is not necessary for all four of the address match registers to be\n+ * programmed, this is application dependent.\n+ */\n+struct spec_addr {\n+\tstruct pfe_mac_addr one;        /* Specific address register 1. */\n+\tstruct pfe_mac_addr two;        /* Specific address register 2. */\n+\tstruct pfe_mac_addr three;      /* Specific address register 3. */\n+\tstruct pfe_mac_addr four;       /* Specific address register 4. */\n+};\n+\n+struct gemac_cfg {\n+\tu32 mode;\n+\tu32 speed;\n+\tu32 duplex;\n+};\n+\n+/* EMAC Hash size */\n+#define EMAC_HASH_REG_BITS       64\n+\n+#define EMAC_SPEC_ADDR_MAX\t4\n+\n+#endif /* _EMAC_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/gpi.h b/drivers/net/ppfe/base/cbus/gpi.h\nnew file mode 100644\nindex 000000000..60d834323\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/gpi.h\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _GPI_H_\n+#define _GPI_H_\n+\n+/* Generic Packet Interface:The generic packet interface block interfaces\n+ * to block like ethernet, Host interfac and covert data into WSP internal\n+ * structures\n+ */\n+\n+#define GPI_VERSION\t0x00\n+#define GPI_CTRL\t0x04\n+#define GPI_RX_CONFIG\t0x08\n+#define GPI_HDR_SIZE\t0x0c\n+#define GPI_BUF_SIZE\t0x10\n+#define GPI_LMEM_ALLOC_ADDR\t0x14\n+#define GPI_LMEM_FREE_ADDR\t0x18\n+#define GPI_DDR_ALLOC_ADDR\t0x1c\n+#define GPI_DDR_FREE_ADDR\t0x20\n+#define GPI_CLASS_ADDR\t0x24\n+#define GPI_DRX_FIFO\t0x28\n+#define GPI_TRX_FIFO\t0x2c\n+#define GPI_INQ_PKTPTR\t0x30\n+#define GPI_DDR_DATA_OFFSET\t0x34\n+#define GPI_LMEM_DATA_OFFSET\t0x38\n+#define GPI_TMLF_TX\t0x4c\n+#define GPI_DTX_ASEQ\t0x50\n+#define GPI_FIFO_STATUS\t0x54\n+#define GPI_FIFO_DEBUG\t0x58\n+#define GPI_TX_PAUSE_TIME\t0x5c\n+#define GPI_LMEM_SEC_BUF_DATA_OFFSET\t0x60\n+#define GPI_DDR_SEC_BUF_DATA_OFFSET\t0x64\n+#define GPI_TOE_CHKSUM_EN\t0x68\n+#define GPI_OVERRUN_DROPCNT\t0x6c\n+#define GPI_CSR_MTIP_PAUSE_REG\t\t0x74\n+#define GPI_CSR_MTIP_PAUSE_QUANTUM\t0x78\n+#define GPI_CSR_RX_CNT\t\t\t0x7c\n+#define GPI_CSR_TX_CNT\t\t\t0x80\n+#define GPI_CSR_DEBUG1\t\t\t0x84\n+#define GPI_CSR_DEBUG2\t\t\t0x88\n+\n+struct gpi_cfg {\n+\tu32 lmem_rtry_cnt;\n+\tu32 tmlf_txthres;\n+\tu32 aseq_len;\n+\tu32 mtip_pause_reg;\n+};\n+\n+/* GPI commons defines */\n+#define GPI_LMEM_BUF_EN\t0x1\n+#define GPI_DDR_BUF_EN\t0x1\n+\n+/* EGPI 1 defines */\n+#define EGPI1_LMEM_RTRY_CNT\t0x40\n+#define EGPI1_TMLF_TXTHRES\t0xBC\n+#define EGPI1_ASEQ_LEN\t0x50\n+\n+/* EGPI 2 defines */\n+#define EGPI2_LMEM_RTRY_CNT\t0x40\n+#define EGPI2_TMLF_TXTHRES\t0xBC\n+#define EGPI2_ASEQ_LEN\t0x40\n+\n+/* EGPI 3 defines */\n+#define EGPI3_LMEM_RTRY_CNT\t0x40\n+#define EGPI3_TMLF_TXTHRES\t0xBC\n+#define EGPI3_ASEQ_LEN\t0x40\n+\n+/* HGPI defines */\n+#define HGPI_LMEM_RTRY_CNT\t0x40\n+#define HGPI_TMLF_TXTHRES\t0xBC\n+#define HGPI_ASEQ_LEN\t0x40\n+\n+#define EGPI_PAUSE_TIME\t\t0x000007D0\n+#define EGPI_PAUSE_ENABLE\t0x40000000\n+#endif /* _GPI_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/hif.h b/drivers/net/ppfe/base/cbus/hif.h\nnew file mode 100644\nindex 000000000..bffd3d923\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/hif.h\n@@ -0,0 +1,86 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _HIF_H_\n+#define _HIF_H_\n+\n+/* @file hif.h.\n+ * hif - PFE hif block control and status register.\n+ * Mapped on CBUS and accessible from all PE's and ARM.\n+ */\n+#define HIF_VERSION\t(HIF_BASE_ADDR + 0x00)\n+#define HIF_TX_CTRL\t(HIF_BASE_ADDR + 0x04)\n+#define HIF_TX_CURR_BD_ADDR\t(HIF_BASE_ADDR + 0x08)\n+#define HIF_TX_ALLOC\t(HIF_BASE_ADDR + 0x0c)\n+#define HIF_TX_BDP_ADDR\t(HIF_BASE_ADDR + 0x10)\n+#define HIF_TX_STATUS\t(HIF_BASE_ADDR + 0x14)\n+#define HIF_RX_CTRL\t(HIF_BASE_ADDR + 0x20)\n+#define HIF_RX_BDP_ADDR\t(HIF_BASE_ADDR + 0x24)\n+#define HIF_RX_STATUS\t(HIF_BASE_ADDR + 0x30)\n+#define HIF_INT_SRC\t(HIF_BASE_ADDR + 0x34)\n+#define HIF_INT_ENABLE\t(HIF_BASE_ADDR + 0x38)\n+#define HIF_POLL_CTRL\t(HIF_BASE_ADDR + 0x3c)\n+#define HIF_RX_CURR_BD_ADDR\t(HIF_BASE_ADDR + 0x40)\n+#define HIF_RX_ALLOC\t(HIF_BASE_ADDR + 0x44)\n+#define HIF_TX_DMA_STATUS\t(HIF_BASE_ADDR + 0x48)\n+#define HIF_RX_DMA_STATUS\t(HIF_BASE_ADDR + 0x4c)\n+#define HIF_INT_COAL\t(HIF_BASE_ADDR + 0x50)\n+\n+/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */\n+#define HIF_INT\t\tBIT(0)\n+#define HIF_RXBD_INT\tBIT(1)\n+#define HIF_RXPKT_INT\tBIT(2)\n+#define HIF_TXBD_INT\tBIT(3)\n+#define HIF_TXPKT_INT\tBIT(4)\n+\n+/* HIF_TX_CTRL bits */\n+#define HIF_CTRL_DMA_EN\t\t\tBIT(0)\n+#define HIF_CTRL_BDP_POLL_CTRL_EN\tBIT(1)\n+#define HIF_CTRL_BDP_CH_START_WSTB\tBIT(2)\n+\n+/* HIF_RX_STATUS bits */\n+#define BDP_CSR_RX_DMA_ACTV     BIT(16)\n+\n+/* HIF_INT_ENABLE bits */\n+#define HIF_INT_EN\t\tBIT(0)\n+#define HIF_RXBD_INT_EN\t\tBIT(1)\n+#define HIF_RXPKT_INT_EN\tBIT(2)\n+#define HIF_TXBD_INT_EN\t\tBIT(3)\n+#define HIF_TXPKT_INT_EN\tBIT(4)\n+\n+/* HIF_POLL_CTRL bits*/\n+#define HIF_RX_POLL_CTRL_CYCLE\t0x0400\n+#define HIF_TX_POLL_CTRL_CYCLE\t0x0400\n+\n+/* HIF_INT_COAL bits*/\n+#define HIF_INT_COAL_ENABLE\tBIT(31)\n+\n+/* Buffer descriptor control bits */\n+#define BD_CTRL_BUFLEN_MASK\t0x3fff\n+#define BD_BUF_LEN(x)\t((x) & BD_CTRL_BUFLEN_MASK)\n+#define BD_CTRL_CBD_INT_EN\tBIT(16)\n+#define BD_CTRL_PKT_INT_EN\tBIT(17)\n+#define BD_CTRL_LIFM\t\tBIT(18)\n+#define BD_CTRL_LAST_BD\t\tBIT(19)\n+#define BD_CTRL_DIR\t\tBIT(20)\n+#define BD_CTRL_LMEM_CPY\tBIT(21) /* Valid only for HIF_NOCPY */\n+#define BD_CTRL_PKT_XFER\tBIT(24)\n+#define BD_CTRL_DESC_EN\t\tBIT(31)\n+#define BD_CTRL_PARSE_DISABLE\tBIT(25)\n+#define BD_CTRL_BRFETCH_DISABLE\tBIT(26)\n+#define BD_CTRL_RTFETCH_DISABLE\tBIT(27)\n+\n+/* Buffer descriptor status bits*/\n+#define BD_STATUS_CONN_ID(x)\t((x) & 0xffff)\n+#define BD_STATUS_DIR_PROC_ID\tBIT(16)\n+#define BD_STATUS_CONN_ID_EN\tBIT(17)\n+#define BD_STATUS_PE2PROC_ID(x)\t(((x) & 7) << 18)\n+#define BD_STATUS_LE_DATA\tBIT(21)\n+#define BD_STATUS_CHKSUM_EN\tBIT(22)\n+\n+/* HIF Buffer descriptor status bits */\n+#define DIR_PROC_ID\tBIT(16)\n+#define PROC_ID(id)\t((id) << 18)\n+\n+#endif /* _HIF_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/hif_nocpy.h b/drivers/net/ppfe/base/cbus/hif_nocpy.h\nnew file mode 100644\nindex 000000000..8c627b1c7\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/hif_nocpy.h\n@@ -0,0 +1,36 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _HIF_NOCPY_H_\n+#define _HIF_NOCPY_H_\n+\n+#define HIF_NOCPY_VERSION\t(HIF_NOCPY_BASE_ADDR + 0x00)\n+#define HIF_NOCPY_TX_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x04)\n+#define HIF_NOCPY_TX_CURR_BD_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x08)\n+#define HIF_NOCPY_TX_ALLOC\t(HIF_NOCPY_BASE_ADDR + 0x0c)\n+#define HIF_NOCPY_TX_BDP_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x10)\n+#define HIF_NOCPY_TX_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x14)\n+#define HIF_NOCPY_RX_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x20)\n+#define HIF_NOCPY_RX_BDP_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x24)\n+#define HIF_NOCPY_RX_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x30)\n+#define HIF_NOCPY_INT_SRC\t(HIF_NOCPY_BASE_ADDR + 0x34)\n+#define HIF_NOCPY_INT_ENABLE\t(HIF_NOCPY_BASE_ADDR + 0x38)\n+#define HIF_NOCPY_POLL_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x3c)\n+#define HIF_NOCPY_RX_CURR_BD_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x40)\n+#define HIF_NOCPY_RX_ALLOC\t(HIF_NOCPY_BASE_ADDR + 0x44)\n+#define HIF_NOCPY_TX_DMA_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x48)\n+#define HIF_NOCPY_RX_DMA_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x4c)\n+#define HIF_NOCPY_RX_INQ0_PKTPTR\t(HIF_NOCPY_BASE_ADDR + 0x50)\n+#define HIF_NOCPY_RX_INQ1_PKTPTR\t(HIF_NOCPY_BASE_ADDR + 0x54)\n+#define HIF_NOCPY_TX_PORT_NO\t(HIF_NOCPY_BASE_ADDR + 0x60)\n+#define HIF_NOCPY_LMEM_ALLOC_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x64)\n+#define HIF_NOCPY_CLASS_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x68)\n+#define HIF_NOCPY_TMU_PORT0_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x70)\n+#define HIF_NOCPY_TMU_PORT1_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x74)\n+#define HIF_NOCPY_TMU_PORT2_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x7c)\n+#define HIF_NOCPY_TMU_PORT3_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x80)\n+#define HIF_NOCPY_TMU_PORT4_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x84)\n+#define HIF_NOCPY_INT_COAL\t(HIF_NOCPY_BASE_ADDR + 0x90)\n+\n+#endif /* _HIF_NOCPY_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/tmu_csr.h b/drivers/net/ppfe/base/cbus/tmu_csr.h\nnew file mode 100644\nindex 000000000..2f4a62a76\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/tmu_csr.h\n@@ -0,0 +1,154 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _TMU_CSR_H_\n+#define _TMU_CSR_H_\n+\n+#define TMU_VERSION\t(TMU_CSR_BASE_ADDR + 0x000)\n+#define TMU_INQ_WATERMARK\t(TMU_CSR_BASE_ADDR + 0x004)\n+#define TMU_PHY_INQ_PKTPTR\t(TMU_CSR_BASE_ADDR + 0x008)\n+#define TMU_PHY_INQ_PKTINFO\t(TMU_CSR_BASE_ADDR + 0x00c)\n+#define TMU_PHY_INQ_FIFO_CNT\t(TMU_CSR_BASE_ADDR + 0x010)\n+#define TMU_SYS_GENERIC_CONTROL\t(TMU_CSR_BASE_ADDR + 0x014)\n+#define TMU_SYS_GENERIC_STATUS\t(TMU_CSR_BASE_ADDR + 0x018)\n+#define TMU_SYS_GEN_CON0\t(TMU_CSR_BASE_ADDR + 0x01c)\n+#define TMU_SYS_GEN_CON1\t(TMU_CSR_BASE_ADDR + 0x020)\n+#define TMU_SYS_GEN_CON2\t(TMU_CSR_BASE_ADDR + 0x024)\n+#define TMU_SYS_GEN_CON3\t(TMU_CSR_BASE_ADDR + 0x028)\n+#define TMU_SYS_GEN_CON4\t(TMU_CSR_BASE_ADDR + 0x02c)\n+#define TMU_TEQ_DISABLE_DROPCHK\t(TMU_CSR_BASE_ADDR + 0x030)\n+#define TMU_TEQ_CTRL\t(TMU_CSR_BASE_ADDR + 0x034)\n+#define TMU_TEQ_QCFG\t(TMU_CSR_BASE_ADDR + 0x038)\n+#define TMU_TEQ_DROP_STAT\t(TMU_CSR_BASE_ADDR + 0x03c)\n+#define TMU_TEQ_QAVG\t(TMU_CSR_BASE_ADDR + 0x040)\n+#define TMU_TEQ_WREG_PROB\t(TMU_CSR_BASE_ADDR + 0x044)\n+#define TMU_TEQ_TRANS_STAT\t(TMU_CSR_BASE_ADDR + 0x048)\n+#define TMU_TEQ_HW_PROB_CFG0\t(TMU_CSR_BASE_ADDR + 0x04c)\n+#define TMU_TEQ_HW_PROB_CFG1\t(TMU_CSR_BASE_ADDR + 0x050)\n+#define TMU_TEQ_HW_PROB_CFG2\t(TMU_CSR_BASE_ADDR + 0x054)\n+#define TMU_TEQ_HW_PROB_CFG3\t(TMU_CSR_BASE_ADDR + 0x058)\n+#define TMU_TEQ_HW_PROB_CFG4\t(TMU_CSR_BASE_ADDR + 0x05c)\n+#define TMU_TEQ_HW_PROB_CFG5\t(TMU_CSR_BASE_ADDR + 0x060)\n+#define TMU_TEQ_HW_PROB_CFG6\t(TMU_CSR_BASE_ADDR + 0x064)\n+#define TMU_TEQ_HW_PROB_CFG7\t(TMU_CSR_BASE_ADDR + 0x068)\n+#define TMU_TEQ_HW_PROB_CFG8\t(TMU_CSR_BASE_ADDR + 0x06c)\n+#define TMU_TEQ_HW_PROB_CFG9\t(TMU_CSR_BASE_ADDR + 0x070)\n+#define TMU_TEQ_HW_PROB_CFG10\t(TMU_CSR_BASE_ADDR + 0x074)\n+#define TMU_TEQ_HW_PROB_CFG11\t(TMU_CSR_BASE_ADDR + 0x078)\n+#define TMU_TEQ_HW_PROB_CFG12\t(TMU_CSR_BASE_ADDR + 0x07c)\n+#define TMU_TEQ_HW_PROB_CFG13\t(TMU_CSR_BASE_ADDR + 0x080)\n+#define TMU_TEQ_HW_PROB_CFG14\t(TMU_CSR_BASE_ADDR + 0x084)\n+#define TMU_TEQ_HW_PROB_CFG15\t(TMU_CSR_BASE_ADDR + 0x088)\n+#define TMU_TEQ_HW_PROB_CFG16\t(TMU_CSR_BASE_ADDR + 0x08c)\n+#define TMU_TEQ_HW_PROB_CFG17\t(TMU_CSR_BASE_ADDR + 0x090)\n+#define TMU_TEQ_HW_PROB_CFG18\t(TMU_CSR_BASE_ADDR + 0x094)\n+#define TMU_TEQ_HW_PROB_CFG19\t(TMU_CSR_BASE_ADDR + 0x098)\n+#define TMU_TEQ_HW_PROB_CFG20\t(TMU_CSR_BASE_ADDR + 0x09c)\n+#define TMU_TEQ_HW_PROB_CFG21\t(TMU_CSR_BASE_ADDR + 0x0a0)\n+#define TMU_TEQ_HW_PROB_CFG22\t(TMU_CSR_BASE_ADDR + 0x0a4)\n+#define TMU_TEQ_HW_PROB_CFG23\t(TMU_CSR_BASE_ADDR + 0x0a8)\n+#define TMU_TEQ_HW_PROB_CFG24\t(TMU_CSR_BASE_ADDR + 0x0ac)\n+#define TMU_TEQ_HW_PROB_CFG25\t(TMU_CSR_BASE_ADDR + 0x0b0)\n+#define TMU_TDQ_IIFG_CFG\t(TMU_CSR_BASE_ADDR + 0x0b4)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY0\n+ */\n+#define TMU_TDQ0_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x0b8)\n+\n+#define TMU_LLM_CTRL\t(TMU_CSR_BASE_ADDR + 0x0bc)\n+#define TMU_LLM_BASE_ADDR\t(TMU_CSR_BASE_ADDR + 0x0c0)\n+#define TMU_LLM_QUE_LEN\t(TMU_CSR_BASE_ADDR + 0x0c4)\n+#define TMU_LLM_QUE_HEADPTR\t(TMU_CSR_BASE_ADDR + 0x0c8)\n+#define TMU_LLM_QUE_TAILPTR\t(TMU_CSR_BASE_ADDR + 0x0cc)\n+#define TMU_LLM_QUE_DROPCNT\t(TMU_CSR_BASE_ADDR + 0x0d0)\n+#define TMU_INT_EN\t(TMU_CSR_BASE_ADDR + 0x0d4)\n+#define TMU_INT_SRC\t(TMU_CSR_BASE_ADDR + 0x0d8)\n+#define TMU_INQ_STAT\t(TMU_CSR_BASE_ADDR + 0x0dc)\n+#define TMU_CTRL\t(TMU_CSR_BASE_ADDR + 0x0e0)\n+\n+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory\n+ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of\n+ * the internal memory. This address is used to access both the PM and DM of\n+ * all the PE's\n+ */\n+#define TMU_MEM_ACCESS_ADDR\t(TMU_CSR_BASE_ADDR + 0x0e4)\n+\n+/* Internal Memory Access Write Data */\n+#define TMU_MEM_ACCESS_WDATA\t(TMU_CSR_BASE_ADDR + 0x0e8)\n+/* Internal Memory Access Read Data. The commands are blocked\n+ * at the mem_access only\n+ */\n+#define TMU_MEM_ACCESS_RDATA\t(TMU_CSR_BASE_ADDR + 0x0ec)\n+\n+/* [31:0] PHY0 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY0_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f0)\n+/* [31:0] PHY1 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY1_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f4)\n+/* [31:0] PHY2 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY2_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f8)\n+/* [31:0] PHY3 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY3_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0fc)\n+#define TMU_BMU_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x100)\n+#define TMU_TX_CTRL\t(TMU_CSR_BASE_ADDR + 0x104)\n+\n+#define TMU_BUS_ACCESS_WDATA\t(TMU_CSR_BASE_ADDR + 0x108)\n+#define TMU_BUS_ACCESS\t(TMU_CSR_BASE_ADDR + 0x10c)\n+#define TMU_BUS_ACCESS_RDATA\t(TMU_CSR_BASE_ADDR + 0x110)\n+\n+#define TMU_PE_SYS_CLK_RATIO\t(TMU_CSR_BASE_ADDR + 0x114)\n+#define TMU_PE_STATUS\t(TMU_CSR_BASE_ADDR + 0x118)\n+#define TMU_TEQ_MAX_THRESHOLD\t(TMU_CSR_BASE_ADDR + 0x11c)\n+/* [31:0] PHY4 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY4_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x134)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY1\n+ */\n+#define TMU_TDQ1_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x138)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY2\n+ */\n+#define TMU_TDQ2_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x13c)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY3\n+ */\n+#define TMU_TDQ3_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x140)\n+#define TMU_BMU_BUF_SIZE\t(TMU_CSR_BASE_ADDR + 0x144)\n+/* [31:0] PHY5 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY5_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x148)\n+\n+#define SW_RESET\t\tBIT(0)\t/* Global software reset */\n+#define INQ_RESET\t\tBIT(2)\n+#define TEQ_RESET\t\tBIT(3)\n+#define TDQ_RESET\t\tBIT(4)\n+#define PE_RESET\t\tBIT(5)\n+#define MEM_INIT\t\tBIT(6)\n+#define MEM_INIT_DONE\t\tBIT(7)\n+#define LLM_INIT\t\tBIT(8)\n+#define LLM_INIT_DONE\t\tBIT(9)\n+#define ECC_MEM_INIT_DONE\tBIT(10)\n+\n+struct tmu_cfg {\n+\tu32 pe_sys_clk_ratio;\n+\tunsigned long llm_base_addr;\n+\tu32 llm_queue_len;\n+};\n+\n+/* Not HW related for pfe_ctrl / pfe common defines */\n+#define DEFAULT_MAX_QDEPTH\t80\n+#define DEFAULT_Q0_QDEPTH\t511 /*We keep one large queue for host tx qos */\n+#define DEFAULT_TMU3_QDEPTH\t127\n+\n+#endif /* _TMU_CSR_H_ */\ndiff --git a/drivers/net/ppfe/base/cbus/util_csr.h b/drivers/net/ppfe/base/cbus/util_csr.h\nnew file mode 100644\nindex 000000000..8b37b6fac\n--- /dev/null\n+++ b/drivers/net/ppfe/base/cbus/util_csr.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _UTIL_CSR_H_\n+#define _UTIL_CSR_H_\n+\n+#define UTIL_VERSION\t(UTIL_CSR_BASE_ADDR + 0x000)\n+#define UTIL_TX_CTRL\t(UTIL_CSR_BASE_ADDR + 0x004)\n+#define UTIL_INQ_PKTPTR\t(UTIL_CSR_BASE_ADDR + 0x010)\n+\n+#define UTIL_HDR_SIZE\t(UTIL_CSR_BASE_ADDR + 0x014)\n+\n+#define UTIL_PE0_QB_DM_ADDR0\t(UTIL_CSR_BASE_ADDR + 0x020)\n+#define UTIL_PE0_QB_DM_ADDR1\t(UTIL_CSR_BASE_ADDR + 0x024)\n+#define UTIL_PE0_RO_DM_ADDR0\t(UTIL_CSR_BASE_ADDR + 0x060)\n+#define UTIL_PE0_RO_DM_ADDR1\t(UTIL_CSR_BASE_ADDR + 0x064)\n+\n+#define UTIL_MEM_ACCESS_ADDR\t(UTIL_CSR_BASE_ADDR + 0x100)\n+#define UTIL_MEM_ACCESS_WDATA\t(UTIL_CSR_BASE_ADDR + 0x104)\n+#define UTIL_MEM_ACCESS_RDATA\t(UTIL_CSR_BASE_ADDR + 0x108)\n+\n+#define UTIL_TM_INQ_ADDR\t(UTIL_CSR_BASE_ADDR + 0x114)\n+#define UTIL_PE_STATUS\t(UTIL_CSR_BASE_ADDR + 0x118)\n+\n+#define UTIL_PE_SYS_CLK_RATIO\t(UTIL_CSR_BASE_ADDR + 0x200)\n+#define UTIL_AFULL_THRES\t(UTIL_CSR_BASE_ADDR + 0x204)\n+#define UTIL_GAP_BETWEEN_READS\t(UTIL_CSR_BASE_ADDR + 0x208)\n+#define UTIL_MAX_BUF_CNT\t(UTIL_CSR_BASE_ADDR + 0x20c)\n+#define UTIL_TSQ_FIFO_THRES\t(UTIL_CSR_BASE_ADDR + 0x210)\n+#define UTIL_TSQ_MAX_CNT\t(UTIL_CSR_BASE_ADDR + 0x214)\n+#define UTIL_IRAM_DATA_0\t(UTIL_CSR_BASE_ADDR + 0x218)\n+#define UTIL_IRAM_DATA_1\t(UTIL_CSR_BASE_ADDR + 0x21c)\n+#define UTIL_IRAM_DATA_2\t(UTIL_CSR_BASE_ADDR + 0x220)\n+#define UTIL_IRAM_DATA_3\t(UTIL_CSR_BASE_ADDR + 0x224)\n+\n+#define UTIL_BUS_ACCESS_ADDR\t(UTIL_CSR_BASE_ADDR + 0x228)\n+#define UTIL_BUS_ACCESS_WDATA\t(UTIL_CSR_BASE_ADDR + 0x22c)\n+#define UTIL_BUS_ACCESS_RDATA\t(UTIL_CSR_BASE_ADDR + 0x230)\n+\n+#define UTIL_INQ_AFULL_THRES\t(UTIL_CSR_BASE_ADDR + 0x234)\n+\n+struct util_cfg {\n+\tu32 pe_sys_clk_ratio;\n+};\n+\n+#endif /* _UTIL_CSR_H_ */\ndiff --git a/drivers/net/ppfe/base/pfe.h b/drivers/net/ppfe/base/pfe.h\nnew file mode 100644\nindex 000000000..c1fe71a3a\n--- /dev/null\n+++ b/drivers/net/ppfe/base/pfe.h\n@@ -0,0 +1,339 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ */\n+\n+#ifndef _PFE_H_\n+#define _PFE_H_\n+\n+#include \"cbus.h\"\n+\n+/*\n+ * WARNING: non atomic version.\n+ */\n+static inline void\n+set_bit(unsigned long nr, void *addr)\n+{\n+\tint *m = ((int *)addr) + (nr >> 5);\n+\t*m |= 1 << (nr & 31);\n+}\n+\n+static inline int\n+test_bit(int nr, const void *addr)\n+{\n+\treturn (1UL & (((const int *)addr)[nr >> 5] >> (nr & 31))) != 0UL;\n+}\n+\n+/*\n+ * WARNING: non atomic version.\n+ */\n+static inline void\n+clear_bit(unsigned long nr, void *addr)\n+{\n+\tint *m = ((int *)addr) + (nr >> 5);\n+\t*m &= ~(1 << (nr & 31));\n+}\n+\n+/*\n+ * WARNING: non atomic version.\n+ */\n+static inline int\n+test_and_clear_bit(unsigned long nr, void *addr)\n+{\n+\tunsigned long mask = 1 << (nr & 0x1f);\n+\tint *m = ((int *)addr) + (nr >> 5);\n+\tint old = *m;\n+\n+\t*m = old & ~mask;\n+\treturn (old & mask) != 0;\n+}\n+\n+/*\n+ * WARNING: non atomic version.\n+ */\n+static inline int\n+test_and_set_bit(unsigned long nr, void *addr)\n+{\n+\tunsigned long mask = 1 << (nr & 0x1f);\n+\tint *m = ((int *)addr) + (nr >> 5);\n+\tint old = *m;\n+\n+\t*m = old | mask;\n+\treturn (old & mask) != 0;\n+}\n+\n+#ifndef BIT\n+#define BIT(nr)                (1UL << (nr))\n+#endif\n+#define CLASS_DMEM_BASE_ADDR(i)\t(0x00000000 | ((i) << 20))\n+/*\n+ * Only valid for mem access register interface\n+ */\n+#define CLASS_IMEM_BASE_ADDR(i)\t(0x00000000 | ((i) << 20))\n+#define CLASS_DMEM_SIZE\t0x00002000\n+#define CLASS_IMEM_SIZE\t0x00008000\n+\n+#define TMU_DMEM_BASE_ADDR(i)\t(0x00000000 + ((i) << 20))\n+/*\n+ * Only valid for mem access register interface\n+ */\n+#define TMU_IMEM_BASE_ADDR(i)\t(0x00000000 + ((i) << 20))\n+#define TMU_DMEM_SIZE\t0x00000800\n+#define TMU_IMEM_SIZE\t0x00002000\n+\n+#define UTIL_DMEM_BASE_ADDR\t0x00000000\n+#define UTIL_DMEM_SIZE\t0x00002000\n+\n+#define PE_LMEM_BASE_ADDR\t0xc3010000\n+#define PE_LMEM_SIZE\t0x8000\n+#define PE_LMEM_END\t(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)\n+\n+#define DMEM_BASE_ADDR\t0x00000000\n+#define DMEM_SIZE\t0x2000\t/* TMU has less... */\n+#define DMEM_END\t(DMEM_BASE_ADDR + DMEM_SIZE)\n+\n+#define PMEM_BASE_ADDR\t0x00010000\n+#define PMEM_SIZE\t0x8000\t/* TMU has less... */\n+#define PMEM_END\t(PMEM_BASE_ADDR + PMEM_SIZE)\n+\n+#define writel(v, p) ({*(volatile unsigned int *)(p) = (v); })\n+#define readl(p) (*(const volatile unsigned int *)(p))\n+\n+/* These check memory ranges from PE point of view/memory map */\n+#define IS_DMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >= DMEM_BASE_ADDR) &&\t\\\n+\t(((unsigned long)(addr_) + (len)) <= DMEM_END); })\n+\n+#define IS_PMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >= PMEM_BASE_ADDR) &&\t\\\n+\t(((unsigned long)(addr_) + (len)) <= PMEM_END); })\n+\n+#define IS_PE_LMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tPE_LMEM_BASE_ADDR) &&\t\t\t\t\\\n+\t(((unsigned long)(addr_) +\t\t\t\\\n+\t(len)) <= PE_LMEM_END); })\n+\n+#define IS_PFE_LMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tCBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\t\t\\\n+\t(((unsigned long)(addr_) + (len)) <=\t\t\\\n+\tCBUS_VIRT_TO_PFE(LMEM_END)); })\n+\n+#define __IS_PHYS_DDR(addr, len)\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tDDR_PHYS_BASE_ADDR) &&\t\t\t\t\\\n+\t(((unsigned long)(addr_) + (len)) <=\t\t\\\n+\tDDR_PHYS_END); })\n+\n+#define IS_PHYS_DDR(addr, len)\t__IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)\n+\n+/*\n+ * If using a run-time virtual address for the cbus base address use this code\n+ */\n+extern void *cbus_base_addr;\n+extern void *ddr_base_addr;\n+extern unsigned long ddr_phys_base_addr;\n+extern unsigned int ddr_size;\n+\n+#define CBUS_BASE_ADDR\tcbus_base_addr\n+#define DDR_PHYS_BASE_ADDR\tddr_phys_base_addr\n+#define DDR_BASE_ADDR\tddr_base_addr\n+#define DDR_SIZE\tddr_size\n+\n+#define DDR_PHYS_END\t(DDR_PHYS_BASE_ADDR + DDR_SIZE)\n+\n+#define LS1012A_PFE_RESET_WA\t/*\n+\t\t\t\t * PFE doesn't have global reset and re-init\n+\t\t\t\t * should takecare few things to make PFE\n+\t\t\t\t * functional after reset\n+\t\t\t\t */\n+#define PFE_CBUS_PHYS_BASE_ADDR\t0xc0000000\t/* CBUS physical base address\n+\t\t\t\t\t\t * as seen by PE's.\n+\t\t\t\t\t\t */\n+/* CBUS physical base address as seen by PE's. */\n+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE\t0xc0000000\n+\n+#define DDR_PHYS_TO_PFE(p)\t(((unsigned long)(p)) & 0x7FFFFFFF)\n+#define DDR_PFE_TO_PHYS(p)\t(((unsigned long)(p)) | 0x80000000)\n+#define CBUS_PHYS_TO_PFE(p)\t(((p) - PFE_CBUS_PHYS_BASE_ADDR) + \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)\n+/* Translates to PFE address map */\n+\n+#define DDR_PHYS_TO_VIRT(p)\t(((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)\n+#define DDR_VIRT_TO_PHYS(v)\t(((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)\n+#define DDR_VIRT_TO_PFE(p)\t(DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))\n+\n+#define CBUS_VIRT_TO_PFE(v)\t(((v) - CBUS_BASE_ADDR) + \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR)\n+#define CBUS_PFE_TO_VIRT(p)\t(((unsigned long)(p) - \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)\n+\n+/* The below part of the code is used in QOS control driver from host */\n+#define TMU_APB_BASE_ADDR       0xc1000000      /* TMU base address seen by\n+\t\t\t\t\t\t * pe's\n+\t\t\t\t\t\t */\n+\n+enum {\n+\tCLASS0_ID = 0,\n+\tCLASS1_ID,\n+\tCLASS2_ID,\n+\tCLASS3_ID,\n+\tCLASS4_ID,\n+\tCLASS5_ID,\n+\tTMU0_ID,\n+\tTMU1_ID,\n+\tTMU2_ID,\n+\tTMU3_ID,\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tUTIL_ID,\n+#endif\n+\tMAX_PE\n+};\n+\n+#define CLASS_MASK\t(BIT(CLASS0_ID) | BIT(CLASS1_ID) |\\\n+\t\t\tBIT(CLASS2_ID) | BIT(CLASS3_ID) |\\\n+\t\t\tBIT(CLASS4_ID) | BIT(CLASS5_ID))\n+#define CLASS_MAX_ID\tCLASS5_ID\n+\n+#define TMU_MASK\t(BIT(TMU0_ID) | BIT(TMU1_ID) |\\\n+\t\t\tBIT(TMU3_ID))\n+\n+#define TMU_MAX_ID\tTMU3_ID\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+#define UTIL_MASK\tBIT(UTIL_ID)\n+#endif\n+\n+struct pe_status {\n+\tu32\tcpu_state;\n+\tu32\tactivity_counter;\n+\tu32\trx;\n+\tunion {\n+\tu32\ttx;\n+\tu32\ttmu_qstatus;\n+\t};\n+\tu32\tdrop;\n+#if defined(CFG_PE_DEBUG)\n+\tu32\tdebug_indicator;\n+\tu32\tdebug[16];\n+#endif\n+} __rte_aligned(16);\n+\n+struct pe_sync_mailbox {\n+\tu32 stop;\n+\tu32 stopped;\n+};\n+\n+/* Drop counter definitions */\n+\n+#define\tCLASS_NUM_DROP_COUNTERS\t13\n+#define\tUTIL_NUM_DROP_COUNTERS\t8\n+\n+/* PE information.\n+ * Structure containing PE's specific information. It is used to create\n+ * generic C functions common to all PE's.\n+ * Before using the library functions this structure needs to be initialized\n+ * with the different registers virtual addresses\n+ * (according to the ARM MMU mmaping). The default initialization supports a\n+ * virtual == physical mapping.\n+ */\n+struct pe_info {\n+\tu32 dmem_base_addr;\t/* PE's dmem base address */\n+\tu32 pmem_base_addr;\t/* PE's pmem base address */\n+\tu32 pmem_size;\t/* PE's pmem size */\n+\n+\tvoid *mem_access_wdata;\t/* PE's _MEM_ACCESS_WDATA register\n+\t\t\t\t * address\n+\t\t\t\t */\n+\tvoid *mem_access_addr;\t/* PE's _MEM_ACCESS_ADDR register\n+\t\t\t\t * address\n+\t\t\t\t */\n+\tvoid *mem_access_rdata;\t/* PE's _MEM_ACCESS_RDATA register\n+\t\t\t\t * address\n+\t\t\t\t */\n+};\n+\n+void pe_lmem_read(u32 *dst, u32 len, u32 offset);\n+void pe_lmem_write(u32 *src, u32 len, u32 offset);\n+\n+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);\n+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);\n+\n+u32 pe_pmem_read(int id, u32 addr, u8 size);\n+\n+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);\n+u32 pe_dmem_read(int id, u32 addr, u8 size);\n+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);\n+void class_pe_lmem_memset(u32 dst, int val, unsigned int len);\n+void class_bus_write(u32 val, u32 addr, u8 size);\n+u32 class_bus_read(u32 addr, u8 size);\n+\n+#define class_bus_readl(addr)\tclass_bus_read(addr, 4)\n+#define class_bus_readw(addr)\tclass_bus_read(addr, 2)\n+#define class_bus_readb(addr)\tclass_bus_read(addr, 1)\n+\n+#define class_bus_writel(val, addr)\tclass_bus_write(val, addr, 4)\n+#define class_bus_writew(val, addr)\tclass_bus_write(val, addr, 2)\n+#define class_bus_writeb(val, addr)\tclass_bus_write(val, addr, 1)\n+\n+#define pe_dmem_readl(id, addr)\tpe_dmem_read(id, addr, 4)\n+#define pe_dmem_readw(id, addr)\tpe_dmem_read(id, addr, 2)\n+#define pe_dmem_readb(id, addr)\tpe_dmem_read(id, addr, 1)\n+\n+#define pe_dmem_writel(id, val, addr)\tpe_dmem_write(id, val, addr, 4)\n+#define pe_dmem_writew(id, val, addr)\tpe_dmem_write(id, val, addr, 2)\n+#define pe_dmem_writeb(id, val, addr)\tpe_dmem_write(id, val, addr, 1)\n+\n+/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */\n+//int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,\n+//\t\t\tstruct device *dev);\n+\n+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,\n+\t\t  unsigned int ddr_size);\n+void bmu_init(void *base, struct BMU_CFG *cfg);\n+void bmu_reset(void *base);\n+void bmu_enable(void *base);\n+void bmu_disable(void *base);\n+void bmu_set_config(void *base, struct BMU_CFG *cfg);\n+\n+/*\n+ * An enumerated type for loopback values.  This can be one of three values, no\n+ * loopback -normal operation, local loopback with internal loopback module of\n+ * MAC or PHY loopback which is through the external PHY.\n+ */\n+#ifndef __MAC_LOOP_ENUM__\n+#define __MAC_LOOP_ENUM__\n+enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};\n+#endif\n+\n+/* Get Chip Revision level\n+ *\n+ */\n+static inline unsigned int CHIP_REVISION(void)\n+{\n+\t/*For LS1012A return always 1 */\n+\treturn 1;\n+}\n+\n+/* Start HIF rx DMA\n+ *\n+ */\n+static inline void hif_rx_dma_start(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);\n+}\n+\n+/* Start HIF tx DMA\n+ *\n+ */\n+static inline void hif_tx_dma_start(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);\n+}\n+\n+#endif /* _PFE_H_ */\n",
    "prefixes": [
        "v3",
        "05/14"
    ]
}