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GET /api/patches/59903/?format=api
{ "id": 59903, "url": "http://patches.dpdk.org/api/patches/59903/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1569506528-60464-22-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1569506528-60464-22-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1569506528-60464-22-git-send-email-xavier.huwei@huawei.com", "date": "2019-09-26T14:02:07", "name": "[v3,21/22] net/hns3: add reset related process for hns3 PMD driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "836a83c7c70498943551827ddfde3f7a4a4fa56e", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1569506528-60464-22-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6552, "url": "http://patches.dpdk.org/api/series/6552/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6552", "date": "2019-09-26T14:01:47", "name": "add hns3 ethernet PMD driver", "version": 3, "mbox": "http://patches.dpdk.org/series/6552/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/59903/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/59903/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CB2601BE8F;\n\tThu, 26 Sep 2019 16:06:08 +0200 (CEST)", "from huawei.com (szxga04-in.huawei.com [45.249.212.190])\n\tby dpdk.org (Postfix) with ESMTP id B2BB71BEAF\n\tfor <dev@dpdk.org>; Thu, 26 Sep 2019 16:05:00 +0200 (CEST)", "from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id 7C76D36E685F730DA76C;\n\tThu, 26 Sep 2019 22:04:58 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP\n\tServer id 14.3.439.0; Thu, 26 Sep 2019 22:04:48 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <xavier.huwei@tom.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Thu, 26 Sep 2019 22:02:07 +0800", "Message-ID": "<1569506528-60464-22-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1569506528-60464-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1569506528-60464-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v3 21/22] net/hns3: add reset related process for\n\thns3 PMD driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds reset related process for hns3 PMD driver.\nThe following three scenarios will trigger the reset process,\nand the driver settings will be restored after the reset is\nsuccessful:\n1. Receive a reset interrupt\n2. PF receives a hardware error interrupt\n3. VF is notified by PF to reset\n\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.c | 35 +++\n drivers/net/hns3/hns3_ethdev.c | 561 +++++++++++++++++++++++++++++++++++++-\n drivers/net/hns3/hns3_ethdev.h | 13 +\n drivers/net/hns3/hns3_ethdev_vf.c | 433 ++++++++++++++++++++++++++++-\n drivers/net/hns3/hns3_intr.c | 512 ++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_intr.h | 11 +\n drivers/net/hns3/hns3_mbx.c | 15 +\n drivers/net/hns3/hns3_rxtx.c | 23 +-\n 8 files changed, 1582 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nindex 706b910..3eebfdd 100644\n--- a/drivers/net/hns3/hns3_cmd.c\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -22,6 +22,7 @@\n \n #include \"hns3_ethdev.h\"\n #include \"hns3_regs.h\"\n+#include \"hns3_intr.h\"\n #include \"hns3_logs.h\"\n \n #define hns3_is_csq(ring) ((ring)->flag & HNS3_TYPE_CSQ)\n@@ -214,9 +215,28 @@ hns3_cmd_csq_clean(struct hns3_hw *hw)\n \thead = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG);\n \n \tif (!is_valid_csq_clean_head(csq, head)) {\n+\t\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\t\tuint32_t global;\n+\t\tuint32_t fun_rst;\n \t\thns3_err(hw, \"wrong cmd head (%u, %u-%u)\", head,\n \t\t\t csq->next_to_use, csq->next_to_clean);\n \t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\tif (hns->is_vf) {\n+\t\t\tglobal = hns3_read_dev(hw, HNS3_VF_RST_ING);\n+\t\t\tfun_rst = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n+\t\t\thns3_err(hw, \"Delayed VF reset global: %x fun_rst: %x\",\n+\t\t\t\t global, fun_rst);\n+\t\t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n+\t\t} else {\n+\t\t\tglobal = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);\n+\t\t\tfun_rst = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n+\t\t\thns3_err(hw, \"Delayed IMP reset global: %x fun_rst: %x\",\n+\t\t\t\t global, fun_rst);\n+\t\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n+\t\t}\n+\n+\t\thns3_schedule_delayed_reset(hns);\n+\n \t\treturn -EIO;\n \t}\n \n@@ -317,6 +337,7 @@ hns3_cmd_get_hardware_reply(struct hns3_hw *hw,\n \n static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n {\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n \tuint32_t timeout = 0;\n \n \tdo {\n@@ -329,6 +350,11 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n \t\t\treturn -EBUSY;\n \t\t}\n \n+\t\tif (is_reset_pending(hns)) {\n+\t\t\thns3_err(hw, \"Don't wait for reply because of reset pending\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\n \t\trte_delay_us(1);\n \t\ttimeout++;\n \t} while (timeout < hw->cmq.tx_timeout);\n@@ -484,6 +510,15 @@ hns3_cmd_init(struct hns3_hw *hw)\n \trte_spinlock_unlock(&hw->cmq.crq.lock);\n \trte_spinlock_unlock(&hw->cmq.csq.lock);\n \n+\t/*\n+\t * Check if there is new reset pending, because the higher level\n+\t * reset may happen when lower level reset is being processed.\n+\t */\n+\tif (is_reset_pending(HNS3_DEV_HW_TO_ADAPTER(hw))) {\n+\t\tPMD_INIT_LOG(ERR, \"New reset pending, keep disable cmd\");\n+\t\tret = -EBUSY;\n+\t\tgoto err_cmd_init;\n+\t}\n \trte_atomic16_clear(&hw->reset.disable_cmd);\n \n \tret = hns3_cmd_query_firmware_version(hw, &hw->fw_version);\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 220be21..361060d 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -9,6 +9,7 @@\n #include <stdint.h>\n #include <inttypes.h>\n #include <unistd.h>\n+#include <rte_atomic.h>\n #include <rte_bus_pci.h>\n #include <rte_common.h>\n #include <rte_cycles.h>\n@@ -49,6 +50,17 @@\n #define HNS3_FILTER_FE_INGRESS\t\t(HNS3_FILTER_FE_NIC_INGRESS_B \\\n \t\t\t\t\t| HNS3_FILTER_FE_ROCE_INGRESS_B)\n \n+/* Reset related Registers */\n+#define HNS3_GLOBAL_RESET_BIT\t\t0\n+#define HNS3_CORE_RESET_BIT\t\t1\n+#define HNS3_IMP_RESET_BIT\t\t2\n+#define HNS3_FUN_RST_ING_B\t\t0\n+\n+#define HNS3_VECTOR0_IMP_RESET_INT_B\t1\n+\n+#define HNS3_RESET_WAIT_MS\t100\n+#define HNS3_RESET_WAIT_CNT\t200\n+\n int hns3_logtype_init;\n int hns3_logtype_driver;\n \n@@ -59,6 +71,8 @@ enum hns3_evt_cause {\n \tHNS3_VECTOR0_EVENT_OTHER,\n };\n \n+static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,\n+\t\t\t\t\t\t uint64_t *levels);\n static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,\n \t\t\t\t int on);\n@@ -96,14 +110,34 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \t * from H/W just for the mailbox.\n \t */\n \tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */\n+\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\thns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);\n \t\tval = BIT(HNS3_VECTOR0_IMPRESET_INT_B);\n+\t\tif (clearval) {\n+\t\t\thw->reset.stats.imp_cnt++;\n+\t\t\thns3_warn(hw, \"IMP reset detected, clear reset status\");\n+\t\t} else {\n+\t\t\thns3_schedule_delayed_reset(hns);\n+\t\t\thns3_warn(hw, \"IMP reset detected, don't clear reset status\");\n+\t\t}\n+\n \t\tret = HNS3_VECTOR0_EVENT_RST;\n \t\tgoto out;\n \t}\n \n \t/* Global reset */\n \tif (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {\n+\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\thns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);\n \t\tval = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);\n+\t\tif (clearval) {\n+\t\t\thw->reset.stats.global_cnt++;\n+\t\t\thns3_warn(hw, \"Global reset detected, clear reset status\");\n+\t\t} else {\n+\t\t\thns3_schedule_delayed_reset(hns);\n+\t\t\thns3_warn(hw, \"Global reset detected, don't clear reset status\");\n+\t\t}\n+\n \t\tret = HNS3_VECTOR0_EVENT_RST;\n \t\tgoto out;\n \t}\n@@ -177,6 +211,15 @@ hns3_interrupt_handler(void *param)\n \n \tevent_cause = hns3_check_event_cause(hns, &clearval);\n \n+\t/* vector 0 interrupt is shared with reset and mailbox source events. */\n+\tif (event_cause == HNS3_VECTOR0_EVENT_ERR) {\n+\t\thns3_handle_msix_error(hns, &hw->reset.request);\n+\t\thns3_schedule_reset(hns);\n+\t} else if (event_cause == HNS3_VECTOR0_EVENT_RST)\n+\t\thns3_schedule_reset(hns);\n+\telse\n+\t\thns3_err(hw, \"Received unknown event\");\n+\n \thns3_clear_event_cause(hw, event_cause, clearval);\n \t/* Enable interrupt if it is not cause by reset */\n \thns3_pf_enable_irq0(hw);\n@@ -251,6 +294,32 @@ hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,\n }\n \n static int\n+hns3_restore_vlan_table(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_user_vlan_table *vlan_entry;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tuint16_t vlan_id;\n+\tint ret = 0;\n+\n+\tif (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {\n+\t\tret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,\n+\t\t\t\t\t 1);\n+\t\treturn ret;\n+\t}\n+\n+\tLIST_FOREACH(vlan_entry, &pf->vlan_list, next) {\n+\t\tif (vlan_entry->hd_tbl_status) {\n+\t\t\tvlan_id = vlan_entry->vlan_id;\n+\t\t\tret = hns3_set_port_vlan_filter(hns, vlan_id, 1);\n+\t\t\tif (ret)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)\n {\n \tstruct hns3_pf *pf = &hns->pf;\n@@ -875,6 +944,26 @@ hns3_init_vlan_config(struct hns3_adapter *hns)\n }\n \n static int\n+hns3_restore_vlan_conf(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);\n+\tif (ret) {\n+\t\thns3_err(hw, \"hns3 restore vlan rx conf fail, ret =%d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);\n+\tif (ret)\n+\t\thns3_err(hw, \"hns3 restore vlan tx conf fail, ret =%d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n hns3_dev_configure_vlan(struct rte_eth_dev *dev)\n {\n \tstruct hns3_adapter *hns = dev->data->dev_private;\n@@ -3528,6 +3617,19 @@ hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)\n }\n \n static int\n+hns3_dev_promisc_restore(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tbool en_mc_pmc;\n+\tbool en_uc_pmc;\n+\n+\ten_uc_pmc = (hw->data->promiscuous == 1) ? true : false;\n+\ten_mc_pmc = (hw->data->all_multicast == 1) ? true : false;\n+\n+\treturn hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);\n+}\n+\n+static int\n hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)\n {\n \tstruct hns3_sfp_speed_cmd *resp;\n@@ -3681,8 +3783,11 @@ hns3_service_handler(void *param)\n \tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\thns3_update_speed_duplex(eth_dev);\n-\thns3_update_link_status(hw);\n+\tif (!hns3_is_reset_pending(hns)) {\n+\t\thns3_update_speed_duplex(eth_dev);\n+\t\thns3_update_link_status(hw);\n+\t} else\n+\t\thns3_warn(hw, \"Cancel the query when reset is pending\");\n \n \trte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);\n }\n@@ -3916,7 +4021,8 @@ hns3_dev_start(struct rte_eth_dev *eth_dev)\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n-\n+\tif (rte_atomic16_read(&hw->reset.resetting))\n+\t\treturn -EBUSY;\n \trte_spinlock_lock(&hw->lock);\n \thw->adapter_state = HNS3_NIC_STARTING;\n \n@@ -3947,8 +4053,11 @@ hns3_do_stop(struct hns3_adapter *hns)\n \t\treturn ret;\n \thw->mac.link_status = ETH_LINK_DOWN;\n \n-\thns3_configure_all_mac_addr(hns, true);\n-\treset_queue = true;\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {\n+\t\thns3_configure_all_mac_addr(hns, true);\n+\t\treset_queue = true;\n+\t} else\n+\t\treset_queue = false;\n \thw->mac.default_addr_setted = false;\n \treturn hns3_stop_queues(hns, reset_queue);\n }\n@@ -3965,10 +4074,11 @@ hns3_dev_stop(struct rte_eth_dev *eth_dev)\n \thns3_set_rxtx_function(eth_dev);\n \n \trte_spinlock_lock(&hw->lock);\n-\n-\thns3_do_stop(hns);\n-\thns3_dev_release_mbufs(hns);\n-\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\tif (rte_atomic16_read(&hw->reset.resetting) == 0) {\n+\t\thns3_do_stop(hns);\n+\t\thns3_dev_release_mbufs(hns);\n+\t\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\t}\n \trte_spinlock_unlock(&hw->lock);\n }\n \n@@ -3982,6 +4092,8 @@ hns3_dev_close(struct rte_eth_dev *eth_dev)\n \t\thns3_dev_stop(eth_dev);\n \n \thw->adapter_state = HNS3_NIC_CLOSING;\n+\thns3_reset_abort(hns);\n+\thw->adapter_state = HNS3_NIC_CLOSED;\n \trte_eal_alarm_cancel(hns3_service_handler, eth_dev);\n \n \thns3_configure_all_mc_mac_addr(hns, true);\n@@ -3989,9 +4101,9 @@ hns3_dev_close(struct rte_eth_dev *eth_dev)\n \thns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);\n \thns3_uninit_pf(eth_dev);\n \thns3_free_all_queues(eth_dev);\n+\trte_free(hw->reset.wait_data);\n \trte_free(eth_dev->process_private);\n \teth_dev->process_private = NULL;\n-\thw->adapter_state = HNS3_NIC_CLOSED;\n \thns3_warn(hw, \"Close port %d finished\", hw->data->port_id);\n }\n \n@@ -4181,6 +4293,410 @@ hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)\n \treturn 0;\n }\n \n+static int\n+hns3_reinit_dev(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3_cmd_init(hw);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to init cmd: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hns3_reset_all_queues(hns);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to reset all queues: %d\", ret);\n+\t\tgoto err_init;\n+\t}\n+\n+\tret = hns3_init_hardware(hns);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to init hardware: %d\", ret);\n+\t\tgoto err_init;\n+\t}\n+\n+\tret = hns3_enable_hw_error_intr(hns, true);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to enable hw error interrupts: %d\",\n+\t\t\t ret);\n+\t\tgoto err_mac_init;\n+\t}\n+\thns3_info(hw, \"Reset done, driver initialization finished.\");\n+\n+\treturn 0;\n+\n+err_mac_init:\n+\thns3_uninit_umv_space(hw);\n+err_init:\n+\thns3_cmd_uninit(hw);\n+\n+\treturn ret;\n+}\n+\n+static bool\n+is_pf_reset_done(struct hns3_hw *hw)\n+{\n+\tuint32_t val, reg, reg_bit;\n+\n+\tswitch (hw->reset.level) {\n+\tcase HNS3_IMP_RESET:\n+\t\treg = HNS3_GLOBAL_RESET_REG;\n+\t\treg_bit = HNS3_IMP_RESET_BIT;\n+\t\tbreak;\n+\tcase HNS3_GLOBAL_RESET:\n+\t\treg = HNS3_GLOBAL_RESET_REG;\n+\t\treg_bit = HNS3_GLOBAL_RESET_BIT;\n+\t\tbreak;\n+\tcase HNS3_FUNC_RESET:\n+\t\treg = HNS3_FUN_RST_ING;\n+\t\treg_bit = HNS3_FUN_RST_ING_B;\n+\t\tbreak;\n+\tcase HNS3_FLR_RESET:\n+\tdefault:\n+\t\thns3_err(hw, \"Wait for unsupported reset level: %d\",\n+\t\t\t hw->reset.level);\n+\t\treturn true;\n+\t}\n+\tval = hns3_read_dev(hw, reg);\n+\tif (hns3_get_bit(val, reg_bit))\n+\t\treturn false;\n+\telse\n+\t\treturn true;\n+}\n+\n+bool\n+hns3_is_reset_pending(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_reset_level reset;\n+\n+\thns3_check_event_cause(hns, NULL);\n+\treset = hns3_get_reset_level(hns, &hw->reset.pending);\n+\tif (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {\n+\t\thns3_warn(hw, \"High level reset %d is pending\", reset);\n+\t\treturn true;\n+\t}\n+\treset = hns3_get_reset_level(hns, &hw->reset.request);\n+\tif (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {\n+\t\thns3_warn(hw, \"High level reset %d is request\", reset);\n+\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static int\n+hns3_wait_hardware_ready(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_wait_data *wait_data = hw->reset.wait_data;\n+\tstruct timeval tv;\n+\n+\tif (wait_data->result == HNS3_WAIT_SUCCESS)\n+\t\treturn 0;\n+\telse if (wait_data->result == HNS3_WAIT_TIMEOUT) {\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_warn(hw, \"Reset step4 hardware not ready after reset time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\treturn -ETIME;\n+\t} else if (wait_data->result == HNS3_WAIT_REQUEST)\n+\t\treturn -EAGAIN;\n+\n+\twait_data->hns = hns;\n+\twait_data->check_completion = is_pf_reset_done;\n+\twait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *\n+\t\t\t\t HNS3_RESET_WAIT_MS + get_timeofday_ms();\n+\twait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;\n+\twait_data->count = HNS3_RESET_WAIT_CNT;\n+\twait_data->result = HNS3_WAIT_REQUEST;\n+\trte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);\n+\treturn -EAGAIN;\n+}\n+\n+static int\n+hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)\n+{\n+\tstruct hns3_cmd_desc desc;\n+\tstruct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);\n+\thns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);\n+\treq->fun_reset_vfid = func_id;\n+\n+\treturn hns3_cmd_send(hw, &desc, 1);\n+}\n+\n+static int\n+hns3_imp_reset_cmd(struct hns3_hw *hw)\n+{\n+\tstruct hns3_cmd_desc desc;\n+\n+\thns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);\n+\tdesc.data[0] = 0xeedd;\n+\n+\treturn hns3_cmd_send(hw, &desc, 1);\n+}\n+\n+static void\n+hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct timeval tv;\n+\tuint32_t val;\n+\n+\tgettimeofday(&tv, NULL);\n+\tif (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||\n+\t hns3_read_dev(hw, HNS3_FUN_RST_ING)) {\n+\t\thns3_warn(hw, \"Don't process msix during resetting time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\treturn;\n+\t}\n+\n+\tswitch (reset_level) {\n+\tcase HNS3_IMP_RESET:\n+\t\thns3_imp_reset_cmd(hw);\n+\t\thns3_warn(hw, \"IMP Reset requested time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\tbreak;\n+\tcase HNS3_GLOBAL_RESET:\n+\t\tval = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);\n+\t\thns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);\n+\t\thns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);\n+\t\thns3_warn(hw, \"Global Reset requested time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\tbreak;\n+\tcase HNS3_FUNC_RESET:\n+\t\thns3_warn(hw, \"PF Reset requested time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\t/* schedule again to check later */\n+\t\thns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);\n+\t\thns3_schedule_reset(hns);\n+\t\tbreak;\n+\tdefault:\n+\t\thns3_warn(hw, \"Unsupported reset level: %d\", reset_level);\n+\t\treturn;\n+\t}\n+\thns3_atomic_clear_bit(reset_level, &hw->reset.request);\n+}\n+\n+static enum hns3_reset_level\n+hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_reset_level reset_level = HNS3_NONE_RESET;\n+\n+\t/* Return the highest priority reset level amongst all */\n+\tif (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))\n+\t\treset_level = HNS3_IMP_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))\n+\t\treset_level = HNS3_GLOBAL_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))\n+\t\treset_level = HNS3_FUNC_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))\n+\t\treset_level = HNS3_FLR_RESET;\n+\n+\tif (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)\n+\t\treturn HNS3_NONE_RESET;\n+\n+\treturn reset_level;\n+}\n+\n+static int\n+hns3_prepare_reset(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint32_t reg_val;\n+\tint ret;\n+\n+\tswitch (hw->reset.level) {\n+\tcase HNS3_FUNC_RESET:\n+\t\tret = hns3_func_reset_cmd(hw, 0);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * After performaning pf reset, it is not necessary to do the\n+\t\t * mailbox handling or send any command to firmware, because\n+\t\t * any mailbox handling or command to firmware is only valid\n+\t\t * after hns3_cmd_init is called.\n+\t\t */\n+\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\thw->reset.stats.request_cnt++;\n+\t\tbreak;\n+\tcase HNS3_IMP_RESET:\n+\t\treg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);\n+\t\thns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |\n+\t\t\t BIT(HNS3_VECTOR0_IMP_RESET_INT_B));\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+hns3_set_rst_done(struct hns3_hw *hw)\n+{\n+\tstruct hns3_pf_rst_done_cmd *req;\n+\tstruct hns3_cmd_desc desc;\n+\n+\treq = (struct hns3_pf_rst_done_cmd *)desc.data;\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);\n+\treq->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;\n+\treturn hns3_cmd_send(hw, &desc, 1);\n+}\n+\n+static int\n+hns3_stop_service(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\teth_dev = &rte_eth_devices[hw->data->port_id];\n+\trte_eal_alarm_cancel(hns3_service_handler, eth_dev);\n+\thw->mac.link_status = ETH_LINK_DOWN;\n+\n+\thns3_set_rxtx_function(eth_dev);\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tif (hns->hw.adapter_state == HNS3_NIC_STARTED ||\n+\t hw->adapter_state == HNS3_NIC_STOPPING) {\n+\t\thns3_do_stop(hns);\n+\t\thw->reset.mbuf_deferred_free = true;\n+\t} else\n+\t\thw->reset.mbuf_deferred_free = false;\n+\n+\t/*\n+\t * It is cumbersome for hardware to pick-and-choose entries for deletion\n+\t * from table space. Hence, for function reset software intervention is\n+\t * required to delete the entries\n+\t */\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0)\n+\t\thns3_configure_all_mc_mac_addr(hns, true);\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_start_service(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\tif (hw->reset.level == HNS3_IMP_RESET ||\n+\t hw->reset.level == HNS3_GLOBAL_RESET)\n+\t\thns3_set_rst_done(hw);\n+\teth_dev = &rte_eth_devices[hw->data->port_id];\n+\thns3_set_rxtx_function(eth_dev);\n+\thns3_service_handler(eth_dev);\n+\treturn 0;\n+}\n+\n+static int\n+hns3_restore_conf(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3_configure_all_mac_addr(hns, false);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hns3_configure_all_mc_mac_addr(hns, false);\n+\tif (ret)\n+\t\tgoto err_mc_mac;\n+\n+\tret = hns3_dev_promisc_restore(hns);\n+\tif (ret)\n+\t\tgoto err_promisc;\n+\n+\tret = hns3_restore_vlan_table(hns);\n+\tif (ret)\n+\t\tgoto err_promisc;\n+\n+\tret = hns3_restore_vlan_conf(hns);\n+\tif (ret)\n+\t\tgoto err_promisc;\n+\n+\tret = hns3_restore_all_fdir_filter(hns);\n+\tif (ret)\n+\t\tgoto err_promisc;\n+\n+\tif (hns->hw.adapter_state == HNS3_NIC_STARTED) {\n+\t\tret = hns3_do_start(hns, false);\n+\t\tif (ret)\n+\t\t\tgoto err_promisc;\n+\t\thns3_info(hw, \"hns3 dev restart successful!\");\n+\t} else if (hw->adapter_state == HNS3_NIC_STOPPING)\n+\t\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\treturn 0;\n+\n+err_promisc:\n+\thns3_configure_all_mc_mac_addr(hns, true);\n+err_mc_mac:\n+\thns3_configure_all_mac_addr(hns, true);\n+\treturn ret;\n+}\n+\n+static void\n+hns3_reset_service(void *param)\n+{\n+\tstruct hns3_adapter *hns = (struct hns3_adapter *)param;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_reset_level reset_level;\n+\tstruct timeval tv_delta;\n+\tstruct timeval tv_start;\n+\tstruct timeval tv;\n+\tuint64_t msec;\n+\tint ret;\n+\n+\t/*\n+\t * The interrupt is not triggered within the delay time.\n+\t * The interrupt may have been lost. It is necessary to handle\n+\t * the interrupt to recover from the error.\n+\t */\n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {\n+\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n+\t\thns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n+\t}\n+\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);\n+\n+\t/*\n+\t * Check if there is any ongoing reset in the hardware. This status can\n+\t * be checked from reset_pending. If there is then, we need to wait for\n+\t * hardware to complete reset.\n+\t * a. If we are able to figure out in reasonable time that hardware\n+\t * has fully resetted then, we can proceed with driver, client\n+\t * reset.\n+\t * b. else, we can come back later to check this status so re-sched\n+\t * now.\n+\t */\n+\treset_level = hns3_get_reset_level(hns, &hw->reset.pending);\n+\tif (reset_level != HNS3_NONE_RESET) {\n+\t\tgettimeofday(&tv_start, NULL);\n+\t\tret = hns3_reset_process(hns, reset_level);\n+\t\tgettimeofday(&tv, NULL);\n+\t\ttimersub(&tv, &tv_start, &tv_delta);\n+\t\tmsec = tv_delta.tv_sec * MSEC_PER_SEC +\n+\t\t tv_delta.tv_usec / USEC_PER_MSEC;\n+\t\tif (msec > HNS3_RESET_PROCESS_MS)\n+\t\t\thns3_err(hw, \"%d handle long time delta %\" PRIx64\n+\t\t\t\t \" ms time=%ld.%.6ld\",\n+\t\t\t\t hw->reset.level, msec,\n+\t\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\tif (ret == -EAGAIN)\n+\t\t\treturn;\n+\t}\n+\n+\t/* Check if we got any *new* reset requests to be honored */\n+\treset_level = hns3_get_reset_level(hns, &hw->reset.request);\n+\tif (reset_level != HNS3_NONE_RESET)\n+\t\thns3_msix_process(hns, reset_level);\n+}\n+\n static const struct eth_dev_ops hns3_eth_dev_ops = {\n \t.dev_start = hns3_dev_start,\n \t.dev_stop = hns3_dev_stop,\n@@ -4226,6 +4742,16 @@ static const struct eth_dev_ops hns3_eth_dev_ops = {\n \t.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,\n };\n \n+static const struct hns3_reset_ops hns3_reset_ops = {\n+\t.reset_service = hns3_reset_service,\n+\t.stop_service = hns3_stop_service,\n+\t.prepare_reset = hns3_prepare_reset,\n+\t.wait_hardware_ready = hns3_wait_hardware_ready,\n+\t.reinit_dev = hns3_reinit_dev,\n+\t.restore_conf\t = hns3_restore_conf,\n+\t.start_service = hns3_start_service,\n+};\n+\n static int\n hns3_dev_init(struct rte_eth_dev *eth_dev)\n {\n@@ -4269,6 +4795,11 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)\n \t */\n \thns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;\n \n+\tret = hns3_reset_init(hw);\n+\tif (ret)\n+\t\tgoto err_init_reset;\n+\thw->reset.ops = &hns3_reset_ops;\n+\n \tret = hns3_init_pf(eth_dev);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR, \"Failed to init pf: %d\", ret);\n@@ -4298,6 +4829,14 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)\n \t */\n \teth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;\n \n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {\n+\t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n+\t\thns3_schedule_reset(hns);\n+\t} else {\n+\t\t/* IMP will wait ready flag before reset */\n+\t\thns3_notify_reset_ready(hw, false);\n+\t}\n+\n \trte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);\n \thns3_info(hw, \"hns3 dev initialization successful!\");\n \treturn 0;\n@@ -4306,6 +4845,8 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)\n \thns3_uninit_pf(eth_dev);\n \n err_init_pf:\n+\trte_free(hw->reset.wait_data);\n+err_init_reset:\n \teth_dev->dev_ops = NULL;\n \teth_dev->rx_pkt_burst = NULL;\n \teth_dev->tx_pkt_burst = NULL;\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex c907a35..9710e45 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -628,5 +628,18 @@ int hns3_config_gro(struct hns3_hw *hw, bool en);\n int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,\n \t\t\t enum rte_filter_type filter_type,\n \t\t\t enum rte_filter_op filter_op, void *arg);\n+bool hns3_is_reset_pending(struct hns3_adapter *hns);\n+bool hns3vf_is_reset_pending(struct hns3_adapter *hns);\n+\n+static inline bool\n+is_reset_pending(struct hns3_adapter *hns)\n+{\n+\tbool ret;\n+\tif (hns->is_vf)\n+\t\tret = hns3vf_is_reset_pending(hns);\n+\telse\n+\t\tret = hns3_is_reset_pending(hns);\n+\treturn ret;\n+}\n \n #endif /* _HNS3_ETHDEV_H_ */\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex e20cfc5..fc98ebb 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -38,12 +38,20 @@\n #define HNS3VF_RESET_WAIT_MS\t20\n #define HNS3VF_RESET_WAIT_CNT\t2000\n \n+/* Reset related Registers */\n+#define HNS3_GLOBAL_RESET_BIT\t\t0\n+#define HNS3_CORE_RESET_BIT\t\t1\n+#define HNS3_IMP_RESET_BIT\t\t2\n+#define HNS3_FUN_RST_ING_B\t\t0\n+\n enum hns3vf_evt_cause {\n \tHNS3VF_VECTOR0_EVENT_RST,\n \tHNS3VF_VECTOR0_EVENT_MBX,\n \tHNS3VF_VECTOR0_EVENT_OTHER,\n };\n \n+static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,\n+\t\t\t\t\t\t uint64_t *levels);\n static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);\n \n@@ -427,6 +435,11 @@ hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n \t\treturn -EBUSY;\n \t}\n \n+\tif (rte_atomic16_read(&hw->reset.resetting)) {\n+\t\thns3_err(hw, \"Failed to set mtu during resetting\");\n+\t\treturn -EIO;\n+\t}\n+\n \trte_spinlock_lock(&hw->lock);\n \tret = hns3vf_config_mtu(hw, mtu);\n \tif (ret) {\n@@ -528,11 +541,32 @@ hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \tstruct hns3_hw *hw = &hns->hw;\n \tenum hns3vf_evt_cause ret;\n \tuint32_t cmdq_stat_reg;\n+\tuint32_t rst_ing_reg;\n \tuint32_t val;\n \n \t/* Fetch the events from their corresponding regs */\n \tcmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);\n \n+\tif (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {\n+\t\trst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n+\t\thns3_warn(hw, \"resetting reg: 0x%x\", rst_ing_reg);\n+\t\thns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);\n+\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\tval = hns3_read_dev(hw, HNS3_VF_RST_ING);\n+\t\thns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);\n+\t\tval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);\n+\t\tif (clearval) {\n+\t\t\thw->reset.stats.global_cnt++;\n+\t\t\thns3_warn(hw, \"Global reset detected, clear reset status\");\n+\t\t} else {\n+\t\t\thns3_schedule_delayed_reset(hns);\n+\t\t\thns3_warn(hw, \"Global reset detected, don't clear reset status\");\n+\t\t}\n+\n+\t\tret = HNS3VF_VECTOR0_EVENT_RST;\n+\t\tgoto out;\n+\t}\n+\n \t/* Check for vector0 mailbox(=CMDQ RX) event source */\n \tif (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {\n \t\tval = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);\n@@ -567,6 +601,9 @@ hns3vf_interrupt_handler(void *param)\n \tevent_cause = hns3vf_check_event_cause(hns, &clearval);\n \n \tswitch (event_cause) {\n+\tcase HNS3VF_VECTOR0_EVENT_RST:\n+\t\thns3_schedule_reset(hns);\n+\t\tbreak;\n \tcase HNS3VF_VECTOR0_EVENT_MBX:\n \t\thns3_dev_handle_mbx_msg(hw);\n \t\tbreak;\n@@ -742,6 +779,12 @@ hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n \tstruct hns3_hw *hw = &hns->hw;\n \tint ret;\n \n+\tif (rte_atomic16_read(&hw->reset.resetting)) {\n+\t\thns3_err(hw,\n+\t\t\t \"vf set vlan id failed during resetting, vlan_id =%u\",\n+\t\t\t vlan_id);\n+\t\treturn -EIO;\n+\t}\n \trte_spinlock_lock(&hw->lock);\n \tret = hns3vf_vlan_filter_configure(hns, vlan_id, on);\n \trte_spinlock_unlock(&hw->lock);\n@@ -790,6 +833,73 @@ hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n }\n \n static int\n+hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)\n+{\n+\tstruct rte_vlan_filter_conf *vfc;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint16_t vlan_id;\n+\tuint64_t vbit;\n+\tuint64_t ids;\n+\tint ret = 0;\n+\tuint32_t i;\n+\n+\tvfc = &hw->data->vlan_filter_conf;\n+\tfor (i = 0; i < RTE_DIM(vfc->ids); i++) {\n+\t\tif (vfc->ids[i] == 0)\n+\t\t\tcontinue;\n+\t\tids = vfc->ids[i];\n+\t\twhile (ids) {\n+\t\t\t/*\n+\t\t\t * 64 means the num bits of ids, one bit corresponds to\n+\t\t\t * one vlan id\n+\t\t\t */\n+\t\t\tvlan_id = 64 * i;\n+\t\t\t/* count trailing zeroes */\n+\t\t\tvbit = ~ids & (ids - 1);\n+\t\t\t/* clear least significant bit set */\n+\t\t\tids ^= (ids ^ (ids - 1)) ^ vbit;\n+\t\t\tfor (; vbit;) {\n+\t\t\t\tvbit >>= 1;\n+\t\t\t\tvlan_id++;\n+\t\t\t}\n+\t\t\tret = hns3vf_vlan_filter_configure(hns, vlan_id, on);\n+\t\t\tif (ret) {\n+\t\t\t\thns3_err(hw,\n+\t\t\t\t\t \"VF handle vlan table failed, ret =%d, on = %d\",\n+\t\t\t\t\t ret, on);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)\n+{\n+\treturn hns3vf_handle_all_vlan_table(hns, 0);\n+}\n+\n+static int\n+hns3vf_restore_vlan_conf(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_eth_conf *dev_conf;\n+\tbool en;\n+\tint ret;\n+\n+\tdev_conf = &hw->data->dev_conf;\n+\ten = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true\n+\t\t\t\t\t\t\t\t : false;\n+\tret = hns3vf_en_hw_strip_rxvtag(hw, en);\n+\tif (ret)\n+\t\thns3_err(hw, \"VF restore vlan conf fail, en =%d, ret =%d\", en,\n+\t\t\t ret);\n+\treturn ret;\n+}\n+\n+static int\n hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)\n {\n \tstruct hns3_adapter *hns = dev->data->dev_private;\n@@ -848,7 +958,19 @@ hns3vf_service_handler(void *param)\n \tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n \tstruct hns3_hw *hw = &hns->hw;\n \n-\thns3vf_request_link_info(hw);\n+\t/*\n+\t * The query link status and reset processing are executed in the\n+\t * interrupt thread.When the IMP reset occurs, IMP will not respond,\n+\t * and the query operation will time out after 30ms. In the case of\n+\t * multiple PF/VFs, each query failure timeout causes the IMP reset\n+\t * interrupt to fail to respond within 100ms.\n+\t * Before querying the link status, check whether there is a reset\n+\t * pending, and if so, abandon the query.\n+\t */\n+\tif (!hns3vf_is_reset_pending(hns))\n+\t\thns3vf_request_link_info(hw);\n+\telse\n+\t\thns3_warn(hw, \"Cancel the query when reset is pending\");\n \n \trte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,\n \t\t\t eth_dev);\n@@ -997,12 +1119,16 @@ static int\n hns3vf_do_stop(struct hns3_adapter *hns)\n {\n \tstruct hns3_hw *hw = &hns->hw;\n+\tbool reset_queue;\n \n \thw->mac.link_status = ETH_LINK_DOWN;\n \n-\thns3vf_configure_mac_addr(hns, true);\n-\n-\treturn 0;\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {\n+\t\thns3vf_configure_mac_addr(hns, true);\n+\t\treset_queue = true;\n+\t} else\n+\t\treset_queue = false;\n+\treturn hns3_stop_queues(hns, reset_queue);\n }\n \n static void\n@@ -1017,9 +1143,11 @@ hns3vf_dev_stop(struct rte_eth_dev *eth_dev)\n \thns3_set_rxtx_function(eth_dev);\n \n \trte_spinlock_lock(&hw->lock);\n-\thns3vf_do_stop(hns);\n-\thns3_dev_release_mbufs(hns);\n-\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\tif (rte_atomic16_read(&hw->reset.resetting) == 0) {\n+\t\thns3vf_do_stop(hns);\n+\t\thns3_dev_release_mbufs(hns);\n+\t\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\t}\n \trte_spinlock_unlock(&hw->lock);\n }\n \n@@ -1033,14 +1161,17 @@ hns3vf_dev_close(struct rte_eth_dev *eth_dev)\n \t\thns3vf_dev_stop(eth_dev);\n \n \thw->adapter_state = HNS3_NIC_CLOSING;\n+\thns3_reset_abort(hns);\n+\thw->adapter_state = HNS3_NIC_CLOSED;\n \trte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);\n \trte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);\n \thns3vf_configure_all_mc_mac_addr(hns, true);\n+\thns3vf_remove_all_vlan_table(hns);\n \thns3vf_uninit_vf(eth_dev);\n \thns3_free_all_queues(eth_dev);\n+\trte_free(hw->reset.wait_data);\n \trte_free(eth_dev->process_private);\n \teth_dev->process_private = NULL;\n-\thw->adapter_state = HNS3_NIC_CLOSED;\n \thns3_warn(hw, \"Close port %d finished\", hw->data->port_id);\n }\n \n@@ -1105,6 +1236,8 @@ hns3vf_dev_start(struct rte_eth_dev *eth_dev)\n \tint ret;\n \n \tPMD_INIT_FUNC_TRACE();\n+\tif (rte_atomic16_read(&hw->reset.resetting))\n+\t\treturn -EBUSY;\n \trte_spinlock_lock(&hw->lock);\n \thw->adapter_state = HNS3_NIC_STARTING;\n \tret = hns3vf_do_start(hns, true);\n@@ -1119,6 +1252,265 @@ hns3vf_dev_start(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static bool\n+is_vf_reset_done(struct hns3_hw *hw)\n+{\n+#define HNS3_FUN_RST_ING_BITS \\\n+\t(BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \\\n+\t BIT(HNS3_VECTOR0_CORERESET_INT_B) | \\\n+\t BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \\\n+\t BIT(HNS3_VECTOR0_FUNCRESET_INT_B))\n+\n+\tuint32_t val;\n+\n+\tif (hw->reset.level == HNS3_VF_RESET) {\n+\t\tval = hns3_read_dev(hw, HNS3_VF_RST_ING);\n+\t\tif (val & HNS3_VF_RST_ING_BIT)\n+\t\t\treturn false;\n+\t} else {\n+\t\tval = hns3_read_dev(hw, HNS3_FUN_RST_ING);\n+\t\tif (val & HNS3_FUN_RST_ING_BITS)\n+\t\t\treturn false;\n+\t}\n+\treturn true;\n+}\n+\n+bool\n+hns3vf_is_reset_pending(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_reset_level reset;\n+\n+\thns3vf_check_event_cause(hns, NULL);\n+\treset = hns3vf_get_reset_level(hw, &hw->reset.pending);\n+\tif (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {\n+\t\thns3_warn(hw, \"High level reset %d is pending\", reset);\n+\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static int\n+hns3vf_wait_hardware_ready(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_wait_data *wait_data = hw->reset.wait_data;\n+\tstruct timeval tv;\n+\n+\tif (wait_data->result == HNS3_WAIT_SUCCESS)\n+\t\treturn 0;\n+\telse if (wait_data->result == HNS3_WAIT_TIMEOUT) {\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_warn(hw, \"Reset step4 hardware not ready after reset time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\treturn -ETIME;\n+\t} else if (wait_data->result == HNS3_WAIT_REQUEST)\n+\t\treturn -EAGAIN;\n+\n+\twait_data->hns = hns;\n+\twait_data->check_completion = is_vf_reset_done;\n+\twait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *\n+\t\t\t\t HNS3VF_RESET_WAIT_MS + get_timeofday_ms();\n+\twait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;\n+\twait_data->count = HNS3VF_RESET_WAIT_CNT;\n+\twait_data->result = HNS3_WAIT_REQUEST;\n+\trte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);\n+\treturn -EAGAIN;\n+}\n+\n+static int\n+hns3vf_prepare_reset(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret = 0;\n+\n+\tif (hw->reset.level == HNS3_VF_FUNC_RESET) {\n+\t\tret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,\n+\t\t\t\t\t0, true, NULL, 0);\n+\t}\n+\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\n+\treturn ret;\n+}\n+\n+static int\n+hns3vf_stop_service(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\teth_dev = &rte_eth_devices[hw->data->port_id];\n+\trte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);\n+\thw->mac.link_status = ETH_LINK_DOWN;\n+\n+\thns3_set_rxtx_function(eth_dev);\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tif (hw->adapter_state == HNS3_NIC_STARTED ||\n+\t hw->adapter_state == HNS3_NIC_STOPPING) {\n+\t\thns3vf_do_stop(hns);\n+\t\thw->reset.mbuf_deferred_free = true;\n+\t} else\n+\t\thw->reset.mbuf_deferred_free = false;\n+\n+\t/*\n+\t * It is cumbersome for hardware to pick-and-choose entries for deletion\n+\t * from table space. Hence, for function reset software intervention is\n+\t * required to delete the entries.\n+\t */\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd) == 0)\n+\t\thns3vf_configure_all_mc_mac_addr(hns, true);\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_start_service(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\teth_dev = &rte_eth_devices[hw->data->port_id];\n+\thns3_set_rxtx_function(eth_dev);\n+\n+\thns3vf_service_handler(eth_dev);\n+\treturn 0;\n+}\n+\n+static int\n+hns3vf_restore_conf(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = hns3vf_configure_mac_addr(hns, false);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = hns3vf_configure_all_mc_mac_addr(hns, false);\n+\tif (ret)\n+\t\tgoto err_mc_mac;\n+\n+\tret = hns3vf_restore_vlan_conf(hns);\n+\tif (ret)\n+\t\tgoto err_vlan_table;\n+\n+\tif (hw->adapter_state == HNS3_NIC_STARTED) {\n+\t\tret = hns3vf_do_start(hns, false);\n+\t\tif (ret)\n+\t\t\tgoto err_vlan_table;\n+\t\thns3_info(hw, \"hns3vf dev restart successful!\");\n+\t} else if (hw->adapter_state == HNS3_NIC_STOPPING)\n+\t\thw->adapter_state = HNS3_NIC_CONFIGURED;\n+\treturn 0;\n+\n+err_vlan_table:\n+\thns3vf_configure_all_mc_mac_addr(hns, true);\n+err_mc_mac:\n+\thns3vf_configure_mac_addr(hns, true);\n+\treturn ret;\n+}\n+\n+static enum hns3_reset_level\n+hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)\n+{\n+\tenum hns3_reset_level reset_level;\n+\n+\t/* return the highest priority reset level amongst all */\n+\tif (hns3_atomic_test_bit(HNS3_VF_RESET, levels))\n+\t\treset_level = HNS3_VF_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))\n+\t\treset_level = HNS3_VF_FULL_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))\n+\t\treset_level = HNS3_VF_PF_FUNC_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))\n+\t\treset_level = HNS3_VF_FUNC_RESET;\n+\telse if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))\n+\t\treset_level = HNS3_FLR_RESET;\n+\telse\n+\t\treset_level = HNS3_NONE_RESET;\n+\n+\tif (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)\n+\t\treturn HNS3_NONE_RESET;\n+\n+\treturn reset_level;\n+}\n+\n+static void\n+hns3vf_reset_service(void *param)\n+{\n+\tstruct hns3_adapter *hns = (struct hns3_adapter *)param;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_reset_level reset_level;\n+\tstruct timeval tv_delta;\n+\tstruct timeval tv_start;\n+\tstruct timeval tv;\n+\tuint64_t msec;\n+\n+\t/*\n+\t * The interrupt is not triggered within the delay time.\n+\t * The interrupt may have been lost. It is necessary to handle\n+\t * the interrupt to recover from the error.\n+\t */\n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {\n+\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\t\thns3_err(hw, \"Handling interrupts in delayed tasks\");\n+\t\thns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);\n+\t}\n+\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);\n+\n+\t/*\n+\t * Hardware reset has been notified, we now have to poll & check if\n+\t * hardware has actually completed the reset sequence.\n+\t */\n+\treset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);\n+\tif (reset_level != HNS3_NONE_RESET) {\n+\t\tgettimeofday(&tv_start, NULL);\n+\t\thns3_reset_process(hns, reset_level);\n+\t\tgettimeofday(&tv, NULL);\n+\t\ttimersub(&tv, &tv_start, &tv_delta);\n+\t\tmsec = tv_delta.tv_sec * MSEC_PER_SEC +\n+\t\t tv_delta.tv_usec / USEC_PER_MSEC;\n+\t\tif (msec > HNS3_RESET_PROCESS_MS)\n+\t\t\thns3_err(hw, \"%d handle long time delta %\" PRIx64\n+\t\t\t\t \" ms time=%ld.%.6ld\",\n+\t\t\t\t hw->reset.level, msec, tv.tv_sec, tv.tv_usec);\n+\t}\n+}\n+\n+static int\n+hns3vf_reinit_dev(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\t/* Firmware command initialize */\n+\tret = hns3_cmd_init(hw);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to init cmd: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hns3_reset_all_queues(hns);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to reset all queues: %d\", ret);\n+\t\tgoto err_init;\n+\t}\n+\n+\tret = hns3vf_init_hardware(hns);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Failed to init hardware: %d\", ret);\n+\t\tgoto err_init;\n+\t}\n+\n+\treturn 0;\n+\n+err_init:\n+\thns3_cmd_uninit(hw);\n+\treturn ret;\n+}\n+\n static const struct eth_dev_ops hns3vf_eth_dev_ops = {\n \t.dev_start = hns3vf_dev_start,\n \t.dev_stop = hns3vf_dev_stop,\n@@ -1153,6 +1545,16 @@ static const struct eth_dev_ops hns3vf_eth_dev_ops = {\n \t.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,\n };\n \n+static const struct hns3_reset_ops hns3vf_reset_ops = {\n+\t.reset_service = hns3vf_reset_service,\n+\t.stop_service = hns3vf_stop_service,\n+\t.prepare_reset = hns3vf_prepare_reset,\n+\t.wait_hardware_ready = hns3vf_wait_hardware_ready,\n+\t.reinit_dev = hns3vf_reinit_dev,\n+\t.restore_conf = hns3vf_restore_conf,\n+\t.start_service = hns3vf_start_service,\n+};\n+\n static int\n hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n {\n@@ -1183,6 +1585,11 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n \thns->is_vf = true;\n \thw->data = eth_dev->data;\n \n+\tret = hns3_reset_init(hw);\n+\tif (ret)\n+\t\tgoto err_init_reset;\n+\thw->reset.ops = &hns3vf_reset_ops;\n+\n \tret = hns3vf_init_vf(eth_dev);\n \tif (ret) {\n \t\tPMD_INIT_LOG(ERR, \"Failed to init vf: %d\", ret);\n@@ -1211,6 +1618,13 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n \t */\n \teth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;\n \n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {\n+\t\thns3_err(hw, \"Reschedule reset service after dev_init\");\n+\t\thns3_schedule_reset(hns);\n+\t} else {\n+\t\t/* IMP will wait ready flag before reset */\n+\t\thns3_notify_reset_ready(hw, false);\n+\t}\n \trte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,\n \t\t\t eth_dev);\n \trte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,\n@@ -1221,6 +1635,9 @@ hns3vf_dev_init(struct rte_eth_dev *eth_dev)\n \thns3vf_uninit_vf(eth_dev);\n \n err_init_vf:\n+\trte_free(hw->reset.wait_data);\n+\n+err_init_reset:\n \teth_dev->dev_ops = NULL;\n \teth_dev->rx_pkt_burst = NULL;\n \teth_dev->tx_pkt_burst = NULL;\ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nindex 3cf52a2..9e2d811 100644\n--- a/drivers/net/hns3/hns3_intr.c\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -33,6 +33,11 @@\n \t\t\thw->reset.stats.merge_cnt++;\t\\\n \t} while (0)\n \n+static const char *reset_string[HNS3_MAX_RESET] = {\n+\t\"none\",\t\"vf_func\", \"vf_pf_func\", \"vf_full\", \"flr\",\n+\t\"vf_global\", \"pf_func\", \"global\", \"IMP\",\n+};\n+\n const struct hns3_hw_error mac_afifo_tnl_int[] = {\n \t{ .int_msk = BIT(0), .msg = \"egu_cge_afifo_ecc_1bit_err\",\n \t .reset_level = HNS3_NONE_RESET },\n@@ -652,3 +657,510 @@ hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)\n out:\n \trte_free(desc);\n }\n+\n+int\n+hns3_reset_init(struct hns3_hw *hw)\n+{\n+\trte_spinlock_init(&hw->lock);\n+\thw->reset.level = HNS3_NONE_RESET;\n+\thw->reset.stage = RESET_STAGE_NONE;\n+\thw->reset.request = 0;\n+\thw->reset.pending = 0;\n+\trte_atomic16_init(&hw->reset.resetting);\n+\trte_atomic16_init(&hw->reset.disable_cmd);\n+\thw->reset.wait_data = rte_zmalloc(\"wait_data\",\n+\t\t\t\t\t sizeof(struct hns3_wait_data), 0);\n+\tif (!hw->reset.wait_data) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for wait_data\");\n+\t\treturn -ENOMEM;\n+\t}\n+\treturn 0;\n+}\n+\n+void\n+hns3_schedule_reset(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\t/* Reschedule the reset process after successful initialization */\n+\tif (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {\n+\t\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING);\n+\t\treturn;\n+\t}\n+\n+\tif (hw->adapter_state >= HNS3_NIC_CLOSED)\n+\t\treturn;\n+\n+\t/* Schedule restart alarm if it is not scheduled yet */\n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED)\n+\t\treturn;\n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED)\n+\t\trte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);\n+\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);\n+\n+\trte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);\n+}\n+\n+void\n+hns3_schedule_delayed_reset(struct hns3_adapter *hns)\n+{\n+#define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC)\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\t/* Do nothing if it is uninited or closed */\n+\tif (hw->adapter_state == HNS3_NIC_UNINITIALIZED ||\n+\t hw->adapter_state >= HNS3_NIC_CLOSED) {\n+\t\treturn;\n+\t}\n+\n+\tif (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE)\n+\t\treturn;\n+\trte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED);\n+\trte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);\n+}\n+\n+void\n+hns3_wait_callback(void *param)\n+{\n+\tstruct hns3_wait_data *data = (struct hns3_wait_data *)param;\n+\tstruct hns3_adapter *hns = data->hns;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint64_t msec;\n+\tbool done;\n+\n+\tdata->count--;\n+\tif (data->check_completion) {\n+\t\t/*\n+\t\t * Check if the current time exceeds the deadline\n+\t\t * or a pending reset coming, or reset during close.\n+\t\t */\n+\t\tmsec = get_timeofday_ms();\n+\t\tif (msec > data->end_ms || is_reset_pending(hns) ||\n+\t\t hw->adapter_state == HNS3_NIC_CLOSING) {\n+\t\t\tdone = false;\n+\t\t\tdata->count = 0;\n+\t\t} else\n+\t\t\tdone = data->check_completion(hw);\n+\t} else\n+\t\tdone = true;\n+\n+\tif (!done && data->count > 0) {\n+\t\trte_eal_alarm_set(data->interval, hns3_wait_callback, data);\n+\t\treturn;\n+\t}\n+\tif (done)\n+\t\tdata->result = HNS3_WAIT_SUCCESS;\n+\telse {\n+\t\thns3_err(hw, \"%s wait timeout at stage %d\",\n+\t\t\t reset_string[hw->reset.level], hw->reset.stage);\n+\t\tdata->result = HNS3_WAIT_TIMEOUT;\n+\t}\n+\thns3_schedule_reset(hns);\n+}\n+\n+void\n+hns3_notify_reset_ready(struct hns3_hw *hw, bool enable)\n+{\n+\tuint32_t reg_val;\n+\n+\treg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG);\n+\tif (enable)\n+\t\treg_val |= HNS3_NIC_SW_RST_RDY;\n+\telse\n+\t\treg_val &= ~HNS3_NIC_SW_RST_RDY;\n+\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val);\n+}\n+\n+int\n+hns3_reset_req_hw_reset(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tif (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) {\n+\t\thw->reset.wait_data->hns = hns;\n+\t\thw->reset.wait_data->check_completion = NULL;\n+\t\thw->reset.wait_data->interval = HNS3_RESET_SYNC_US;\n+\t\thw->reset.wait_data->count = 1;\n+\t\thw->reset.wait_data->result = HNS3_WAIT_REQUEST;\n+\t\trte_eal_alarm_set(hw->reset.wait_data->interval,\n+\t\t\t\t hns3_wait_callback, hw->reset.wait_data);\n+\t\treturn -EAGAIN;\n+\t} else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)\n+\t\treturn -EAGAIN;\n+\n+\t/* inform hardware that preparatory work is done */\n+\thns3_notify_reset_ready(hw, true);\n+\treturn 0;\n+}\n+\n+static void\n+hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)\n+{\n+\tuint64_t merge_cnt = hw->reset.stats.merge_cnt;\n+\tint64_t tmp;\n+\n+\tswitch (hw->reset.level) {\n+\tcase HNS3_IMP_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_IMP_RESET, levels);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\tbreak;\n+\tcase HNS3_GLOBAL_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\tbreak;\n+\tcase HNS3_FUNC_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_FUNC_RESET, levels);\n+\t\tbreak;\n+\tcase HNS3_VF_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_VF_RESET, levels);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\tbreak;\n+\tcase HNS3_VF_FULL_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\tbreak;\n+\tcase HNS3_VF_PF_FUNC_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels);\n+\t\ttmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels);\n+\t\tHNS3_CHECK_MERGE_CNT(tmp);\n+\t\tbreak;\n+\tcase HNS3_VF_FUNC_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels);\n+\t\tbreak;\n+\tcase HNS3_FLR_RESET:\n+\t\thns3_atomic_clear_bit(HNS3_FLR_RESET, levels);\n+\t\tbreak;\n+\tcase HNS3_NONE_RESET:\n+\tdefault:\n+\t\treturn;\n+\t};\n+\tif (merge_cnt != hw->reset.stats.merge_cnt)\n+\t\thns3_warn(hw,\n+\t\t\t \"No need to do low-level reset after %s reset. \"\n+\t\t\t \"merge cnt: %\" PRIx64 \" total merge cnt: %\" PRIx64,\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t hw->reset.stats.merge_cnt - merge_cnt,\n+\t\t\t hw->reset.stats.merge_cnt);\n+}\n+\n+static bool\n+hns3_reset_err_handle(struct hns3_adapter *hns)\n+{\n+#define MAX_RESET_FAIL_CNT 5\n+\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tif (hw->adapter_state == HNS3_NIC_CLOSING)\n+\t\tgoto reset_fail;\n+\n+\tif (is_reset_pending(hns)) {\n+\t\thw->reset.attempts = 0;\n+\t\thw->reset.stats.fail_cnt++;\n+\t\thns3_warn(hw, \"%s reset fail because new Reset is pending \"\n+\t\t\t \"attempts:%\" PRIx64,\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t hw->reset.stats.fail_cnt);\n+\t\thw->reset.level = HNS3_NONE_RESET;\n+\t\treturn true;\n+\t}\n+\n+\thw->reset.attempts++;\n+\tif (hw->reset.attempts < MAX_RESET_FAIL_CNT) {\n+\t\thns3_atomic_set_bit(hw->reset.level, &hw->reset.pending);\n+\t\thns3_warn(hw, \"%s retry to reset attempts: %d\",\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t hw->reset.attempts);\n+\t\treturn true;\n+\t}\n+\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd))\n+\t\thns3_cmd_init(hw);\n+reset_fail:\n+\thw->reset.attempts = 0;\n+\thw->reset.stats.fail_cnt++;\n+\thns3_warn(hw, \"%s reset fail fail_cnt:%\" PRIx64 \" success_cnt:%\" PRIx64\n+\t\t \" global_cnt:%\" PRIx64 \" imp_cnt:%\" PRIx64\n+\t\t \" request_cnt:%\" PRIx64 \" exec_cnt:%\" PRIx64\n+\t\t \" merge_cnt:%\" PRIx64,\n+\t\t reset_string[hw->reset.level], hw->reset.stats.fail_cnt,\n+\t\t hw->reset.stats.success_cnt, hw->reset.stats.global_cnt,\n+\t\t hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt,\n+\t\t hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt);\n+\n+\t/* IMP no longer waiting the ready flag */\n+\thns3_notify_reset_ready(hw, true);\n+\treturn false;\n+}\n+\n+static int\n+hns3_reset_pre(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct timeval tv;\n+\tint ret;\n+\n+\tif (hw->reset.stage == RESET_STAGE_NONE) {\n+\t\trte_atomic16_set(&hns->hw.reset.resetting, 1);\n+\t\thw->reset.stage = RESET_STAGE_DOWN;\n+\t\tret = hw->reset.ops->stop_service(hns);\n+\t\tgettimeofday(&tv, NULL);\n+\t\tif (ret) {\n+\t\t\thns3_warn(hw, \"Reset step1 down fail=%d time=%ld.%.6ld\",\n+\t\t\t\t ret, tv.tv_sec, tv.tv_usec);\n+\t\t\treturn ret;\n+\t\t}\n+\t\thns3_warn(hw, \"Reset step1 down success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.stage = RESET_STAGE_PREWAIT;\n+\t}\n+\tif (hw->reset.stage == RESET_STAGE_PREWAIT) {\n+\t\tret = hw->reset.ops->prepare_reset(hns);\n+\t\tgettimeofday(&tv, NULL);\n+\t\tif (ret) {\n+\t\t\thns3_warn(hw,\n+\t\t\t\t \"Reset step2 prepare wait fail=%d time=%ld.%.6ld\",\n+\t\t\t\t ret, tv.tv_sec, tv.tv_usec);\n+\t\t\treturn ret;\n+\t\t}\n+\t\thns3_warn(hw, \"Reset step2 prepare wait success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.stage = RESET_STAGE_REQ_HW_RESET;\n+\t\thw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+hns3_reset_post(struct hns3_adapter *hns)\n+{\n+#define TIMEOUT_RETRIES_CNT\t5\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct timeval tv_delta;\n+\tstruct timeval tv;\n+\tint ret = 0;\n+\n+\tif (hw->adapter_state == HNS3_NIC_CLOSING) {\n+\t\thns3_warn(hw, \"Don't do reset_post during closing, just uninit cmd\");\n+\t\thns3_cmd_uninit(hw);\n+\t\treturn -EPERM;\n+\t}\n+\n+\tif (hw->reset.stage == RESET_STAGE_DEV_INIT) {\n+\t\trte_spinlock_lock(&hw->lock);\n+\t\tif (hw->reset.mbuf_deferred_free) {\n+\t\t\thns3_dev_release_mbufs(hns);\n+\t\t\thw->reset.mbuf_deferred_free = false;\n+\t\t}\n+\t\tret = hw->reset.ops->reinit_dev(hns);\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t\tgettimeofday(&tv, NULL);\n+\t\tif (ret) {\n+\t\t\thns3_warn(hw, \"Reset step5 devinit fail=%d retries=%d\",\n+\t\t\t\t ret, hw->reset.retries);\n+\t\t\tgoto err;\n+\t\t}\n+\t\thns3_warn(hw, \"Reset step5 devinit success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.retries = 0;\n+\t\thw->reset.stage = RESET_STAGE_RESTORE;\n+\t\trte_eal_alarm_set(SWITCH_CONTEXT_US,\n+\t\t\t\t hw->reset.ops->reset_service, hns);\n+\t\treturn -EAGAIN;\n+\t}\n+\tif (hw->reset.stage == RESET_STAGE_RESTORE) {\n+\t\trte_spinlock_lock(&hw->lock);\n+\t\tret = hw->reset.ops->restore_conf(hns);\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t\tgettimeofday(&tv, NULL);\n+\t\tif (ret) {\n+\t\t\thns3_warn(hw,\n+\t\t\t\t \"Reset step6 restore fail=%d retries=%d\",\n+\t\t\t\t ret, hw->reset.retries);\n+\t\t\tgoto err;\n+\t\t}\n+\t\thns3_warn(hw, \"Reset step6 restore success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.retries = 0;\n+\t\thw->reset.stage = RESET_STAGE_DONE;\n+\t}\n+\tif (hw->reset.stage == RESET_STAGE_DONE) {\n+\t\t/* IMP will wait ready flag before reset */\n+\t\thns3_notify_reset_ready(hw, false);\n+\t\thns3_clear_reset_level(hw, &hw->reset.pending);\n+\t\trte_atomic16_clear(&hns->hw.reset.resetting);\n+\t\thw->reset.attempts = 0;\n+\t\thw->reset.stats.success_cnt++;\n+\t\thw->reset.stage = RESET_STAGE_NONE;\n+\t\thw->reset.ops->start_service(hns);\n+\t\tgettimeofday(&tv, NULL);\n+\t\ttimersub(&tv, &hw->reset.start_time, &tv_delta);\n+\t\thns3_warn(hw, \"%s reset done fail_cnt:%\" PRIx64\n+\t\t\t \" success_cnt:%\" PRIx64 \" global_cnt:%\" PRIx64\n+\t\t\t \" imp_cnt:%\" PRIx64 \" request_cnt:%\" PRIx64\n+\t\t\t \" exec_cnt:%\" PRIx64 \" merge_cnt:%\" PRIx64,\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt,\n+\t\t\t hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt,\n+\t\t\t hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt,\n+\t\t\t hw->reset.stats.merge_cnt);\n+\t\thns3_warn(hw,\n+\t\t\t \"%s reset done delta %ld ms time=%ld.%.6ld\",\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t tv_delta.tv_sec * MSEC_PER_SEC +\n+\t\t\t tv_delta.tv_usec / USEC_PER_MSEC,\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.level = HNS3_NONE_RESET;\n+\t}\n+\treturn 0;\n+\n+err:\n+\tif (ret == -ETIME) {\n+\t\thw->reset.retries++;\n+\t\tif (hw->reset.retries < TIMEOUT_RETRIES_CNT) {\n+\t\t\trte_eal_alarm_set(HNS3_RESET_SYNC_US,\n+\t\t\t\t\t hw->reset.ops->reset_service, hns);\n+\t\t\treturn -EAGAIN;\n+\t\t}\n+\t}\n+\thw->reset.retries = 0;\n+\treturn -EIO;\n+}\n+\n+/*\n+ * There are three scenarios as follows:\n+ * When the reset is not in progress, the reset process starts.\n+ * During the reset process, if the reset level has not changed,\n+ * the reset process continues; otherwise, the reset process is aborted.\n+ *\thw->reset.level new_level action\n+ *\tHNS3_NONE_RESET\t HNS3_XXXX_RESET start reset\n+ *\tHNS3_XXXX_RESET HNS3_XXXX_RESET continue reset\n+ *\tHNS3_LOW_RESET HNS3_HIGH_RESET abort\n+ */\n+int\n+hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct timeval tv_delta;\n+\tstruct timeval tv;\n+\tint ret;\n+\n+\tif (hw->reset.level == HNS3_NONE_RESET) {\n+\t\thw->reset.level = new_level;\n+\t\thw->reset.stats.exec_cnt++;\n+\t\tgettimeofday(&hw->reset.start_time, NULL);\n+\t\thns3_warn(hw, \"Start %s reset time=%ld.%.6ld\",\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t hw->reset.start_time.tv_sec,\n+\t\t\t hw->reset.start_time.tv_usec);\n+\t}\n+\n+\tif (is_reset_pending(hns)) {\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_warn(hw,\n+\t\t\t \"%s reset is aborted by high level time=%ld.%.6ld\",\n+\t\t\t reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);\n+\t\tif (hw->reset.wait_data->result == HNS3_WAIT_REQUEST)\n+\t\t\trte_eal_alarm_cancel(hns3_wait_callback,\n+\t\t\t\t\t hw->reset.wait_data);\n+\t\tret = -EBUSY;\n+\t\tgoto err;\n+\t}\n+\n+\tret = hns3_reset_pre(hns);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tif (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) {\n+\t\tret = hns3_reset_req_hw_reset(hns);\n+\t\tif (ret == -EAGAIN)\n+\t\t\treturn ret;\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_warn(hw,\n+\t\t\t \"Reset step3 request IMP reset success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.stage = RESET_STAGE_WAIT;\n+\t\thw->reset.wait_data->result = HNS3_WAIT_UNKNOWN;\n+\t}\n+\tif (hw->reset.stage == RESET_STAGE_WAIT) {\n+\t\tret = hw->reset.ops->wait_hardware_ready(hns);\n+\t\tif (ret)\n+\t\t\tgoto retry;\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_warn(hw, \"Reset step4 reset wait success time=%ld.%.6ld\",\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.stage = RESET_STAGE_DEV_INIT;\n+\t}\n+\n+\tret = hns3_reset_post(hns);\n+\tif (ret)\n+\t\tgoto retry;\n+\n+\treturn 0;\n+retry:\n+\tif (ret == -EAGAIN)\n+\t\treturn ret;\n+err:\n+\thns3_clear_reset_level(hw, &hw->reset.pending);\n+\tif (hns3_reset_err_handle(hns)) {\n+\t\thw->reset.stage = RESET_STAGE_PREWAIT;\n+\t\thns3_schedule_reset(hns);\n+\t} else {\n+\t\trte_spinlock_lock(&hw->lock);\n+\t\tif (hw->reset.mbuf_deferred_free) {\n+\t\t\thns3_dev_release_mbufs(hns);\n+\t\t\thw->reset.mbuf_deferred_free = false;\n+\t\t}\n+\t\trte_spinlock_unlock(&hw->lock);\n+\t\trte_atomic16_clear(&hns->hw.reset.resetting);\n+\t\thw->reset.stage = RESET_STAGE_NONE;\n+\t\tgettimeofday(&tv, NULL);\n+\t\ttimersub(&tv, &hw->reset.start_time, &tv_delta);\n+\t\thns3_warn(hw, \"%s reset fail delta %ld ms time=%ld.%.6ld\",\n+\t\t\t reset_string[hw->reset.level],\n+\t\t\t tv_delta.tv_sec * MSEC_PER_SEC +\n+\t\t\t tv_delta.tv_usec / USEC_PER_MSEC,\n+\t\t\t tv.tv_sec, tv.tv_usec);\n+\t\thw->reset.level = HNS3_NONE_RESET;\n+\t}\n+\n+\treturn -EIO;\n+}\n+\n+/*\n+ * The reset process can only be terminated after handshake with IMP(step3),\n+ * so that IMP can complete the reset process normally.\n+ */\n+void\n+hns3_reset_abort(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct timeval tv;\n+\tint i;\n+\n+\tfor (i = 0; i < HNS3_QUIT_RESET_CNT; i++) {\n+\t\tif (hw->reset.level == HNS3_NONE_RESET)\n+\t\t\tbreak;\n+\t\trte_delay_ms(HNS3_QUIT_RESET_DELAY_MS);\n+\t}\n+\n+\t/* IMP no longer waiting the ready flag */\n+\thns3_notify_reset_ready(hw, true);\n+\n+\trte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);\n+\trte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data);\n+\n+\tif (hw->reset.level != HNS3_NONE_RESET) {\n+\t\tgettimeofday(&tv, NULL);\n+\t\thns3_err(hw, \"Failed to terminate reset: %s time=%ld.%.6ld\",\n+\t\t\t reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec);\n+\t}\n+}\ndiff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h\nindex b57b4ac..d0af16c 100644\n--- a/drivers/net/hns3/hns3_intr.h\n+++ b/drivers/net/hns3/hns3_intr.h\n@@ -49,6 +49,8 @@\n #define HNS3_SSU_COMMON_ERR_INT_MASK\t\tGENMASK(9, 0)\n #define HNS3_SSU_PORT_INT_MSIX_MASK\t\t0x7BFF\n \n+#define HNS3_RESET_PROCESS_MS\t\t\t200\n+\n struct hns3_hw_blk {\n \tconst char *name;\n \tint (*enable_err_intr)(struct hns3_adapter *hns, bool en);\n@@ -64,5 +66,14 @@ int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);\n void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);\n void hns3_intr_unregister(const struct rte_intr_handle *hdl,\n \t\t\t rte_intr_callback_fn cb_fn, void *cb_arg);\n+void hns3_notify_reset_ready(struct hns3_hw *hw, bool enable);\n+int hns3_reset_init(struct hns3_hw *hw);\n+void hns3_wait_callback(void *param);\n+void hns3_schedule_reset(struct hns3_adapter *hns);\n+void hns3_schedule_delayed_reset(struct hns3_adapter *hns);\n+int hns3_reset_req_hw_reset(struct hns3_adapter *hns);\n+int hns3_reset_process(struct hns3_adapter *hns,\n+\t\t enum hns3_reset_level reset_level);\n+void hns3_reset_abort(struct hns3_adapter *hns);\n \n #endif /* _HNS3_INTR_H_ */\ndiff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c\nindex c03e71d..2bfd974 100644\n--- a/drivers/net/hns3/hns3_mbx.c\n+++ b/drivers/net/hns3/hns3_mbx.c\n@@ -81,6 +81,7 @@ hns3_get_mbx_resp(struct hns3_hw *hw, uint16_t code0, uint16_t code1,\n \t\t uint8_t *resp_data, uint16_t resp_len)\n {\n #define HNS3_MAX_RETRY_MS\t500\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n \tstruct hns3_mbx_resp_status *mbx_resp;\n \tbool in_irq = false;\n \tuint64_t now;\n@@ -96,6 +97,19 @@ hns3_get_mbx_resp(struct hns3_hw *hw, uint16_t code0, uint16_t code1,\n \tend = now + HNS3_MAX_RETRY_MS;\n \twhile ((hw->mbx_resp.head != hw->mbx_resp.tail + hw->mbx_resp.lost) &&\n \t (now < end)) {\n+\t\tif (rte_atomic16_read(&hw->reset.disable_cmd)) {\n+\t\t\thns3_err(hw, \"Don't wait for mbx respone because of \"\n+\t\t\t\t \"disable_cmd\");\n+\t\t\treturn -EBUSY;\n+\t\t}\n+\n+\t\tif (is_reset_pending(hns)) {\n+\t\t\thw->mbx_resp.req_msg_data = 0;\n+\t\t\thns3_err(hw, \"Don't wait for mbx respone because of \"\n+\t\t\t\t \"reset pending\");\n+\t\t\treturn -EIO;\n+\t\t}\n+\n \t\t/*\n \t\t * The mbox response is running on the interrupt thread.\n \t\t * Sending mbox in the interrupt thread cannot wait for the\n@@ -224,6 +238,7 @@ hns3_mbx_handler(struct hns3_hw *hw)\n \n \t\t\thns3_warn(hw, \"PF inform reset level %d\", reset_level);\n \t\t\thw->reset.stats.request_cnt++;\n+\t\t\thns3_schedule_reset(HNS3_DEV_HW_TO_ADAPTER(hw));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\thns3_err(hw, \"Fetched unsupported(%d) message from arq\",\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex 9283864..b29d98a 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -1651,9 +1651,26 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \treturn nb_tx;\n }\n \n+static uint16_t\n+hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,\n+\t\t struct rte_mbuf **pkts __rte_unused,\n+\t\t uint16_t pkts_n __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)\n {\n-\teth_dev->rx_pkt_burst = hns3_recv_pkts;\n-\teth_dev->tx_pkt_burst = hns3_xmit_pkts;\n-\teth_dev->tx_pkt_prepare = hns3_prep_pkts;\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\n+\tif (hns->hw.adapter_state == HNS3_NIC_STARTED &&\n+\t rte_atomic16_read(&hns->hw.reset.resetting) == 0) {\n+\t\teth_dev->rx_pkt_burst = hns3_recv_pkts;\n+\t\teth_dev->tx_pkt_burst = hns3_xmit_pkts;\n+\t\teth_dev->tx_pkt_prepare = hns3_prep_pkts;\n+\t} else {\n+\t\teth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;\n+\t\teth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;\n+\t\teth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;\n+\t}\n }\n", "prefixes": [ "v3", "21/22" ] }