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GET /api/patches/59834/?format=api
{ "id": 59834, "url": "http://patches.dpdk.org/api/patches/59834/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190926085232.47667-14-jasvinder.singh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190926085232.47667-14-jasvinder.singh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190926085232.47667-14-jasvinder.singh@intel.com", "date": "2019-09-26T08:52:30", "name": "[v3,13/15] ip_pipeline: add subport config flexibility to TM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bc710c8d76c2a20ead8ea289e9e760d810160cba", "submitter": { "id": 285, "url": "http://patches.dpdk.org/api/people/285/?format=api", "name": "Jasvinder Singh", "email": "jasvinder.singh@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190926085232.47667-14-jasvinder.singh@intel.com/mbox/", "series": [ { "id": 6540, "url": "http://patches.dpdk.org/api/series/6540/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6540", "date": "2019-09-26T08:52:17", "name": "sched: subport level configuration of pipe nodes", "version": 3, "mbox": "http://patches.dpdk.org/series/6540/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/59834/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/59834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C25771BFA5;\n\tThu, 26 Sep 2019 10:53:32 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 725D51BF4F\n\tfor <dev@dpdk.org>; Thu, 26 Sep 2019 10:52:58 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2019 01:52:58 -0700", "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby fmsmga007.fm.intel.com with ESMTP; 26 Sep 2019 01:52:57 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,551,1559545200\"; d=\"scan'208\";a=\"189945621\"", "From": "Jasvinder Singh <jasvinder.singh@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Thu, 26 Sep 2019 09:52:30 +0100", "Message-Id": "<20190926085232.47667-14-jasvinder.singh@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190926085232.47667-1-jasvinder.singh@intel.com>", "References": "<20190909100530.86020-1-jasvinder.singh@intel.com>\n\t<20190926085232.47667-1-jasvinder.singh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 13/15] ip_pipeline: add subport config\n\tflexibility to TM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Modify ip pipeline traffic management function to allow different\nsubports of the same port to have different configuration in terms\nof number of pipes, pipe queue sizes, etc.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n examples/ip_pipeline/cli.c | 71 ++++++++++++++++++-------------------\n examples/ip_pipeline/tmgr.c | 25 +++++++------\n examples/ip_pipeline/tmgr.h | 7 ++--\n 3 files changed, 51 insertions(+), 52 deletions(-)", "diff": "diff --git a/examples/ip_pipeline/cli.c b/examples/ip_pipeline/cli.c\nindex c6cf4204e..e37a84444 100644\n--- a/examples/ip_pipeline/cli.c\n+++ b/examples/ip_pipeline/cli.c\n@@ -380,7 +380,12 @@ static const char cmd_tmgr_subport_profile_help[] =\n \" <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate> <tc4_rate>\"\n \" <tc5_rate> <tc6_rate> <tc7_rate> <tc8_rate>\"\n \" <tc9_rate> <tc10_rate> <tc11_rate> <tc12_rate>\\n\"\n-\" <tc_period>\\n\";\n+\" <tc_period>\\n\"\n+\" pps <n_pipes_per_subport>\\n\"\n+\" qsize <qsize_tc0> <qsize_tc1> <qsize_tc2>\"\n+\" <qsize_tc3> <qsize_tc4> <qsize_tc5> <qsize_tc6>\"\n+\" <qsize_tc7> <qsize_tc8> <qsize_tc9> <qsize_tc10>\"\n+\" <qsize_tc11> <qsize_tc12>\";\n \n static void\n cmd_tmgr_subport_profile(char **tokens,\n@@ -391,7 +396,7 @@ cmd_tmgr_subport_profile(char **tokens,\n \tstruct rte_sched_subport_params p;\n \tint status, i;\n \n-\tif (n_tokens != 19) {\n+\tif (n_tokens != 35) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -417,6 +422,27 @@ cmd_tmgr_subport_profile(char **tokens,\n \t\treturn;\n \t}\n \n+\tif (strcmp(tokens[19], \"pps\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pps\");\n+\t\treturn;\n+\t}\n+\n+\tif (parser_read_uint32(&p.n_pipes_per_subport_enabled, tokens[20]) != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_pipes_per_subport\");\n+\t\treturn;\n+\t}\n+\n+\tif (strcmp(tokens[21], \"qsize\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"qsize\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tif (parser_read_uint16(&p.qsize[i], tokens[22 + i]) != 0) {\n+\t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"qsize\");\n+\t\t\treturn;\n+\t\t}\n+\n \tstatus = tmgr_subport_profile_add(&p);\n \tif (status != 0) {\n \t\tsnprintf(out, out_size, MSG_CMD_FAIL, tokens[0]);\n@@ -491,11 +517,6 @@ static const char cmd_tmgr_help[] =\n \"tmgr <tmgr_name>\\n\"\n \" rate <rate>\\n\"\n \" spp <n_subports_per_port>\\n\"\n-\" pps <n_pipes_per_subport>\\n\"\n-\" qsize <qsize_tc0> <qsize_tc1> <qsize_tc2>\"\n-\" <qsize_tc3> <qsize_tc4> <qsize_tc5> <qsize_tc6>\"\n-\" <qsize_tc7> <qsize_tc8> <qsize_tc9> <qsize_tc10>\"\n-\" <qsize_tc11> <qsize_tc12>\\n\"\n \" fo <frame_overhead>\\n\"\n \" mtu <mtu>\\n\"\n \" cpu <cpu_id>\\n\";\n@@ -509,9 +530,8 @@ cmd_tmgr(char **tokens,\n \tstruct tmgr_port_params p;\n \tchar *name;\n \tstruct tmgr_port *tmgr_port;\n-\tint i;\n \n-\tif (n_tokens != 28) {\n+\tif (n_tokens != 12) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -538,53 +558,32 @@ cmd_tmgr(char **tokens,\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[6], \"pps\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pps\");\n-\t\treturn;\n-\t}\n-\n-\tif (parser_read_uint32(&p.n_pipes_per_subport, tokens[7]) != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_pipes_per_subport\");\n-\t\treturn;\n-\t}\n-\n-\tif (strcmp(tokens[8], \"qsize\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"qsize\");\n-\t\treturn;\n-\t}\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tif (parser_read_uint16(&p.qsize[i], tokens[9 + i]) != 0) {\n-\t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"qsize\");\n-\t\t\treturn;\n-\t\t}\n-\n-\tif (strcmp(tokens[22], \"fo\") != 0) {\n+\tif (strcmp(tokens[6], \"fo\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"fo\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.frame_overhead, tokens[23]) != 0) {\n+\tif (parser_read_uint32(&p.frame_overhead, tokens[7]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"frame_overhead\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[24], \"mtu\") != 0) {\n+\tif (strcmp(tokens[8], \"mtu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.mtu, tokens[25]) != 0) {\n+\tif (parser_read_uint32(&p.mtu, tokens[9]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[26], \"cpu\") != 0) {\n+\tif (strcmp(tokens[10], \"cpu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"cpu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.cpu_id, tokens[27]) != 0) {\n+\tif (parser_read_uint32(&p.cpu_id, tokens[11]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"cpu_id\");\n \t\treturn;\n \t}\ndiff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c\nindex 40cbf1d0a..91ccbf60f 100644\n--- a/examples/ip_pipeline/tmgr.c\n+++ b/examples/ip_pipeline/tmgr.c\n@@ -47,7 +47,8 @@ int\n tmgr_subport_profile_add(struct rte_sched_subport_params *p)\n {\n \t/* Check input params */\n-\tif (p == NULL)\n+\tif (p == NULL ||\n+\t\tp->n_pipes_per_subport_enabled == 0)\n \t\treturn -1;\n \n \t/* Save profile */\n@@ -90,7 +91,6 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\ttmgr_port_find(name) ||\n \t\t(params == NULL) ||\n \t\t(params->n_subports_per_port == 0) ||\n-\t\t(params->n_pipes_per_subport == 0) ||\n \t\t(params->cpu_id >= RTE_MAX_NUMA_NODES) ||\n \t\t(n_subport_profiles == 0) ||\n \t\t(n_pipe_profiles == 0))\n@@ -103,18 +103,16 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tp.mtu = params->mtu;\n \tp.frame_overhead = params->frame_overhead;\n \tp.n_subports_per_port = params->n_subports_per_port;\n-\tp.n_pipes_per_subport = params->n_pipes_per_subport;\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tp.qsize[i] = params->qsize[i];\n-\n-\tp.pipe_profiles = pipe_profile;\n-\tp.n_pipe_profiles = n_pipe_profiles;\n+\tp.n_pipes_per_subport = TMGR_PIPE_SUBPORT_MAX;\n \n \ts = rte_sched_port_config(&p);\n \tif (s == NULL)\n \t\treturn NULL;\n \n+\tsubport_profile[0].pipe_profiles = pipe_profile;\n+\tsubport_profile[0].n_pipe_profiles = n_pipe_profiles;\n+\tsubport_profile[0].n_max_pipe_profiles = TMGR_PIPE_PROFILE_MAX;\n+\n \tfor (i = 0; i < params->n_subports_per_port; i++) {\n \t\tint status;\n \n@@ -128,7 +126,7 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\t\treturn NULL;\n \t\t}\n \n-\t\tfor (j = 0; j < params->n_pipes_per_subport; j++) {\n+\t\tfor (j = 0; j < subport_profile[0].n_pipes_per_subport_enabled; j++) {\n \t\t\tstatus = rte_sched_pipe_config(\n \t\t\t\ts,\n \t\t\t\ti,\n@@ -153,7 +151,6 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tstrlcpy(tmgr_port->name, name, sizeof(tmgr_port->name));\n \ttmgr_port->s = s;\n \ttmgr_port->n_subports_per_port = params->n_subports_per_port;\n-\ttmgr_port->n_pipes_per_subport = params->n_pipes_per_subport;\n \n \t/* Node add to list */\n \tTAILQ_INSERT_TAIL(&tmgr_port_list, tmgr_port, node);\n@@ -205,8 +202,10 @@ tmgr_pipe_config(const char *port_name,\n \tport = tmgr_port_find(port_name);\n \tif ((port == NULL) ||\n \t\t(subport_id >= port->n_subports_per_port) ||\n-\t\t(pipe_id_first >= port->n_pipes_per_subport) ||\n-\t\t(pipe_id_last >= port->n_pipes_per_subport) ||\n+\t\t(pipe_id_first >=\n+\t\t\tsubport_profile[subport_id].n_pipes_per_subport_enabled) ||\n+\t\t(pipe_id_last >=\n+\t\t\tsubport_profile[subport_id].n_pipes_per_subport_enabled) ||\n \t\t(pipe_id_first > pipe_id_last) ||\n \t\t(pipe_profile_id >= n_pipe_profiles))\n \t\treturn -1;\ndiff --git a/examples/ip_pipeline/tmgr.h b/examples/ip_pipeline/tmgr.h\nindex 8703a2e00..1fcf66ee1 100644\n--- a/examples/ip_pipeline/tmgr.h\n+++ b/examples/ip_pipeline/tmgr.h\n@@ -12,6 +12,10 @@\n \n #include \"common.h\"\n \n+#ifndef TMGR_PIPE_SUBPORT_MAX\n+#define TMGR_PIPE_SUBPORT_MAX 4096\n+#endif\n+\n #ifndef TMGR_SUBPORT_PROFILE_MAX\n #define TMGR_SUBPORT_PROFILE_MAX 256\n #endif\n@@ -25,7 +29,6 @@ struct tmgr_port {\n \tchar name[NAME_SIZE];\n \tstruct rte_sched_port *s;\n \tuint32_t n_subports_per_port;\n-\tuint32_t n_pipes_per_subport;\n };\n \n TAILQ_HEAD(tmgr_port_list, tmgr_port);\n@@ -42,8 +45,6 @@ struct tmgr_port_params {\n \tuint32_t frame_overhead;\n \tuint32_t mtu;\n \tuint32_t cpu_id;\n-\tuint32_t n_pipes_per_subport;\n-\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n };\n \n int\n", "prefixes": [ "v3", "13/15" ] }