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GET /api/patches/58924/?format=api
{ "id": 58924, "url": "http://patches.dpdk.org/api/patches/58924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190906234359.78593-2-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190906234359.78593-2-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190906234359.78593-2-ajit.khaparde@broadcom.com", "date": "2019-09-06T23:43:59", "name": "[1/1] net/bnxt: add support for CoS classification", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "07eb67a84fa59fdb93dc4fb6bd4980b384655f2e", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190906234359.78593-2-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 6320, "url": "http://patches.dpdk.org/api/series/6320/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6320", "date": "2019-09-06T23:43:58", "name": "bnxt patch to support CoS classification", "version": 1, "mbox": "http://patches.dpdk.org/series/6320/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58924/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/58924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A0DC11F416;\n\tSat, 7 Sep 2019 01:44:14 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id 7723E1F3B8\n\tfor <dev@dpdk.org>; Sat, 7 Sep 2019 01:44:11 +0200 (CEST)", "from nis-sj1-27.broadcom.com (nis-sj1-27.lvn.broadcom.net\n\t[10.75.144.136])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id B70D330C0E3;\n\tFri, 6 Sep 2019 16:44:07 -0700 (PDT)", "from localhost.localdomain (unknown [10.230.1.110])\n\tby nis-sj1-27.broadcom.com (Postfix) with ESMTP id 67B7EAC06AB;\n\tFri, 6 Sep 2019 16:44:07 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com B70D330C0E3", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1567813447;\n\tbh=CddoDvgYKOV234PqBsfJRP8pdpW44wbuW75QAKFB1CM=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=l4owVQfGX+p3SvMa3LLrTrpTiCE6YG1NNjmXJIfyYr6vpQeQYD/xIaVAeSuepxych\n\tR0R0ZEq5B6MWL0mOU7gpWaXRSEd9OAJStPR3b2ZyKVvouSaVIjDVjVjAv1V61kg65Y\n\t9+lcOGjkvhiKqSvGjv9ixrjIgkA2gdamfXL9hpFI=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>,\n\tSomnath Kotur <somnath.kotur@broadcom.com>", "Date": "Fri, 6 Sep 2019 16:43:59 -0700", "Message-Id": "<20190906234359.78593-2-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.20.1 (Apple Git-117)", "In-Reply-To": "<20190906234359.78593-1-ajit.khaparde@broadcom.com>", "References": "<20190906234359.78593-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 1/1] net/bnxt: add support for CoS classification", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\n\nClass of Service (CoS) is a way to manage multiple types of\ntraffic over a network to offer different types of services\nto applications. CoS classification (priority to cosqueue) is\ndetermined by the user and configured through the PF driver.\nDPDK driver queries this configuration and maps the cos queue\nids to different VNICs. This patch adds this support.\n\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 8 +++-\n drivers/net/bnxt/bnxt_ethdev.c | 19 ++++++++\n drivers/net/bnxt/bnxt_hwrm.c | 64 ++++++++++++++++++--------\n drivers/net/bnxt/bnxt_hwrm.h | 10 ++++\n drivers/net/bnxt/bnxt_rxq.c | 3 +-\n drivers/net/bnxt/bnxt_vnic.h | 1 +\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 28 ++++++++++-\n 7 files changed, 111 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex 773227048..7e71607ab 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -461,8 +461,10 @@ struct bnxt {\n \n \tuint32_t\t\tflow_flags;\n #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN\tBIT(0)\n-\n \tpthread_mutex_t flow_lock;\n+\n+\tuint32_t\t\tvnic_cap_flags;\n+#define BNXT_VNIC_CAP_COS_CLASSIFY\tBIT(0)\n \tunsigned int\t\trx_nr_rings;\n \tunsigned int\t\trx_cp_nr_rings;\n \tunsigned int\t\trx_num_qs_per_vnic;\n@@ -515,8 +517,10 @@ struct bnxt {\n \tuint16_t hwrm_max_ext_req_len;\n \n \tstruct bnxt_link_info\tlink_info;\n-\tstruct bnxt_cos_queue_info\tcos_queue[BNXT_COS_QUEUE_COUNT];\n+\tstruct bnxt_cos_queue_info\trx_cos_queue[BNXT_COS_QUEUE_COUNT];\n+\tstruct bnxt_cos_queue_info\ttx_cos_queue[BNXT_COS_QUEUE_COUNT];\n \tuint8_t\t\t\ttx_cosq_id;\n+\tuint8_t\t\t\trx_cosq_cnt;\n \tuint8_t max_tc;\n \tuint8_t max_lltc;\n \tuint8_t max_q;\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex f5cbc0038..720a36d7b 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -311,6 +311,25 @@ static int bnxt_init_chip(struct bnxt *bp)\n \t\tgoto err_out;\n \t}\n \n+\tif (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))\n+\t\tgoto skip_cosq_cfg;\n+\n+\tfor (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {\n+\t\tif (bp->rx_cos_queue[i].id != 0xff) {\n+\t\t\tstruct bnxt_vnic_info *vnic = &bp->vnic_info[j++];\n+\n+\t\t\tif (!vnic) {\n+\t\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\t \"Num pools more than FW profile\\n\");\n+\t\t\t\trc = -EINVAL;\n+\t\t\t\tgoto err_out;\n+\t\t\t}\n+\t\t\tvnic->cos_queue_id = bp->rx_cos_queue[i].id;\n+\t\t\tbp->rx_cosq_cnt++;\n+\t\t}\n+\t}\n+\n+skip_cosq_cfg:\n \trc = bnxt_mq_rx_configure(bp);\n \tif (rc) {\n \t\tPMD_DRV_LOG(ERR, \"MQ mode configure failure rc: %x\\n\", rc);\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 227d893da..f919f8599 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -677,6 +677,7 @@ int bnxt_hwrm_func_qcaps(struct bnxt *bp)\n \treturn rc;\n }\n \n+/* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */\n int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)\n {\n \tint rc = 0;\n@@ -691,6 +692,12 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)\n \n \tHWRM_CHECK_RESULT();\n \n+\tif (rte_le_to_cpu_32(resp->flags) &\n+\t HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;\n+\t\tPMD_DRV_LOG(INFO, \"CoS assignment capability enabled\\n\");\n+\t}\n+\n \tbp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);\n \n \tHWRM_UNLOCK();\n@@ -1170,11 +1177,13 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)\n \tint rc = 0;\n \tstruct hwrm_queue_qportcfg_input req = {.req_type = 0 };\n \tstruct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tuint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;\n \tint i;\n \n+get_rx_info:\n \tHWRM_PREP(req, QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);\n \n-\treq.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;\n+\treq.flags = rte_cpu_to_le_32(dir);\n \t/* HWRM Version >= 1.9.1 */\n \tif (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)\n \t\treq.drv_qmap_cap =\n@@ -1183,29 +1192,39 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)\n \n \tHWRM_CHECK_RESULT();\n \n-#define GET_QUEUE_INFO(x) \\\n-\tbp->cos_queue[x].id = resp->queue_id##x; \\\n-\tbp->cos_queue[x].profile = resp->queue_id##x##_service_profile\n-\n-\tGET_QUEUE_INFO(0);\n-\tGET_QUEUE_INFO(1);\n-\tGET_QUEUE_INFO(2);\n-\tGET_QUEUE_INFO(3);\n-\tGET_QUEUE_INFO(4);\n-\tGET_QUEUE_INFO(5);\n-\tGET_QUEUE_INFO(6);\n-\tGET_QUEUE_INFO(7);\n+\tif (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {\n+\t\tGET_TX_QUEUE_INFO(0);\n+\t\tGET_TX_QUEUE_INFO(1);\n+\t\tGET_TX_QUEUE_INFO(2);\n+\t\tGET_TX_QUEUE_INFO(3);\n+\t\tGET_TX_QUEUE_INFO(4);\n+\t\tGET_TX_QUEUE_INFO(5);\n+\t\tGET_TX_QUEUE_INFO(6);\n+\t\tGET_TX_QUEUE_INFO(7);\n+\t} else {\n+\t\tGET_RX_QUEUE_INFO(0);\n+\t\tGET_RX_QUEUE_INFO(1);\n+\t\tGET_RX_QUEUE_INFO(2);\n+\t\tGET_RX_QUEUE_INFO(3);\n+\t\tGET_RX_QUEUE_INFO(4);\n+\t\tGET_RX_QUEUE_INFO(5);\n+\t\tGET_RX_QUEUE_INFO(6);\n+\t\tGET_RX_QUEUE_INFO(7);\n+\t}\n \n \tHWRM_UNLOCK();\n \n+\tif (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)\n+\t\tgoto done;\n+\n \tif (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {\n-\t\tbp->tx_cosq_id = bp->cos_queue[0].id;\n+\t\tbp->tx_cosq_id = bp->tx_cos_queue[0].id;\n \t} else {\n \t\t/* iterate and find the COSq profile to use for Tx */\n-\t\tfor (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {\n-\t\t\tif (bp->cos_queue[i].profile ==\n+\t\tfor (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {\n+\t\t\tif (bp->tx_cos_queue[i].profile ==\n \t\t\t\tHWRM_QUEUE_SERVICE_PROFILE_LOSSY) {\n-\t\t\t\tbp->tx_cosq_id = bp->cos_queue[i].id;\n+\t\t\t\tbp->tx_cosq_id = bp->tx_cos_queue[i].id;\n \t\t\t\tbreak;\n \t\t\t}\n \t\t}\n@@ -1217,8 +1236,12 @@ int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)\n \t\tbp->max_tc = BNXT_MAX_QUEUE;\n \tbp->max_q = bp->max_tc;\n \n-\tPMD_DRV_LOG(DEBUG, \"Tx Cos Queue to use: %d\\n\", bp->tx_cosq_id);\n+\tif (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {\n+\t\tdir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;\n+\t\tgoto get_rx_info;\n+\t}\n \n+done:\n \treturn rc;\n }\n \n@@ -1654,6 +1677,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \t\tctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;\n \t\tctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;\n \t}\n+\tif (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {\n+\t\tctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;\n+\t\treq.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);\n+\t}\n+\n \tenables |= ctx_enable_flag;\n \treq.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);\n \treq.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex 9fa52be72..c78e54adf 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -52,6 +52,16 @@ HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED\n \tHWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC | \\\n \tHWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT)\n \n+#define GET_TX_QUEUE_INFO(x) \\\n+\tbp->tx_cos_queue[x].id = resp->queue_id##x; \\\n+\tbp->tx_cos_queue[x].profile =\t\\\n+\t\tresp->queue_id##x##_service_profile\n+\n+#define GET_RX_QUEUE_INFO(x) \\\n+\tbp->rx_cos_queue[x].id = resp->queue_id##x; \\\n+\tbp->rx_cos_queue[x].profile =\t\\\n+\t\tresp->queue_id##x##_service_profile\n+\n int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp,\n \t\t\t\t struct bnxt_vnic_info *vnic);\n int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic,\ndiff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c\nindex 2e5f2cf29..4df839fa2 100644\n--- a/drivers/net/bnxt/bnxt_rxq.c\n+++ b/drivers/net/bnxt/bnxt_rxq.c\n@@ -75,6 +75,7 @@ int bnxt_mq_rx_configure(struct bnxt *bp)\n \t\tswitch (dev_conf->rxmode.mq_mode) {\n \t\tcase ETH_MQ_RX_VMDQ_RSS:\n \t\tcase ETH_MQ_RX_VMDQ_ONLY:\n+\t\tcase ETH_MQ_RX_VMDQ_DCB_RSS:\n \t\t\t/* FALLTHROUGH */\n \t\t\t/* ETH_8/64_POOLs */\n \t\t\tpools = conf->nb_queue_pools;\n@@ -90,7 +91,7 @@ int bnxt_mq_rx_configure(struct bnxt *bp)\n \t\t\t\tpools = max_pools;\n \t\t\tbreak;\n \t\tcase ETH_MQ_RX_RSS:\n-\t\t\tpools = 1;\n+\t\t\tpools = bp->rx_cosq_cnt ? bp->rx_cosq_cnt : 1;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tPMD_DRV_LOG(ERR, \"Unsupported mq_mod %d\\n\",\ndiff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h\nindex de34b21eb..4f760e0b0 100644\n--- a/drivers/net/bnxt/bnxt_vnic.h\n+++ b/drivers/net/bnxt/bnxt_vnic.h\n@@ -45,6 +45,7 @@ struct bnxt_vnic_info {\n \tuint16_t\tcos_rule;\n \tuint16_t\tlb_rule;\n \tuint16_t\trx_queue_cnt;\n+\tuint16_t\tcos_queue_id;\n \tbool\t\tvlan_strip;\n \tbool\t\tfunc_default;\n \tbool\t\tbd_stall;\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 54f0c04c0..a2097126e 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -21146,7 +21146,7 @@ struct hwrm_vnic_free_output {\n *****************/\n \n \n-/* hwrm_vnic_cfg_input (size:320b/40B) */\n+/* hwrm_vnic_cfg_input (size:384b/48B) */\n struct hwrm_vnic_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -21289,6 +21289,9 @@ struct hwrm_vnic_cfg_input {\n \t */\n \t#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \\\n \t\tUINT32_C(0x40)\n+\t/* This bit must be '1' for the queue_id field to be configured. */\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \\\n+\t\tUINT32_C(0x80)\n \t/* Logical vnic ID */\n \tuint16_t\tvnic_id;\n \t/*\n@@ -21334,6 +21337,19 @@ struct hwrm_vnic_cfg_input {\n \t * be chosen if packet does not match any RSS rules.\n \t */\n \tuint16_t\tdefault_cmpl_ring_id;\n+\t/*\n+\t * When specified, only incoming packets classified to the specified CoS\n+\t * queue ID will be arriving on this VNIC. Packet priority to CoS mapping\n+\t * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,\n+\t * ntuple filters with VNIC destination specified are invalid since they\n+\t * conflict with the the CoS to VNIC steering rules in this mode.\n+\t *\n+\t * If this field is not specified, packet to VNIC steering will be\n+\t * subject to the standard L2 filter rules and any additional ntuple\n+\t * filter rules with destination VNIC specified.\n+\t */\n+\tuint16_t\tqueue_id;\n+\tuint8_t\tunused0[6];\n } __attribute__((packed));\n \n /* hwrm_vnic_cfg_output (size:128b/16B) */\n@@ -21629,6 +21645,16 @@ struct hwrm_vnic_qcaps_output {\n \t */\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \\\n \t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', it indicates that firmware supports the\n+\t * ability to steer incoming packets from one CoS queue to one\n+\t * VNIC. This optional feature can then be enabled\n+\t * using HWRM_VNIC_CFG on any VNIC. This feature is only\n+\t * available when NVM option “enable_cos_classfication” is set\n+\t * to 1. If set to '0', firmware does not support this feature.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \\\n+\t\tUINT32_C(0x100)\n \t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2.\n", "prefixes": [ "1/1" ] }