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GET /api/patches/58877/?format=api
{ "id": 58877, "url": "http://patches.dpdk.org/api/patches/58877/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190906131256.23367-1-akhil.goyal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190906131256.23367-1-akhil.goyal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190906131256.23367-1-akhil.goyal@nxp.com", "date": "2019-09-06T13:12:55", "name": "[1/2] crypto/dpaa_sec: support event crypto adapter", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "06568a5f934938d0f849f673f374f92617c875ec", "submitter": { "id": 517, "url": "http://patches.dpdk.org/api/people/517/?format=api", "name": "Akhil Goyal", "email": "akhil.goyal@nxp.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190906131256.23367-1-akhil.goyal@nxp.com/mbox/", "series": [ { "id": 6307, "url": "http://patches.dpdk.org/api/series/6307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6307", "date": "2019-09-06T13:12:55", "name": "[1/2] crypto/dpaa_sec: support event crypto adapter", "version": 1, "mbox": "http://patches.dpdk.org/series/6307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58877/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/58877/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 03ACD1F411;\n\tFri, 6 Sep 2019 15:27:24 +0200 (CEST)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby dpdk.org (Postfix) with ESMTP id F19491F410\n\tfor <dev@dpdk.org>; Fri, 6 Sep 2019 15:27:22 +0200 (CEST)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8BE602001FB;\n\tFri, 6 Sep 2019 15:27:22 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7F5EE200041;\n\tFri, 6 Sep 2019 15:27:19 +0200 (CEST)", "from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 3C485402A5;\n\tFri, 6 Sep 2019 21:27:16 +0800 (SGT)" ], "From": "Akhil Goyal <akhil.goyal@nxp.com>", "To": "dev@dpdk.org", "Cc": "hemant.agrawal@nxp.com, anoobj@marvell.com, jerinj@marvell.com,\n\tAkhil Goyal <akhil.goyal@nxp.com>", "Date": "Fri, 6 Sep 2019 18:42:55 +0530", "Message-Id": "<20190906131256.23367-1-akhil.goyal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[dpdk-dev] [PATCH 1/2] crypto/dpaa_sec: support event crypto adapter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "dpaa_sec hw queues can be attached to a hw dpaa event\ndevice and the application can configure the event\ncrypto adapter to access the dpaa_sec packets using\nhardware events.\nThis patch defines APIs which can be used by the\ndpaa event device to attach/detach dpaa_sec queues.\n\nSigned-off-by: Akhil Goyal <akhil.goyal@nxp.com>\n---\n drivers/bus/dpaa/base/qbman/qman.c | 9 +-\n drivers/bus/dpaa/include/fsl_qman.h | 2 +-\n drivers/crypto/dpaa_sec/Makefile | 1 +\n drivers/crypto/dpaa_sec/dpaa_sec.c | 200 +++++++++++++++++-\n drivers/crypto/dpaa_sec/dpaa_sec_event.h | 19 ++\n .../dpaa_sec/rte_pmd_dpaa_sec_version.map | 8 +\n 6 files changed, 231 insertions(+), 8 deletions(-)\n create mode 100644 drivers/crypto/dpaa_sec/dpaa_sec_event.h", "diff": "diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c\nindex c6f7d7bb3..e43fc65ef 100644\n--- a/drivers/bus/dpaa/base/qbman/qman.c\n+++ b/drivers/bus/dpaa/base/qbman/qman.c\n@@ -2286,7 +2286,7 @@ int qman_enqueue_multi(struct qman_fq *fq,\n \n int\n qman_enqueue_multi_fq(struct qman_fq *fq[], const struct qm_fd *fd,\n-\t\t int frames_to_send)\n+\t\t u32 *flags, int frames_to_send)\n {\n \tstruct qman_portal *p = get_affine_portal();\n \tstruct qm_portal *portal = &p->p;\n@@ -2294,7 +2294,7 @@ qman_enqueue_multi_fq(struct qman_fq *fq[], const struct qm_fd *fd,\n \tregister struct qm_eqcr *eqcr = &portal->eqcr;\n \tstruct qm_eqcr_entry *eq = eqcr->cursor, *prev_eq;\n \n-\tu8 i, diff, old_ci, sent = 0;\n+\tu8 i = 0, diff, old_ci, sent = 0;\n \n \t/* Update the available entries if no entry is free */\n \tif (!eqcr->available) {\n@@ -2313,6 +2313,11 @@ qman_enqueue_multi_fq(struct qman_fq *fq[], const struct qm_fd *fd,\n \t\teq->fd.addr = cpu_to_be40(fd->addr);\n \t\teq->fd.status = cpu_to_be32(fd->status);\n \t\teq->fd.opaque = cpu_to_be32(fd->opaque);\n+\t\tif (flags && (flags[i] & QMAN_ENQUEUE_FLAG_DCA)) {\n+\t\t\teq->dca = QM_EQCR_DCA_ENABLE |\n+\t\t\t\t((flags[i] >> 8) & QM_EQCR_DCA_IDXMASK);\n+\t\t}\n+\t\ti++;\n \n \t\teq = (void *)((unsigned long)(eq + 1) &\n \t\t\t(~(unsigned long)(QM_EQCR_SIZE << 6)));\ndiff --git a/drivers/bus/dpaa/include/fsl_qman.h b/drivers/bus/dpaa/include/fsl_qman.h\nindex e5cccbbea..29fb2eb9d 100644\n--- a/drivers/bus/dpaa/include/fsl_qman.h\n+++ b/drivers/bus/dpaa/include/fsl_qman.h\n@@ -1773,7 +1773,7 @@ int qman_enqueue_multi(struct qman_fq *fq, const struct qm_fd *fd, u32 *flags,\n */\n int\n qman_enqueue_multi_fq(struct qman_fq *fq[], const struct qm_fd *fd,\n-\t\t int frames_to_send);\n+\t\t u32 *flags, int frames_to_send);\n \n typedef int (*qman_cb_precommit) (void *arg);\n \ndiff --git a/drivers/crypto/dpaa_sec/Makefile b/drivers/crypto/dpaa_sec/Makefile\nindex 1d8b7bec1..353c2549f 100644\n--- a/drivers/crypto/dpaa_sec/Makefile\n+++ b/drivers/crypto/dpaa_sec/Makefile\n@@ -16,6 +16,7 @@ CFLAGS += $(WERROR_FLAGS)\n \n CFLAGS += -I$(RTE_SDK)/drivers/bus/dpaa\n CFLAGS += -I$(RTE_SDK)/drivers/bus/dpaa/include\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/dpaa/base/qbman\n CFLAGS += -I$(RTE_SDK)/drivers/crypto/dpaa_sec/\n #sharing the hw flib headers from dpaa2_sec pmd\n CFLAGS += -I$(RTE_SDK)/drivers/crypto/dpaa2_sec/\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c\nindex e6f57ce3d..e96307a8a 100644\n--- a/drivers/crypto/dpaa_sec/dpaa_sec.c\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c\n@@ -37,6 +37,7 @@\n \n #include <rte_dpaa_bus.h>\n #include <dpaa_sec.h>\n+#include <dpaa_sec_event.h>\n #include <dpaa_sec_log.h>\n \n enum rta_sec_era rta_sec_era;\n@@ -60,9 +61,6 @@ dpaa_sec_op_ending(struct dpaa_sec_op_ctx *ctx)\n \t\tDPAA_SEC_DP_WARN(\"SEC return err: 0x%x\", ctx->fd_status);\n \t\tctx->op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n \t}\n-\n-\t/* report op status to sym->op and then free the ctx memory */\n-\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n }\n \n static inline struct dpaa_sec_op_ctx *\n@@ -1656,7 +1654,7 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \tstruct rte_crypto_op *op;\n \tstruct dpaa_sec_job *cf;\n \tdpaa_sec_session *ses;\n-\tuint32_t auth_only_len;\n+\tuint32_t auth_only_len, index, flags[DPAA_SEC_BURST] = {0};\n \tstruct qman_fq *inq[DPAA_SEC_BURST];\n \n \twhile (nb_ops) {\n@@ -1664,6 +1662,18 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\t\t\tDPAA_SEC_BURST : nb_ops;\n \t\tfor (loop = 0; loop < frames_to_send; loop++) {\n \t\t\top = *(ops++);\n+\t\t\tif (op->sym->m_src->seqn != 0) {\n+\t\t\t\tindex = op->sym->m_src->seqn - 1;\n+\t\t\t\tif (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) {\n+\t\t\t\t\t/* QM_EQCR_DCA_IDXMASK = 0x0f */\n+\t\t\t\t\tflags[loop] = ((index & 0x0f) << 8);\n+\t\t\t\t\tflags[loop] |= QMAN_ENQUEUE_FLAG_DCA;\n+\t\t\t\t\tDPAA_PER_LCORE_DQRR_SIZE--;\n+\t\t\t\t\tDPAA_PER_LCORE_DQRR_HELD &=\n+\t\t\t\t\t\t\t\t~(1 << index);\n+\t\t\t\t}\n+\t\t\t}\n+\n \t\t\tswitch (op->sess_type) {\n \t\t\tcase RTE_CRYPTO_OP_WITH_SESSION:\n \t\t\t\tses = (dpaa_sec_session *)\n@@ -1764,7 +1774,7 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \t\tloop = 0;\n \t\twhile (loop < frames_to_send) {\n \t\t\tloop += qman_enqueue_multi_fq(&inq[loop], &fds[loop],\n-\t\t\t\t\tframes_to_send - loop);\n+\t\t\t\t\t&flags[loop], frames_to_send - loop);\n \t\t}\n \t\tnb_ops -= frames_to_send;\n \t\tnum_tx += frames_to_send;\n@@ -2572,6 +2582,186 @@ dpaa_sec_dev_infos_get(struct rte_cryptodev *dev,\n \t}\n }\n \n+static enum qman_cb_dqrr_result\n+dpaa_sec_process_parallel_event(void *event,\n+\t\t\tstruct qman_portal *qm __always_unused,\n+\t\t\tstruct qman_fq *outq,\n+\t\t\tconst struct qm_dqrr_entry *dqrr,\n+\t\t\tvoid **bufs)\n+{\n+\tconst struct qm_fd *fd;\n+\tstruct dpaa_sec_job *job;\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tstruct rte_event *ev = (struct rte_event *)event;\n+\n+\tfd = &dqrr->fd;\n+\n+\t/* sg is embedded in an op ctx,\n+\t * sg[0] is for output\n+\t * sg[1] for input\n+\t */\n+\tjob = dpaa_mem_ptov(qm_fd_addr_get64(fd));\n+\n+\tctx = container_of(job, struct dpaa_sec_op_ctx, job);\n+\tctx->fd_status = fd->status;\n+\tif (ctx->op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n+\t\tstruct qm_sg_entry *sg_out;\n+\t\tuint32_t len;\n+\n+\t\tsg_out = &job->sg[0];\n+\t\thw_sg_to_cpu(sg_out);\n+\t\tlen = sg_out->length;\n+\t\tctx->op->sym->m_src->pkt_len = len;\n+\t\tctx->op->sym->m_src->data_len = len;\n+\t}\n+\tif (!ctx->fd_status) {\n+\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t} else {\n+\t\tDPAA_SEC_DP_WARN(\"SEC return err: 0x%x\", ctx->fd_status);\n+\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t}\n+\tev->event_ptr = (void *)ctx->op;\n+\n+\tev->flow_id = outq->ev.flow_id;\n+\tev->sub_event_type = outq->ev.sub_event_type;\n+\tev->event_type = RTE_EVENT_TYPE_CRYPTODEV;\n+\tev->op = RTE_EVENT_OP_NEW;\n+\tev->sched_type = outq->ev.sched_type;\n+\tev->queue_id = outq->ev.queue_id;\n+\tev->priority = outq->ev.priority;\n+\t*bufs = (void *)ctx->op;\n+\n+\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n+\n+\treturn qman_cb_dqrr_consume;\n+}\n+\n+static enum qman_cb_dqrr_result\n+dpaa_sec_process_atomic_event(void *event,\n+\t\t\tstruct qman_portal *qm __rte_unused,\n+\t\t\tstruct qman_fq *outq,\n+\t\t\tconst struct qm_dqrr_entry *dqrr,\n+\t\t\tvoid **bufs)\n+{\n+\tu8 index;\n+\tconst struct qm_fd *fd;\n+\tstruct dpaa_sec_job *job;\n+\tstruct dpaa_sec_op_ctx *ctx;\n+\tstruct rte_event *ev = (struct rte_event *)event;\n+\n+\tfd = &dqrr->fd;\n+\n+\t/* sg is embedded in an op ctx,\n+\t * sg[0] is for output\n+\t * sg[1] for input\n+\t */\n+\tjob = dpaa_mem_ptov(qm_fd_addr_get64(fd));\n+\n+\tctx = container_of(job, struct dpaa_sec_op_ctx, job);\n+\tctx->fd_status = fd->status;\n+\tif (ctx->op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n+\t\tstruct qm_sg_entry *sg_out;\n+\t\tuint32_t len;\n+\n+\t\tsg_out = &job->sg[0];\n+\t\thw_sg_to_cpu(sg_out);\n+\t\tlen = sg_out->length;\n+\t\tctx->op->sym->m_src->pkt_len = len;\n+\t\tctx->op->sym->m_src->data_len = len;\n+\t}\n+\tif (!ctx->fd_status) {\n+\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t} else {\n+\t\tDPAA_SEC_DP_WARN(\"SEC return err: 0x%x\", ctx->fd_status);\n+\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t}\n+\tev->event_ptr = (void *)ctx->op;\n+\tev->flow_id = outq->ev.flow_id;\n+\tev->sub_event_type = outq->ev.sub_event_type;\n+\tev->event_type = RTE_EVENT_TYPE_CRYPTODEV;\n+\tev->op = RTE_EVENT_OP_NEW;\n+\tev->sched_type = outq->ev.sched_type;\n+\tev->queue_id = outq->ev.queue_id;\n+\tev->priority = outq->ev.priority;\n+\n+\t/* Save active dqrr entries */\n+\tindex = ((uintptr_t)dqrr >> 6) & (16/*QM_DQRR_SIZE*/ - 1);\n+\tDPAA_PER_LCORE_DQRR_SIZE++;\n+\tDPAA_PER_LCORE_DQRR_HELD |= 1 << index;\n+\tDPAA_PER_LCORE_DQRR_MBUF(index) = ctx->op->sym->m_src;\n+\tev->impl_opaque = index + 1;\n+\tctx->op->sym->m_src->seqn = (uint32_t)index + 1;\n+\t*bufs = (void *)ctx->op;\n+\n+\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n+\n+\treturn qman_cb_dqrr_defer;\n+}\n+\n+int\n+dpaa_sec_eventq_attach(const struct rte_cryptodev *dev,\n+\t\tint qp_id,\n+\t\tuint16_t ch_id,\n+\t\tconst struct rte_event *event)\n+{\n+\tstruct dpaa_sec_qp *qp = dev->data->queue_pairs[qp_id];\n+\tstruct qm_mcc_initfq opts = {0};\n+\n+\tint ret;\n+\n+\topts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |\n+\t\t QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CONTEXTB;\n+\topts.fqd.dest.channel = ch_id;\n+\n+\tswitch (event->sched_type) {\n+\tcase RTE_SCHED_TYPE_ATOMIC:\n+\t\topts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;\n+\t\t/* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary\n+\t\t * configuration with HOLD_ACTIVE setting\n+\t\t */\n+\t\topts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);\n+\t\tqp->outq.cb.dqrr_dpdk_cb = dpaa_sec_process_atomic_event;\n+\t\tbreak;\n+\tcase RTE_SCHED_TYPE_ORDERED:\n+\t\tDPAA_SEC_ERR(\"Ordered queue schedule type is not supported\\n\");\n+\t\treturn -1;\n+\tdefault:\n+\t\topts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;\n+\t\tqp->outq.cb.dqrr_dpdk_cb = dpaa_sec_process_parallel_event;\n+\t\tbreak;\n+\t}\n+\n+\tret = qman_init_fq(&qp->outq, QMAN_INITFQ_FLAG_SCHED, &opts);\n+\tif (unlikely(ret)) {\n+\t\tDPAA_SEC_ERR(\"unable to init caam source fq!\");\n+\t\treturn ret;\n+\t}\n+\n+\tmemcpy(&qp->outq.ev, event, sizeof(struct rte_event));\n+\n+\treturn 0;\n+}\n+\n+int\n+dpaa_sec_eventq_detach(const struct rte_cryptodev *dev,\n+\t\t\tint qp_id)\n+{\n+\tstruct qm_mcc_initfq opts = {0};\n+\tint ret;\n+\tstruct dpaa_sec_qp *qp = dev->data->queue_pairs[qp_id];\n+\n+\topts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |\n+\t\t QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CONTEXTB;\n+\tqp->outq.cb.dqrr = dqrr_out_fq_cb_rx;\n+\tqp->outq.cb.ern = ern_sec_fq_handler;\n+\tret = qman_init_fq(&qp->outq, 0, &opts);\n+\tif (ret)\n+\t\tRTE_LOG(ERR, PMD, \"Error in qman_init_fq: ret: %d\\n\", ret);\n+\tqp->outq.cb.dqrr = NULL;\n+\n+\treturn ret;\n+}\n+\n static struct rte_cryptodev_ops crypto_ops = {\n \t.dev_configure\t = dpaa_sec_dev_configure,\n \t.dev_start\t = dpaa_sec_dev_start,\ndiff --git a/drivers/crypto/dpaa_sec/dpaa_sec_event.h b/drivers/crypto/dpaa_sec/dpaa_sec_event.h\nnew file mode 100644\nindex 000000000..8d1a01809\n--- /dev/null\n+++ b/drivers/crypto/dpaa_sec/dpaa_sec_event.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2019 NXP\n+ *\n+ */\n+\n+#ifndef _DPAA_SEC_EVENT_H_\n+#define _DPAA_SEC_EVENT_H_\n+\n+int\n+dpaa_sec_eventq_attach(const struct rte_cryptodev *dev,\n+\t\tint qp_id,\n+\t\tuint16_t ch_id,\n+\t\tconst struct rte_event *event);\n+\n+int\n+dpaa_sec_eventq_detach(const struct rte_cryptodev *dev,\n+\t\tint qp_id);\n+\n+#endif /* _DPAA_SEC_EVENT_H_ */\ndiff --git a/drivers/crypto/dpaa_sec/rte_pmd_dpaa_sec_version.map b/drivers/crypto/dpaa_sec/rte_pmd_dpaa_sec_version.map\nindex a70bd197b..cc7f2162e 100644\n--- a/drivers/crypto/dpaa_sec/rte_pmd_dpaa_sec_version.map\n+++ b/drivers/crypto/dpaa_sec/rte_pmd_dpaa_sec_version.map\n@@ -2,3 +2,11 @@ DPDK_17.11 {\n \n \tlocal: *;\n };\n+\n+DPDK_19.11 {\n+\tglobal:\n+\n+\tdpaa_sec_eventq_attach;\n+\tdpaa_sec_eventq_detach;\n+\n+} DPDK_17.11;\n", "prefixes": [ "1/2" ] }