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GET /api/patches/58862/?format=api
{ "id": 58862, "url": "http://patches.dpdk.org/api/patches/58862/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190906131330.40185-1-roy.fan.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190906131330.40185-1-roy.fan.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190906131330.40185-1-roy.fan.zhang@intel.com", "date": "2019-09-06T13:13:20", "name": "[00/10] security: add software synchronous crypto process", "commit_ref": null, "pull_url": null, "state": null, "archived": false, "hash": null, "submitter": { "id": 304, "url": "http://patches.dpdk.org/api/people/304/?format=api", "name": "Fan Zhang", "email": "roy.fan.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190906131330.40185-1-roy.fan.zhang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/58862/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/58862/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 28EA81F371;\n\tFri, 6 Sep 2019 15:13:37 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id 9C4301F2BA\n\tfor <dev@dpdk.org>; Fri, 6 Sep 2019 15:13:35 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Sep 2019 06:13:34 -0700", "from silpixa00398673.ir.intel.com (HELO\n\tsilpixa00398673.ger.corp.intel.com) ([10.237.223.136])\n\tby fmsmga002.fm.intel.com with ESMTP; 06 Sep 2019 06:13:32 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,473,1559545200\"; d=\"scan'208\";a=\"213140694\"", "From": "Fan Zhang <roy.fan.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "konstantin.ananyev@intel.com, declan.doherty@intel.com,\n\takhil.goyal@nxp.com, Fan Zhang <roy.fan.zhang@intel.com>", "Date": "Fri, 6 Sep 2019 14:13:20 +0100", "Message-Id": "<20190906131330.40185-1-roy.fan.zhang@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20190903154046.55992-1-roy.fan.zhang@intel.com>", "References": "<20190903154046.55992-1-roy.fan.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 00/10] security: add software synchronous crypto\n\tprocess", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This RFC patch adds a way to rte_security to process symmetric crypto\nworkload in bulk synchronously for SW crypto devices.\n\nOriginally both SW and HW crypto PMDs works under rte_cryptodev to\nprocess the crypto workload asynchronously. This way provides uniformity\nto both PMD types but also introduce unnecessary performance penalty to\nSW PMDs such as extra SW ring enqueue/dequeue steps to \"simulate\"\nasynchronous working manner and unnecessary HW addresses computation.\n\nWe introduce a new way for SW crypto devices that perform crypto operation\nsynchronously with only fields required for the computation as input.\n\nIn rte_security, a new action type \"RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO\"\nis introduced. This action type allows the burst of symmetric crypto\nworkload using the same algorithm, key, and direction being processed by\nCPU cycles synchronously. This flexible action type does not require\nexternal hardware involvement.\n\nThis patch also includes the announcement of a new API\n\"rte_security_process_cpu_crypto_bulk\". With this API the packet is sent to\nthe crypto device for symmetric crypto processing. The device will encrypt\nor decrypt the buffer based on the session data specified and preprocessed\nin the security session. Different than the inline or lookaside modes, when\nthe function exits, the user will expect the buffers are either processed\nsuccessfully, or having the error number assigned to the appropriate index\nof the status array.\n\nThe proof-of-concept AESNI-GCM and AESNI-MB SW PMDs are updated with the\nsupport of this new method. To demonstrate the performance gain with\nthis method 2 simple performance evaluation apps under unit-test are added\n\"app/test: security_aesni_gcm_perftest/security_aesni_mb_perftest\". The\nusers can freely compare their results against crypto perf application\nresults.\n\nIn the end, the ipsec library and ipsec-secgw sample application are also\nupdated to support this feature. Several test scripts are added to the\nipsec-secgw test-suite to prove the correctness of the implementation.\n\nFan Zhang (10):\n security: introduce CPU Crypto action type and API\n crypto/aesni_gcm: add rte_security handler\n app/test: add security cpu crypto autotest\n app/test: add security cpu crypto perftest\n crypto/aesni_mb: add rte_security handler\n app/test: add aesni_mb security cpu crypto autotest\n app/test: add aesni_mb security cpu crypto perftest\n ipsec: add rte_security cpu_crypto action support\n examples/ipsec-secgw: add security cpu_crypto action support\n doc: update security cpu process description\n\n app/test/Makefile | 1 +\n app/test/meson.build | 1 +\n app/test/test_security_cpu_crypto.c | 1326 ++++++++++++++++++++\n doc/guides/cryptodevs/aesni_gcm.rst | 6 +\n doc/guides/cryptodevs/aesni_mb.rst | 7 +\n doc/guides/prog_guide/rte_security.rst | 112 +-\n doc/guides/rel_notes/release_19_11.rst | 7 +\n drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 91 +-\n drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 95 ++\n drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h | 23 +\n drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 291 ++++-\n drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c | 91 +-\n drivers/crypto/aesni_mb/rte_aesni_mb_pmd_private.h | 21 +-\n examples/ipsec-secgw/ipsec.c | 22 +\n examples/ipsec-secgw/ipsec_process.c | 7 +-\n examples/ipsec-secgw/sa.c | 13 +-\n examples/ipsec-secgw/test/run_test.sh | 10 +\n .../test/trs_3descbc_sha1_cpu_crypto_defs.sh | 5 +\n .../test/trs_aescbc_sha1_cpu_crypto_defs.sh | 5 +\n .../test/trs_aesctr_sha1_cpu_crypto_defs.sh | 5 +\n .../ipsec-secgw/test/trs_aesgcm_cpu_crypto_defs.sh | 5 +\n .../test/trs_aesgcm_mb_cpu_crypto_defs.sh | 7 +\n .../test/tun_3descbc_sha1_cpu_crypto_defs.sh | 5 +\n .../test/tun_aescbc_sha1_cpu_crypto_defs.sh | 5 +\n .../test/tun_aesctr_sha1_cpu_crypto_defs.sh | 5 +\n .../ipsec-secgw/test/tun_aesgcm_cpu_crypto_defs.sh | 5 +\n .../test/tun_aesgcm_mb_cpu_crypto_defs.sh | 7 +\n lib/librte_ipsec/esp_inb.c | 174 ++-\n lib/librte_ipsec/esp_outb.c | 290 ++++-\n lib/librte_ipsec/sa.c | 53 +-\n lib/librte_ipsec/sa.h | 29 +\n lib/librte_ipsec/ses.c | 4 +-\n lib/librte_security/rte_security.c | 16 +\n lib/librte_security/rte_security.h | 51 +-\n lib/librte_security/rte_security_driver.h | 19 +\n lib/librte_security/rte_security_version.map | 1 +\n 36 files changed, 2791 insertions(+), 24 deletions(-)\n create mode 100644 app/test/test_security_cpu_crypto.c\n create mode 100644 examples/ipsec-secgw/test/trs_3descbc_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/trs_aescbc_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/trs_aesctr_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/trs_aesgcm_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/trs_aesgcm_mb_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/tun_3descbc_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/tun_aescbc_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/tun_aesctr_sha1_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/tun_aesgcm_cpu_crypto_defs.sh\n create mode 100644 examples/ipsec-secgw/test/tun_aesgcm_mb_cpu_crypto_defs.sh", "diff": null, "prefixes": [ "00/10" ] }