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GET /api/patches/58603/?format=api
{ "id": 58603, "url": "http://patches.dpdk.org/api/patches/58603/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190905053933.27929-2-xiaoyun.li@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190905053933.27929-2-xiaoyun.li@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190905053933.27929-2-xiaoyun.li@intel.com", "date": "2019-09-05T05:39:30", "name": "[1/4] raw/ntb: setup ntb queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "34c6bfe0d8c422f32f56557be8d785a0261d1af6", "submitter": { "id": 798, "url": "http://patches.dpdk.org/api/people/798/?format=api", "name": "Li, Xiaoyun", "email": "xiaoyun.li@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190905053933.27929-2-xiaoyun.li@intel.com/mbox/", "series": [ { "id": 6245, "url": "http://patches.dpdk.org/api/series/6245/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6245", "date": "2019-09-05T05:39:29", "name": "enable FIFO for NTB", "version": 1, "mbox": "http://patches.dpdk.org/series/6245/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58603/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/58603/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 22DD61EBF1;\n\tThu, 5 Sep 2019 07:39:54 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id EB25B1EBE0\n\tfor <dev@dpdk.org>; Thu, 5 Sep 2019 07:39:51 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t04 Sep 2019 22:39:51 -0700", "from dpdk-xiaoyun3.sh.intel.com ([10.67.118.227])\n\tby orsmga008.jf.intel.com with ESMTP; 04 Sep 2019 22:39:48 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,469,1559545200\"; d=\"scan'208\";a=\"177188693\"", "From": "Xiaoyun Li <xiaoyun.li@intel.com>", "To": "jingjing.wu@intel.com, keith.wiles@intel.com, omkar.maslekar@intel.com, \n\tcunming.liang@intel.com", "Cc": "dev@dpdk.org,\n\tXiaoyun Li <xiaoyun.li@intel.com>", "Date": "Thu, 5 Sep 2019 13:39:30 +0800", "Message-Id": "<20190905053933.27929-2-xiaoyun.li@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190905053933.27929-1-xiaoyun.li@intel.com>", "References": "<20190905053933.27929-1-xiaoyun.li@intel.com>", "Subject": "[dpdk-dev] [PATCH 1/4] raw/ntb: setup ntb queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Setup and init ntb txq and rxq. And negotiate queue information\nwith the peer. If queue size and number of queues are not\nconsistent on both sides, return error.\n\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\n---\n doc/guides/rawdevs/ntb.rst | 39 +-\n doc/guides/rel_notes/release_19_11.rst | 4 +\n drivers/raw/ntb/Makefile | 3 +\n drivers/raw/ntb/meson.build | 1 +\n drivers/raw/ntb/ntb.c | 705 ++++++++++++++++++-------\n drivers/raw/ntb/ntb.h | 151 ++++--\n drivers/raw/ntb/ntb_hw_intel.c | 26 +-\n drivers/raw/ntb/rte_pmd_ntb.h | 43 ++\n 8 files changed, 718 insertions(+), 254 deletions(-)\n create mode 100644 drivers/raw/ntb/rte_pmd_ntb.h", "diff": "diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst\nindex 0a61ec03d..99e7db441 100644\n--- a/doc/guides/rawdevs/ntb.rst\n+++ b/doc/guides/rawdevs/ntb.rst\n@@ -45,8 +45,45 @@ to use, i.e. igb_uio, vfio. The ``dpdk-devbind.py`` script can be used to\n show devices status and to bind them to a suitable kernel driver. They will\n appear under the category of \"Misc (rawdev) devices\".\n \n+Ring Layout\n+-----------\n+\n+Since read/write remote system's memory are through PCI bus, remote read\n+is much more expensive than remote write. Thus, the enqueue and dequeue\n+based on ntb ring should avoid remote read. The ring layout for ntb is\n+like the following:\n+- Ring Format:\n+ desc_ring:\n+ 0 16 64\n+ +---------------------------------------------------------------+\n+ | buffer address |\n+ +---------------+-----------------------------------------------+\n+ | buffer length | resv |\n+ +---------------+-----------------------------------------------+\n+ used_ring:\n+ 0 16 32\n+ +---------------+---------------+\n+ | packet length | flags |\n+ +---------------+---------------+\n+- Ring Layout\n+ +------------------------+ +------------------------+\n+ | used_ring | | desc_ring |\n+ | +---+ | | +---+ |\n+ | | | | | | | |\n+ | +---+ +--------+ | | +---+ |\n+ | | | ---> | buffer | <+---+-| | |\n+ | +---+ +--------+ | | +---+ |\n+ | | | | | | | |\n+ | +---+ | | +---+ |\n+ | ... | | ... |\n+ | | | |\n+ | +---------+ | | +---------+ |\n+ | | tx_tail | | | | rx_tail | |\n+ | System A +---------+ | | System B +---------+ |\n+ +------------------------+ +------------------------+\n+ <---------traffic---------\n+\n Limitation\n ----------\n \n-- The FIFO hasn't been introduced and will come in 19.11 release.\n - This PMD only supports Intel Skylake platform.\ndiff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst\nindex 8490d897c..7ac3d5ca6 100644\n--- a/doc/guides/rel_notes/release_19_11.rst\n+++ b/doc/guides/rel_notes/release_19_11.rst\n@@ -56,6 +56,10 @@ New Features\n Also, make sure to start the actual text at the margin.\n =========================================================\n \n+ * **Introduced FIFO for NTB PMD.**\n+\n+ Introduced FIFO for NTB (Non-transparent Bridge) PMD to support\n+ packet based processing.\n \n Removed Items\n -------------\ndiff --git a/drivers/raw/ntb/Makefile b/drivers/raw/ntb/Makefile\nindex 6fe2aaf40..814cd05ca 100644\n--- a/drivers/raw/ntb/Makefile\n+++ b/drivers/raw/ntb/Makefile\n@@ -25,4 +25,7 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += ntb.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += ntb_hw_intel.c\n \n+# install this header file\n+SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV)-include := rte_pmd_ntb.h\n+\n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/raw/ntb/meson.build b/drivers/raw/ntb/meson.build\nindex 7f39437f8..7a7d26126 100644\n--- a/drivers/raw/ntb/meson.build\n+++ b/drivers/raw/ntb/meson.build\n@@ -5,4 +5,5 @@ deps += ['rawdev', 'mbuf', 'mempool',\n \t 'pci', 'bus_pci']\n sources = files('ntb.c',\n 'ntb_hw_intel.c')\n+install_headers('rte_pmd_ntb.h')\n allow_experimental_apis = true\ndiff --git a/drivers/raw/ntb/ntb.c b/drivers/raw/ntb/ntb.c\nindex bfecce1e4..124c82a95 100644\n--- a/drivers/raw/ntb/ntb.c\n+++ b/drivers/raw/ntb/ntb.c\n@@ -12,6 +12,7 @@\n #include <rte_eal.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n+#include <rte_mbuf.h>\n #include <rte_bus_pci.h>\n #include <rte_memzone.h>\n #include <rte_memcpy.h>\n@@ -19,6 +20,7 @@\n #include <rte_rawdev_pmd.h>\n \n #include \"ntb_hw_intel.h\"\n+#include \"rte_pmd_ntb.h\"\n #include \"ntb.h\"\n \n int ntb_logtype;\n@@ -28,48 +30,7 @@ static const struct rte_pci_id pci_id_ntb_map[] = {\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n-static int\n-ntb_set_mw(struct rte_rawdev *dev, int mw_idx, uint64_t mw_size)\n-{\n-\tstruct ntb_hw *hw = dev->dev_private;\n-\tchar mw_name[RTE_MEMZONE_NAMESIZE];\n-\tconst struct rte_memzone *mz;\n-\tint ret = 0;\n-\n-\tif (hw->ntb_ops->mw_set_trans == NULL) {\n-\t\tNTB_LOG(ERR, \"Not supported to set mw.\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\tsnprintf(mw_name, sizeof(mw_name), \"ntb_%d_mw_%d\",\n-\t\t dev->dev_id, mw_idx);\n-\n-\tmz = rte_memzone_lookup(mw_name);\n-\tif (mz)\n-\t\treturn 0;\n-\n-\t/**\n-\t * Hardware requires that mapped memory base address should be\n-\t * aligned with EMBARSZ and needs continuous memzone.\n-\t */\n-\tmz = rte_memzone_reserve_aligned(mw_name, mw_size, dev->socket_id,\n-\t\t\t\tRTE_MEMZONE_IOVA_CONTIG, hw->mw_size[mw_idx]);\n-\tif (!mz) {\n-\t\tNTB_LOG(ERR, \"Cannot allocate aligned memzone.\");\n-\t\treturn -EIO;\n-\t}\n-\thw->mz[mw_idx] = mz;\n-\n-\tret = (*hw->ntb_ops->mw_set_trans)(dev, mw_idx, mz->iova, mw_size);\n-\tif (ret) {\n-\t\tNTB_LOG(ERR, \"Cannot set mw translation.\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn ret;\n-}\n-\n-static void\n+static inline void\n ntb_link_cleanup(struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n@@ -89,20 +50,94 @@ ntb_link_cleanup(struct rte_rawdev *dev)\n \t}\n \n \t/* Clear mw so that peer cannot access local memory.*/\n-\tfor (i = 0; i < hw->mw_cnt; i++) {\n+\tfor (i = 0; i < hw->used_mw_num; i++) {\n \t\tstatus = (*hw->ntb_ops->mw_set_trans)(dev, i, 0, 0);\n \t\tif (status)\n \t\t\tNTB_LOG(ERR, \"Failed to clean mw.\");\n \t}\n }\n \n+static inline int\n+ntb_handshake_work(const struct rte_rawdev *dev)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint32_t val;\n+\tint ret, i;\n+\n+\tif (hw->ntb_ops->spad_write == NULL ||\n+\t hw->ntb_ops->mw_set_trans == NULL) {\n+\t\tNTB_LOG(ERR, \"Scratchpad/MW setting is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Tell peer the mw info of local side. */\n+\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_NUM_MWS, 1, hw->mw_cnt);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tfor (i = 0; i < hw->mw_cnt; i++) {\n+\t\tNTB_LOG(INFO, \"Local %u mw size: 0x%\"PRIx64\"\", i,\n+\t\t\t\thw->mw_size[i]);\n+\t\tval = hw->mw_size[i] >> 32;\n+\t\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_MW0_SZ_H + 2 * i,\n+\t\t\t\t\t\t 1, val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tval = hw->mw_size[i];\n+\t\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_MW0_SZ_L + 2 * i,\n+\t\t\t\t\t\t 1, val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Tell peer about the queue info and map memory to the peer. */\n+\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_Q_SZ, 1, hw->queue_size);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_NUM_QPS, 1,\n+\t\t\t\t\t hw->queue_pairs);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_USED_MWS, 1,\n+\t\t\t\t\t hw->used_mw_num);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tfor (i = 0; i < hw->used_mw_num; i++) {\n+\t\tval = (uint64_t)(hw->mz[i]->addr) >> 32;\n+\t\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_MW0_BA_H + 2 * i,\n+\t\t\t\t\t\t 1, val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tval = (uint64_t)(hw->mz[i]->addr);\n+\t\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_MW0_BA_L + 2 * i,\n+\t\t\t\t\t\t 1, val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < hw->used_mw_num; i++) {\n+\t\tret = (*hw->ntb_ops->mw_set_trans)(dev, i, hw->mz[i]->iova,\n+\t\t\t\t\t\t hw->mz[i]->len);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Ring doorbell 0 to tell peer the device is ready. */\n+\tret = (*hw->ntb_ops->peer_db_set)(dev, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n static void\n ntb_dev_intr_handler(void *param)\n {\n \tstruct rte_rawdev *dev = (struct rte_rawdev *)param;\n \tstruct ntb_hw *hw = dev->dev_private;\n-\tuint32_t mw_size_h, mw_size_l;\n+\tuint32_t val_h, val_l;\n+\tuint64_t peer_mw_size;\n \tuint64_t db_bits = 0;\n+\tuint8_t peer_mw_cnt;\n \tint i = 0;\n \n \tif (hw->ntb_ops->db_read == NULL ||\n@@ -118,7 +153,7 @@ ntb_dev_intr_handler(void *param)\n \n \t/* Doorbell 0 is for peer device ready. */\n \tif (db_bits & 1) {\n-\t\tNTB_LOG(DEBUG, \"DB0: Peer device is up.\");\n+\t\tNTB_LOG(INFO, \"DB0: Peer device is up.\");\n \t\t/* Clear received doorbell. */\n \t\t(*hw->ntb_ops->db_clear)(dev, 1);\n \n@@ -129,47 +164,44 @@ ntb_dev_intr_handler(void *param)\n \t\tif (hw->peer_dev_up)\n \t\t\treturn;\n \n-\t\tif (hw->ntb_ops->spad_read == NULL ||\n-\t\t hw->ntb_ops->spad_write == NULL) {\n-\t\t\tNTB_LOG(ERR, \"Scratchpad is not supported.\");\n+\t\tif (hw->ntb_ops->spad_read == NULL) {\n+\t\t\tNTB_LOG(ERR, \"Scratchpad read is not supported.\");\n+\t\t\treturn;\n+\t\t}\n+\n+\t\t/* Check if mw setting on the peer is the same as local. */\n+\t\tpeer_mw_cnt = (*hw->ntb_ops->spad_read)(dev, SPAD_NUM_MWS, 0);\n+\t\tif (peer_mw_cnt != hw->mw_cnt) {\n+\t\t\tNTB_LOG(ERR, \"Both mw cnt must be the same.\");\n \t\t\treturn;\n \t\t}\n \n-\t\thw->peer_mw_cnt = (*hw->ntb_ops->spad_read)\n-\t\t\t\t (dev, SPAD_NUM_MWS, 0);\n-\t\thw->peer_mw_size = rte_zmalloc(\"uint64_t\",\n-\t\t\t\t hw->peer_mw_cnt * sizeof(uint64_t), 0);\n \t\tfor (i = 0; i < hw->mw_cnt; i++) {\n-\t\t\tmw_size_h = (*hw->ntb_ops->spad_read)\n-\t\t\t\t (dev, SPAD_MW0_SZ_H + 2 * i, 0);\n-\t\t\tmw_size_l = (*hw->ntb_ops->spad_read)\n-\t\t\t\t (dev, SPAD_MW0_SZ_L + 2 * i, 0);\n-\t\t\thw->peer_mw_size[i] = ((uint64_t)mw_size_h << 32) |\n-\t\t\t\t\t mw_size_l;\n+\t\t\tval_h = (*hw->ntb_ops->spad_read)\n+\t\t\t\t(dev, SPAD_MW0_SZ_H + 2 * i, 0);\n+\t\t\tval_l = (*hw->ntb_ops->spad_read)\n+\t\t\t\t(dev, SPAD_MW0_SZ_L + 2 * i, 0);\n+\t\t\tpeer_mw_size = ((uint64_t)val_h << 32) | val_l;\n \t\t\tNTB_LOG(DEBUG, \"Peer %u mw size: 0x%\"PRIx64\"\", i,\n-\t\t\t\t\thw->peer_mw_size[i]);\n+\t\t\t\t\tpeer_mw_size);\n+\t\t\tif (peer_mw_size != hw->mw_size[i]) {\n+\t\t\t\tNTB_LOG(ERR, \"Mw config must be the same.\");\n+\t\t\t\treturn;\n+\t\t\t}\n \t\t}\n \n \t\thw->peer_dev_up = 1;\n \n \t\t/**\n-\t\t * Handshake with peer. Spad_write only works when both\n-\t\t * devices are up. So write spad again when db is received.\n-\t\t * And set db again for the later device who may miss\n+\t\t * Handshake with peer. Spad_write & mw_set_trans only works\n+\t\t * when both devices are up. So write spad again when db is\n+\t\t * received. And set db again for the later device who may miss\n \t\t * the 1st db.\n \t\t */\n-\t\tfor (i = 0; i < hw->mw_cnt; i++) {\n-\t\t\t(*hw->ntb_ops->spad_write)(dev, SPAD_NUM_MWS,\n-\t\t\t\t\t\t 1, hw->mw_cnt);\n-\t\t\tmw_size_h = hw->mw_size[i] >> 32;\n-\t\t\t(*hw->ntb_ops->spad_write)(dev, SPAD_MW0_SZ_H + 2 * i,\n-\t\t\t\t\t\t 1, mw_size_h);\n-\n-\t\t\tmw_size_l = hw->mw_size[i];\n-\t\t\t(*hw->ntb_ops->spad_write)(dev, SPAD_MW0_SZ_L + 2 * i,\n-\t\t\t\t\t\t 1, mw_size_l);\n+\t\tif (ntb_handshake_work(dev) < 0) {\n+\t\t\tNTB_LOG(ERR, \"Handshake work failed.\");\n+\t\t\treturn;\n \t\t}\n-\t\t(*hw->ntb_ops->peer_db_set)(dev, 0);\n \n \t\t/* To get the link info. */\n \t\tif (hw->ntb_ops->get_link_status == NULL) {\n@@ -183,7 +215,7 @@ ntb_dev_intr_handler(void *param)\n \t}\n \n \tif (db_bits & (1 << 1)) {\n-\t\tNTB_LOG(DEBUG, \"DB1: Peer device is down.\");\n+\t\tNTB_LOG(INFO, \"DB1: Peer device is down.\");\n \t\t/* Clear received doorbell. */\n \t\t(*hw->ntb_ops->db_clear)(dev, 2);\n \n@@ -197,7 +229,7 @@ ntb_dev_intr_handler(void *param)\n \t}\n \n \tif (db_bits & (1 << 2)) {\n-\t\tNTB_LOG(DEBUG, \"DB2: Peer device agrees dev to be down.\");\n+\t\tNTB_LOG(INFO, \"DB2: Peer device agrees dev to be down.\");\n \t\t/* Clear received doorbell. */\n \t\t(*hw->ntb_ops->db_clear)(dev, (1 << 2));\n \t\thw->peer_dev_up = 0;\n@@ -206,24 +238,228 @@ ntb_dev_intr_handler(void *param)\n }\n \n static void\n-ntb_queue_conf_get(struct rte_rawdev *dev __rte_unused,\n-\t\t uint16_t queue_id __rte_unused,\n-\t\t rte_rawdev_obj_t queue_conf __rte_unused)\n+ntb_queue_conf_get(struct rte_rawdev *dev,\n+\t\t uint16_t queue_id,\n+\t\t rte_rawdev_obj_t queue_conf)\n+{\n+\tstruct ntb_queue_conf *q_conf = queue_conf;\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\n+\tq_conf->tx_free_thresh = hw->tx_queues[queue_id]->tx_free_thresh;\n+\tq_conf->nb_desc = hw->rx_queues[queue_id]->nb_rx_desc;\n+\tq_conf->rx_mp = hw->rx_queues[queue_id]->mpool;\n+}\n+\n+static void\n+ntb_rxq_release_mbufs(struct ntb_rx_queue *q)\n+{\n+\tint i;\n+\n+\tif (!q || !q->sw_ring) {\n+\t\tNTB_LOG(ERR, \"Pointer to rxq or sw_ring is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < q->nb_rx_desc; i++) {\n+\t\tif (q->sw_ring[i].mbuf) {\n+\t\t\trte_pktmbuf_free_seg(q->sw_ring[i].mbuf);\n+\t\t\tq->sw_ring[i].mbuf = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static void\n+ntb_rxq_release(struct ntb_rx_queue *rxq)\n+{\n+\tif (!rxq) {\n+\t\tNTB_LOG(ERR, \"Pointer to rxq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tntb_rxq_release_mbufs(rxq);\n+\n+\trte_free(rxq->sw_ring);\n+\trte_free(rxq);\n+}\n+\n+static int\n+ntb_rxq_setup(struct rte_rawdev *dev,\n+\t uint16_t qp_id,\n+\t rte_rawdev_obj_t queue_conf)\n+{\n+\tstruct ntb_queue_conf *rxq_conf = queue_conf;\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tstruct ntb_rx_queue *rxq;\n+\n+\t/* Allocate the rx queue data structure */\n+\trxq = rte_zmalloc_socket(\"ntb rx queue\",\n+\t\t\t\t sizeof(struct ntb_rx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t dev->socket_id);\n+\tif (!rxq) {\n+\t\tNTB_LOG(ERR, \"Failed to allocate memory for \"\n+\t\t\t \"rx queue data structure.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (rxq_conf->rx_mp == NULL) {\n+\t\tNTB_LOG(ERR, \"Invalid null mempool pointer.\");\n+\t\treturn -EINVAL;\n+\t}\n+\trxq->nb_rx_desc = rxq_conf->nb_desc;\n+\trxq->mpool = rxq_conf->rx_mp;\n+\trxq->port_id = dev->dev_id;\n+\trxq->queue_id = qp_id;\n+\trxq->hw = hw;\n+\n+\t/* Allocate the software ring. */\n+\trxq->sw_ring =\n+\t\trte_zmalloc_socket(\"ntb rx sw ring\",\n+\t\t\t\t sizeof(struct ntb_rx_entry) *\n+\t\t\t\t rxq->nb_rx_desc,\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t dev->socket_id);\n+\tif (!rxq->sw_ring) {\n+\t\tntb_rxq_release(rxq);\n+\t\tNTB_LOG(ERR, \"Failed to allocate memory for SW ring\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\thw->rx_queues[qp_id] = rxq;\n+\n+\treturn 0;\n+}\n+\n+static void\n+ntb_txq_release_mbufs(struct ntb_tx_queue *q)\n+{\n+\tint i;\n+\n+\tif (!q || !q->sw_ring) {\n+\t\tNTB_LOG(ERR, \"Pointer to txq or sw_ring is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < q->nb_tx_desc; i++) {\n+\t\tif (q->sw_ring[i].mbuf) {\n+\t\t\trte_pktmbuf_free_seg(q->sw_ring[i].mbuf);\n+\t\t\tq->sw_ring[i].mbuf = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static void\n+ntb_txq_release(struct ntb_tx_queue *txq)\n {\n+\tif (!txq) {\n+\t\tNTB_LOG(ERR, \"Pointer to txq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tntb_txq_release_mbufs(txq);\n+\n+\trte_free(txq->sw_ring);\n+\trte_free(txq);\n }\n \n static int\n-ntb_queue_setup(struct rte_rawdev *dev __rte_unused,\n-\t\tuint16_t queue_id __rte_unused,\n-\t\trte_rawdev_obj_t queue_conf __rte_unused)\n+ntb_txq_setup(struct rte_rawdev *dev,\n+\t uint16_t qp_id,\n+\t rte_rawdev_obj_t queue_conf)\n {\n+\tstruct ntb_queue_conf *txq_conf = queue_conf;\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tstruct ntb_tx_queue *txq;\n+\tuint16_t i, prev;\n+\n+\t/* Allocate the TX queue data structure. */\n+\ttxq = rte_zmalloc_socket(\"ntb tx queue\",\n+\t\t\t\t sizeof(struct ntb_tx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t dev->socket_id);\n+\tif (!txq) {\n+\t\tNTB_LOG(ERR, \"Failed to allocate memory for \"\n+\t\t\t \"tx queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxq->nb_tx_desc = txq_conf->nb_desc;\n+\ttxq->port_id = dev->dev_id;\n+\ttxq->queue_id = qp_id;\n+\ttxq->hw = hw;\n+\n+\t/* Allocate software ring */\n+\ttxq->sw_ring =\n+\t\trte_zmalloc_socket(\"ntb tx sw ring\",\n+\t\t\t\t sizeof(struct ntb_tx_entry) *\n+\t\t\t\t txq->nb_tx_desc,\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t dev->socket_id);\n+\tif (!txq->sw_ring) {\n+\t\tntb_txq_release(txq);\n+\t\tNTB_LOG(ERR, \"Failed to allocate memory for SW TX ring\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tprev = txq->nb_tx_desc - 1;\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\ttxq->sw_ring[i].last_id = i;\n+\t\ttxq->sw_ring[prev].next_id = i;\n+\t\tprev = i;\n+\t}\n+\n+\ttxq->tx_free_thresh = txq_conf->tx_free_thresh ?\n+\t\t\t txq_conf->tx_free_thresh :\n+\t\t\t NTB_DFLT_TX_FREE_THRESH;\n+\tif (txq->tx_free_thresh >= txq->nb_tx_desc - 3) {\n+\t\tNTB_LOG(ERR, \"tx_free_thresh must be less than nb_desc - 3. \"\n+\t\t\t\"(tx_free_thresh=%u qp_id=%u)\", txq->tx_free_thresh,\n+\t\t\tqp_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->tx_queues[qp_id] = txq;\n+\n \treturn 0;\n }\n \n+\n+static int\n+ntb_queue_setup(struct rte_rawdev *dev,\n+\t\tuint16_t queue_id,\n+\t\trte_rawdev_obj_t queue_conf)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tint ret;\n+\n+\tif (queue_id > hw->queue_pairs)\n+\t\treturn -EINVAL;\n+\n+\tret = ntb_txq_setup(dev, queue_id, queue_conf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = ntb_rxq_setup(dev, queue_id, queue_conf);\n+\n+\treturn ret;\n+}\n+\n static int\n-ntb_queue_release(struct rte_rawdev *dev __rte_unused,\n-\t\t uint16_t queue_id __rte_unused)\n+ntb_queue_release(struct rte_rawdev *dev, uint16_t queue_id)\n {\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tstruct ntb_tx_queue *txq;\n+\tstruct ntb_rx_queue *rxq;\n+\n+\tif (queue_id > hw->queue_pairs)\n+\t\treturn -EINVAL;\n+\n+\ttxq = hw->tx_queues[queue_id];\n+\trxq = hw->rx_queues[queue_id];\n+\tntb_txq_release(txq);\n+\tntb_rxq_release(rxq);\n+\n \treturn 0;\n }\n \n@@ -234,6 +470,77 @@ ntb_queue_count(struct rte_rawdev *dev)\n \treturn hw->queue_pairs;\n }\n \n+static int\n+ntb_queue_init(struct rte_rawdev *dev, uint16_t qp_id)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tstruct ntb_rx_queue *rxq = hw->rx_queues[qp_id];\n+\tstruct ntb_tx_queue *txq = hw->tx_queues[qp_id];\n+\tvolatile struct ntb_header *local_hdr;\n+\tstruct ntb_header *remote_hdr;\n+\tuint16_t q_size = hw->queue_size;\n+\tuint32_t hdr_offset;\n+\tvoid *bar_addr;\n+\tuint16_t i;\n+\n+\tif (hw->ntb_ops->get_peer_mw_addr == NULL) {\n+\t\tNTB_LOG(ERR, \"Failed to get mapped peer addr.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Put queue info into the start of shared memory. */\n+\thdr_offset = hw->hdr_size_per_queue * qp_id;\n+\tlocal_hdr = (volatile struct ntb_header *)\n+\t\t ((uint64_t)hw->mz[0]->addr + hdr_offset);\n+\tbar_addr = (*hw->ntb_ops->get_peer_mw_addr)(dev, 0);\n+\tif (bar_addr == NULL)\n+\t\treturn -EINVAL;\n+\tremote_hdr = (struct ntb_header *)\n+\t\t ((uint64_t)bar_addr + hdr_offset);\n+\n+\t/* rxq init. */\n+\trxq->rx_desc_ring = (struct ntb_desc *)\n+\t\t\t (&remote_hdr->desc_ring);\n+\trxq->rx_used_ring = (volatile struct ntb_used *)\n+\t\t\t (&local_hdr->desc_ring[q_size]);\n+\trxq->avail_cnt = &remote_hdr->avail_cnt;\n+\trxq->used_cnt = &local_hdr->used_cnt;\n+\n+\tfor (i = 0; i < rxq->nb_rx_desc - 1; i++) {\n+\t\tstruct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mpool);\n+\t\tif (unlikely(!mbuf)) {\n+\t\t\tNTB_LOG(ERR, \"Failed to allocate mbuf for RX\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tmbuf->port = dev->dev_id;\n+\n+\t\trxq->sw_ring[i].mbuf = mbuf;\n+\n+\t\trxq->rx_desc_ring[i].addr = rte_pktmbuf_mtod(mbuf, uint64_t);\n+\t\trxq->rx_desc_ring[i].len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;\n+\t}\n+\trte_wmb();\n+\t*rxq->avail_cnt = rxq->nb_rx_desc - 1;\n+\trxq->last_avail = rxq->nb_rx_desc - 1;\n+\trxq->last_used = 0;\n+\n+\t/* txq init */\n+\ttxq->tx_desc_ring = (volatile struct ntb_desc *)\n+\t\t\t (&local_hdr->desc_ring);\n+\ttxq->tx_used_ring = (struct ntb_used *)\n+\t\t\t (&remote_hdr->desc_ring[q_size]);\n+\ttxq->avail_cnt = &local_hdr->avail_cnt;\n+\ttxq->used_cnt = &remote_hdr->used_cnt;\n+\n+\trte_wmb();\n+\t*txq->used_cnt = 0;\n+\ttxq->last_used = 0;\n+\ttxq->last_avail = 0;\n+\ttxq->nb_tx_free = txq->nb_tx_desc - 1;\n+\n+\treturn 0;\n+}\n+\n static int\n ntb_enqueue_bufs(struct rte_rawdev *dev,\n \t\t struct rte_rawdev_buf **buffers,\n@@ -278,58 +585,51 @@ static void\n ntb_dev_info_get(struct rte_rawdev *dev, rte_rawdev_obj_t dev_info)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n-\tstruct ntb_attr *ntb_attrs = dev_info;\n+\tstruct ntb_dev_info *info = dev_info;\n \n-\tstrncpy(ntb_attrs[NTB_TOPO_ID].name, NTB_TOPO_NAME, NTB_ATTR_NAME_LEN);\n-\tswitch (hw->topo) {\n-\tcase NTB_TOPO_B2B_DSD:\n-\t\tstrncpy(ntb_attrs[NTB_TOPO_ID].value, \"B2B DSD\",\n-\t\t\tNTB_ATTR_VAL_LEN);\n-\t\tbreak;\n-\tcase NTB_TOPO_B2B_USD:\n-\t\tstrncpy(ntb_attrs[NTB_TOPO_ID].value, \"B2B USD\",\n-\t\t\tNTB_ATTR_VAL_LEN);\n-\t\tbreak;\n-\tdefault:\n-\t\tstrncpy(ntb_attrs[NTB_TOPO_ID].value, \"Unsupported\",\n-\t\t\tNTB_ATTR_VAL_LEN);\n-\t}\n+\tinfo->mw_cnt = hw->mw_cnt;\n+\tinfo->mw_size = hw->mw_size;\n \n-\tstrncpy(ntb_attrs[NTB_LINK_STATUS_ID].name, NTB_LINK_STATUS_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_LINK_STATUS_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->link_status);\n-\n-\tstrncpy(ntb_attrs[NTB_SPEED_ID].name, NTB_SPEED_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_SPEED_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->link_speed);\n-\n-\tstrncpy(ntb_attrs[NTB_WIDTH_ID].name, NTB_WIDTH_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_WIDTH_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->link_width);\n-\n-\tstrncpy(ntb_attrs[NTB_MW_CNT_ID].name, NTB_MW_CNT_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_MW_CNT_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->mw_cnt);\n+\t/**\n+\t * Intel hardware requires that mapped memory base address should be\n+\t * aligned with EMBARSZ and needs continuous memzone.\n+\t */\n+\tinfo->mw_size_align = (uint8_t)(hw->pci_dev->id.vendor_id ==\n+\t\t\t\t\tNTB_INTEL_VENDOR_ID);\n \n-\tstrncpy(ntb_attrs[NTB_DB_CNT_ID].name, NTB_DB_CNT_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_DB_CNT_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->db_cnt);\n+\tif (!hw->queue_size || !hw->queue_pairs) {\n+\t\tNTB_LOG(ERR, \"No queue size and queue num assigned.\");\n+\t\treturn;\n+\t}\n \n-\tstrncpy(ntb_attrs[NTB_SPAD_CNT_ID].name, NTB_SPAD_CNT_NAME,\n-\t\tNTB_ATTR_NAME_LEN);\n-\tsnprintf(ntb_attrs[NTB_SPAD_CNT_ID].value, NTB_ATTR_VAL_LEN,\n-\t\t \"%d\", hw->spad_cnt);\n+\thw->hdr_size_per_queue = RTE_ALIGN(sizeof(struct ntb_header) +\n+\t\t\t\thw->queue_size * sizeof(struct ntb_desc) +\n+\t\t\t\thw->queue_size * sizeof(struct ntb_used),\n+\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\tinfo->ntb_hdr_size = hw->hdr_size_per_queue * hw->queue_pairs;\n }\n \n static int\n-ntb_dev_configure(const struct rte_rawdev *dev __rte_unused,\n-\t\t rte_rawdev_obj_t config __rte_unused)\n+ntb_dev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n {\n+\tstruct ntb_dev_config *conf = config;\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tint ret;\n+\n+\thw->queue_pairs\t= conf->num_queues;\n+\thw->queue_size = conf->queue_size;\n+\thw->used_mw_num = conf->mz_num;\n+\thw->mz = conf->mz_list;\n+\thw->rx_queues = rte_zmalloc(\"ntb_rx_queues\",\n+\t\t\tsizeof(struct ntb_rx_queue *) * hw->queue_pairs, 0);\n+\thw->tx_queues = rte_zmalloc(\"ntb_tx_queues\",\n+\t\t\tsizeof(struct ntb_tx_queue *) * hw->queue_pairs, 0);\n+\n+\t/* Start handshake with the peer. */\n+\tret = ntb_handshake_work(dev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \treturn 0;\n }\n \n@@ -337,21 +637,52 @@ static int\n ntb_dev_start(struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n-\tint ret, i;\n+\tuint32_t peer_base_l, peer_val;\n+\tuint64_t peer_base_h;\n+\tuint32_t i;\n+\tint ret;\n \n-\t/* TODO: init queues and start queues. */\n+\tif (!hw->link_status || !hw->peer_dev_up)\n+\t\treturn -EINVAL;\n \n-\t/* Map memory of bar_size to remote. */\n-\thw->mz = rte_zmalloc(\"struct rte_memzone *\",\n-\t\t\t hw->mw_cnt * sizeof(struct rte_memzone *), 0);\n-\tfor (i = 0; i < hw->mw_cnt; i++) {\n-\t\tret = ntb_set_mw(dev, i, hw->mw_size[i]);\n+\tfor (i = 0; i < hw->queue_pairs; i++) {\n+\t\tret = ntb_queue_init(dev, i);\n \t\tif (ret) {\n-\t\t\tNTB_LOG(ERR, \"Fail to set mw.\");\n+\t\t\tNTB_LOG(ERR, \"Failed to init queue.\");\n \t\t\treturn ret;\n \t\t}\n \t}\n \n+\thw->peer_mw_base = rte_zmalloc(\"ntb_peer_mw_base\", hw->mw_cnt *\n+\t\t\t\t\tsizeof(uint64_t), 0);\n+\n+\tif (hw->ntb_ops->spad_read == NULL)\n+\t\treturn -ENOTSUP;\n+\n+\tpeer_val = (*hw->ntb_ops->spad_read)(dev, SPAD_Q_SZ, 0);\n+\tif (peer_val != hw->queue_size) {\n+\t\tNTB_LOG(ERR, \"Inconsistent queue size! (local: %u peer: %u)\",\n+\t\t\thw->queue_size, peer_val);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpeer_val = (*hw->ntb_ops->spad_read)(dev, SPAD_NUM_QPS, 0);\n+\tif (peer_val != hw->queue_pairs) {\n+\t\tNTB_LOG(ERR, \"Inconsistent number of queues! (local: %u peer:\"\n+\t\t\t\" %u)\", hw->queue_pairs, peer_val);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->peer_used_mws = (*hw->ntb_ops->spad_read)(dev, SPAD_USED_MWS, 0);\n+\n+\tfor (i = 0; i < hw->peer_used_mws; i++) {\n+\t\tpeer_base_h = (*hw->ntb_ops->spad_read)(dev,\n+\t\t\t\tSPAD_MW0_BA_H + 2 * i, 0);\n+\t\tpeer_base_l = (*hw->ntb_ops->spad_read)(dev,\n+\t\t\t\tSPAD_MW0_BA_L + 2 * i, 0);\n+\t\thw->peer_mw_base[i] = (peer_base_h << 32) + peer_base_l;\n+\t}\n+\n \tdev->started = 1;\n \n \treturn 0;\n@@ -361,10 +692,10 @@ static void\n ntb_dev_stop(struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n+\tstruct ntb_rx_queue *rxq;\n+\tstruct ntb_tx_queue *txq;\n \tuint32_t time_out;\n-\tint status;\n-\n-\t/* TODO: stop rx/tx queues. */\n+\tint status, i;\n \n \tif (!hw->peer_dev_up)\n \t\tgoto clean;\n@@ -405,6 +736,13 @@ ntb_dev_stop(struct rte_rawdev *dev)\n \tif (status)\n \t\tNTB_LOG(ERR, \"Failed to clear doorbells.\");\n \n+\tfor (i = 0; i < hw->queue_pairs; i++) {\n+\t\trxq = hw->rx_queues[i];\n+\t\ttxq = hw->tx_queues[i];\n+\t\tntb_rxq_release_mbufs(rxq);\n+\t\tntb_txq_release_mbufs(txq);\n+\t}\n+\n \tdev->started = 0;\n }\n \n@@ -413,12 +751,15 @@ ntb_dev_close(struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tstruct rte_intr_handle *intr_handle;\n-\tint ret = 0;\n+\tint i;\n \n \tif (dev->started)\n \t\tntb_dev_stop(dev);\n \n-\t/* TODO: free queues. */\n+\t/* free queues */\n+\tfor (i = 0; i < hw->queue_pairs; i++)\n+\t\tntb_queue_release(dev, i);\n+\thw->queue_pairs = 0;\n \n \tintr_handle = &hw->pci_dev->intr_handle;\n \t/* Clean datapath event and vec mapping */\n@@ -434,7 +775,7 @@ ntb_dev_close(struct rte_rawdev *dev)\n \trte_intr_callback_unregister(intr_handle,\n \t\t\t\t ntb_dev_intr_handler, dev);\n \n-\treturn ret;\n+\treturn 0;\n }\n \n static int\n@@ -445,7 +786,7 @@ ntb_dev_reset(struct rte_rawdev *rawdev __rte_unused)\n \n static int\n ntb_attr_set(struct rte_rawdev *dev, const char *attr_name,\n-\t\t\t\t uint64_t attr_value)\n+\t uint64_t attr_value)\n {\n \tstruct ntb_hw *hw;\n \tint index;\n@@ -463,7 +804,21 @@ ntb_attr_set(struct rte_rawdev *dev, const char *attr_name,\n \t\tindex = atoi(&attr_name[NTB_SPAD_USER_LEN]);\n \t\t(*hw->ntb_ops->spad_write)(dev, hw->spad_user_list[index],\n \t\t\t\t\t 1, attr_value);\n-\t\tNTB_LOG(INFO, \"Set attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Set attribute (%s) Value (%\" PRIu64 \")\",\n+\t\t\tattr_name, attr_value);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!strncmp(attr_name, NTB_QUEUE_SZ_NAME, NTB_ATTR_NAME_LEN)) {\n+\t\thw->queue_size = attr_value;\n+\t\tNTB_LOG(DEBUG, \"Set attribute (%s) Value (%\" PRIu64 \")\",\n+\t\t\tattr_name, attr_value);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!strncmp(attr_name, NTB_QUEUE_NUM_NAME, NTB_ATTR_NAME_LEN)) {\n+\t\thw->queue_pairs = attr_value;\n+\t\tNTB_LOG(DEBUG, \"Set attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, attr_value);\n \t\treturn 0;\n \t}\n@@ -475,7 +830,7 @@ ntb_attr_set(struct rte_rawdev *dev, const char *attr_name,\n \n static int\n ntb_attr_get(struct rte_rawdev *dev, const char *attr_name,\n-\t\t\t\t uint64_t *attr_value)\n+\t uint64_t *attr_value)\n {\n \tstruct ntb_hw *hw;\n \tint index;\n@@ -489,49 +844,50 @@ ntb_attr_get(struct rte_rawdev *dev, const char *attr_name,\n \n \tif (!strncmp(attr_name, NTB_TOPO_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->topo;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_LINK_STATUS_NAME, NTB_ATTR_NAME_LEN)) {\n-\t\t*attr_value = hw->link_status;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\t/* hw->link_status only indicates hw link status. */\n+\t\t*attr_value = hw->link_status && hw->peer_dev_up;\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_SPEED_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->link_speed;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_WIDTH_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->link_width;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_MW_CNT_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->mw_cnt;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_DB_CNT_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->db_cnt;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n \n \tif (!strncmp(attr_name, NTB_SPAD_CNT_NAME, NTB_ATTR_NAME_LEN)) {\n \t\t*attr_value = hw->spad_cnt;\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n@@ -542,7 +898,7 @@ ntb_attr_get(struct rte_rawdev *dev, const char *attr_name,\n \t\tindex = atoi(&attr_name[NTB_SPAD_USER_LEN]);\n \t\t*attr_value = (*hw->ntb_ops->spad_read)(dev,\n \t\t\t\thw->spad_user_list[index], 0);\n-\t\tNTB_LOG(INFO, \"Attribute (%s) Value (%\" PRIu64 \")\",\n+\t\tNTB_LOG(DEBUG, \"Attribute (%s) Value (%\" PRIu64 \")\",\n \t\t\tattr_name, *attr_value);\n \t\treturn 0;\n \t}\n@@ -585,6 +941,7 @@ ntb_xstats_reset(struct rte_rawdev *dev __rte_unused,\n \treturn 0;\n }\n \n+\n static const struct rte_rawdev_ops ntb_ops = {\n \t.dev_info_get = ntb_dev_info_get,\n \t.dev_configure = ntb_dev_configure,\n@@ -615,7 +972,6 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tstruct rte_intr_handle *intr_handle;\n-\tuint32_t val;\n \tint ret, i;\n \n \thw->pci_dev = pci_dev;\n@@ -688,45 +1044,6 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)\n \t/* enable uio intr after callback register */\n \trte_intr_enable(intr_handle);\n \n-\tif (hw->ntb_ops->spad_write == NULL) {\n-\t\tNTB_LOG(ERR, \"Scratchpad is not supported.\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\t/* Tell peer the mw_cnt of local side. */\n-\tret = (*hw->ntb_ops->spad_write)(dev, SPAD_NUM_MWS, 1, hw->mw_cnt);\n-\tif (ret) {\n-\t\tNTB_LOG(ERR, \"Failed to tell peer mw count.\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Tell peer each mw size on local side. */\n-\tfor (i = 0; i < hw->mw_cnt; i++) {\n-\t\tNTB_LOG(DEBUG, \"Local %u mw size: 0x%\"PRIx64\"\", i,\n-\t\t\t\thw->mw_size[i]);\n-\t\tval = hw->mw_size[i] >> 32;\n-\t\tret = (*hw->ntb_ops->spad_write)\n-\t\t\t\t(dev, SPAD_MW0_SZ_H + 2 * i, 1, val);\n-\t\tif (ret) {\n-\t\t\tNTB_LOG(ERR, \"Failed to tell peer mw size.\");\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tval = hw->mw_size[i];\n-\t\tret = (*hw->ntb_ops->spad_write)\n-\t\t\t\t(dev, SPAD_MW0_SZ_L + 2 * i, 1, val);\n-\t\tif (ret) {\n-\t\t\tNTB_LOG(ERR, \"Failed to tell peer mw size.\");\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\t/* Ring doorbell 0 to tell peer the device is ready. */\n-\tret = (*hw->ntb_ops->peer_db_set)(dev, 0);\n-\tif (ret) {\n-\t\tNTB_LOG(ERR, \"Failed to tell peer device is probed.\");\n-\t\treturn ret;\n-\t}\n-\n \treturn ret;\n }\n \n@@ -839,5 +1156,5 @@ RTE_INIT(ntb_init_log)\n {\n \tntb_logtype = rte_log_register(\"pmd.raw.ntb\");\n \tif (ntb_logtype >= 0)\n-\t\trte_log_set_level(ntb_logtype, RTE_LOG_DEBUG);\n+\t\trte_log_set_level(ntb_logtype, RTE_LOG_INFO);\n }\ndiff --git a/drivers/raw/ntb/ntb.h b/drivers/raw/ntb/ntb.h\nindex d355231b0..0ad20aed3 100644\n--- a/drivers/raw/ntb/ntb.h\n+++ b/drivers/raw/ntb/ntb.h\n@@ -2,8 +2,8 @@\n * Copyright(c) 2019 Intel Corporation.\n */\n \n-#ifndef _NTB_RAWDEV_H_\n-#define _NTB_RAWDEV_H_\n+#ifndef _NTB_H_\n+#define _NTB_H_\n \n #include <stdbool.h>\n \n@@ -19,38 +19,13 @@ extern int ntb_logtype;\n /* Device IDs */\n #define NTB_INTEL_DEV_ID_B2B_SKX 0x201C\n \n-#define NTB_TOPO_NAME \"topo\"\n-#define NTB_LINK_STATUS_NAME \"link_status\"\n-#define NTB_SPEED_NAME \"speed\"\n-#define NTB_WIDTH_NAME \"width\"\n-#define NTB_MW_CNT_NAME \"mw_count\"\n-#define NTB_DB_CNT_NAME \"db_count\"\n-#define NTB_SPAD_CNT_NAME \"spad_count\"\n /* Reserved to app to use. */\n #define NTB_SPAD_USER \"spad_user_\"\n #define NTB_SPAD_USER_LEN (sizeof(NTB_SPAD_USER) - 1)\n-#define NTB_SPAD_USER_MAX_NUM 10\n+#define NTB_SPAD_USER_MAX_NUM 4\n #define NTB_ATTR_NAME_LEN 30\n-#define NTB_ATTR_VAL_LEN 30\n-#define NTB_ATTR_MAX 20\n-\n-/* NTB Attributes */\n-struct ntb_attr {\n-\t/**< Name of the attribute */\n-\tchar name[NTB_ATTR_NAME_LEN];\n-\t/**< Value or reference of value of attribute */\n-\tchar value[NTB_ATTR_NAME_LEN];\n-};\n \n-enum ntb_attr_idx {\n-\tNTB_TOPO_ID = 0,\n-\tNTB_LINK_STATUS_ID,\n-\tNTB_SPEED_ID,\n-\tNTB_WIDTH_ID,\n-\tNTB_MW_CNT_ID,\n-\tNTB_DB_CNT_ID,\n-\tNTB_SPAD_CNT_ID,\n-};\n+#define NTB_DFLT_TX_FREE_THRESH 256\n \n enum ntb_topo {\n \tNTB_TOPO_NONE = 0,\n@@ -87,10 +62,15 @@ enum ntb_spad_idx {\n \tSPAD_NUM_MWS = 1,\n \tSPAD_NUM_QPS,\n \tSPAD_Q_SZ,\n+\tSPAD_USED_MWS,\n \tSPAD_MW0_SZ_H,\n \tSPAD_MW0_SZ_L,\n \tSPAD_MW1_SZ_H,\n \tSPAD_MW1_SZ_L,\n+\tSPAD_MW0_BA_H,\n+\tSPAD_MW0_BA_L,\n+\tSPAD_MW1_BA_H,\n+\tSPAD_MW1_BA_L,\n };\n \n /**\n@@ -110,26 +90,97 @@ enum ntb_spad_idx {\n * @vector_bind: Bind vector source [intr] to msix vector [msix].\n */\n struct ntb_dev_ops {\n-\tint (*ntb_dev_init)(struct rte_rawdev *dev);\n-\tvoid *(*get_peer_mw_addr)(struct rte_rawdev *dev, int mw_idx);\n-\tint (*mw_set_trans)(struct rte_rawdev *dev, int mw_idx,\n+\tint (*ntb_dev_init)(const struct rte_rawdev *dev);\n+\tvoid *(*get_peer_mw_addr)(const struct rte_rawdev *dev, int mw_idx);\n+\tint (*mw_set_trans)(const struct rte_rawdev *dev, int mw_idx,\n \t\t\t uint64_t addr, uint64_t size);\n-\tint (*get_link_status)(struct rte_rawdev *dev);\n-\tint (*set_link)(struct rte_rawdev *dev, bool up);\n-\tuint32_t (*spad_read)(struct rte_rawdev *dev, int spad, bool peer);\n-\tint (*spad_write)(struct rte_rawdev *dev, int spad,\n+\tint (*get_link_status)(const struct rte_rawdev *dev);\n+\tint (*set_link)(const struct rte_rawdev *dev, bool up);\n+\tuint32_t (*spad_read)(const struct rte_rawdev *dev, int spad,\n+\t\t\t bool peer);\n+\tint (*spad_write)(const struct rte_rawdev *dev, int spad,\n \t\t\t bool peer, uint32_t spad_v);\n-\tuint64_t (*db_read)(struct rte_rawdev *dev);\n-\tint (*db_clear)(struct rte_rawdev *dev, uint64_t db_bits);\n-\tint (*db_set_mask)(struct rte_rawdev *dev, uint64_t db_mask);\n-\tint (*peer_db_set)(struct rte_rawdev *dev, uint8_t db_bit);\n-\tint (*vector_bind)(struct rte_rawdev *dev, uint8_t intr, uint8_t msix);\n+\tuint64_t (*db_read)(const struct rte_rawdev *dev);\n+\tint (*db_clear)(const struct rte_rawdev *dev, uint64_t db_bits);\n+\tint (*db_set_mask)(const struct rte_rawdev *dev, uint64_t db_mask);\n+\tint (*peer_db_set)(const struct rte_rawdev *dev, uint8_t db_bit);\n+\tint (*vector_bind)(const struct rte_rawdev *dev, uint8_t intr,\n+\t\t\t uint8_t msix);\n+};\n+\n+struct ntb_desc {\n+\tuint64_t addr; /* buffer addr */\n+\tuint16_t len; /* buffer length */\n+\tuint16_t rsv1;\n+\tuint32_t rsv2;\n+};\n+\n+struct ntb_used {\n+\tuint16_t len; /* buffer length */\n+#define NTB_FLAG_EOP 1 /* end of packet */\n+\tuint16_t flags; /* flags */\n+};\n+\n+struct ntb_rx_entry {\n+\tstruct rte_mbuf *mbuf;\n+};\n+\n+struct ntb_rx_queue {\n+\tstruct ntb_desc *rx_desc_ring;\n+\tvolatile struct ntb_used *rx_used_ring;\n+\tuint16_t *avail_cnt;\n+\tvolatile uint16_t *used_cnt;\n+\tuint16_t last_avail;\n+\tuint16_t last_used;\n+\tuint16_t nb_rx_desc;\n+\n+\tuint16_t rx_free_thresh;\n+\n+\tstruct rte_mempool *mpool; /**< mempool for mbuf allocation */\n+\tstruct ntb_rx_entry *sw_ring;\n+\n+\tuint16_t queue_id; /**< DPDK queue index. */\n+\tuint16_t port_id; /**< Device port identifier. */\n+\n+\tstruct ntb_hw *hw;\n+};\n+\n+struct ntb_tx_entry {\n+\tstruct rte_mbuf *mbuf;\n+\tuint16_t next_id;\n+\tuint16_t last_id;\n+};\n+\n+struct ntb_tx_queue {\n+\tvolatile struct ntb_desc *tx_desc_ring;\n+\tstruct ntb_used *tx_used_ring;\n+\tvolatile uint16_t *avail_cnt;\n+\tuint16_t *used_cnt;\n+\tuint16_t last_avail; /**< Next need to be free. */\n+\tuint16_t last_used; /**< Next need to be sent. */\n+\tuint16_t nb_tx_desc;\n+\n+\t/**< Total number of TX descriptors ready to be allocated. */\n+\tuint16_t nb_tx_free;\n+\tuint16_t tx_free_thresh;\n+\n+\tstruct ntb_tx_entry *sw_ring;\n+\n+\tuint16_t queue_id; /**< DPDK queue index. */\n+\tuint16_t port_id; /**< Device port identifier. */\n+\n+\tstruct ntb_hw *hw;\n+};\n+\n+struct ntb_header {\n+\tuint16_t avail_cnt __rte_cache_aligned;\n+\tuint16_t used_cnt __rte_cache_aligned;\n+\tstruct ntb_desc desc_ring[] __rte_cache_aligned;\n };\n \n /* ntb private data. */\n struct ntb_hw {\n \tuint8_t mw_cnt;\n-\tuint8_t peer_mw_cnt;\n \tuint8_t db_cnt;\n \tuint8_t spad_cnt;\n \n@@ -147,18 +198,26 @@ struct ntb_hw {\n \tstruct rte_pci_device *pci_dev;\n \tchar *hw_addr;\n \n-\tuint64_t *mw_size;\n-\tuint64_t *peer_mw_size;\n \tuint8_t peer_dev_up;\n+\tuint64_t *mw_size;\n+\t/* remote mem base addr */\n+\tuint64_t *peer_mw_base;\n \n \tuint16_t queue_pairs;\n \tuint16_t queue_size;\n+\tuint32_t hdr_size_per_queue;\n+\n+\tstruct ntb_rx_queue **rx_queues;\n+\tstruct ntb_tx_queue **tx_queues;\n \n-\t/**< mem zone to populate RX ring. */\n+\t/* memzone to populate RX ring. */\n \tconst struct rte_memzone **mz;\n+\tuint8_t used_mw_num;\n+\n+\tuint8_t peer_used_mws;\n \n \t/* Reserve several spad for app to use. */\n \tint spad_user_list[NTB_SPAD_USER_MAX_NUM];\n };\n \n-#endif /* _NTB_RAWDEV_H_ */\n+#endif /* _NTB_H_ */\ndiff --git a/drivers/raw/ntb/ntb_hw_intel.c b/drivers/raw/ntb/ntb_hw_intel.c\nindex 21eaa8511..0e73f1609 100644\n--- a/drivers/raw/ntb/ntb_hw_intel.c\n+++ b/drivers/raw/ntb/ntb_hw_intel.c\n@@ -26,7 +26,7 @@ static enum xeon_ntb_bar intel_ntb_bar[] = {\n };\n \n static int\n-intel_ntb_dev_init(struct rte_rawdev *dev)\n+intel_ntb_dev_init(const struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint8_t reg_val, bar;\n@@ -77,7 +77,7 @@ intel_ntb_dev_init(struct rte_rawdev *dev)\n \thw->db_cnt = XEON_DB_COUNT;\n \thw->spad_cnt = XEON_SPAD_COUNT;\n \n-\thw->mw_size = rte_zmalloc(\"uint64_t\",\n+\thw->mw_size = rte_zmalloc(\"ntb_mw_size\",\n \t\t\t\t hw->mw_cnt * sizeof(uint64_t), 0);\n \tfor (i = 0; i < hw->mw_cnt; i++) {\n \t\tbar = intel_ntb_bar[i];\n@@ -94,7 +94,7 @@ intel_ntb_dev_init(struct rte_rawdev *dev)\n }\n \n static void *\n-intel_ntb_get_peer_mw_addr(struct rte_rawdev *dev, int mw_idx)\n+intel_ntb_get_peer_mw_addr(const struct rte_rawdev *dev, int mw_idx)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint8_t bar;\n@@ -116,7 +116,7 @@ intel_ntb_get_peer_mw_addr(struct rte_rawdev *dev, int mw_idx)\n }\n \n static int\n-intel_ntb_mw_set_trans(struct rte_rawdev *dev, int mw_idx,\n+intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,\n \t\t uint64_t addr, uint64_t size)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n@@ -163,7 +163,7 @@ intel_ntb_mw_set_trans(struct rte_rawdev *dev, int mw_idx,\n }\n \n static int\n-intel_ntb_get_link_status(struct rte_rawdev *dev)\n+intel_ntb_get_link_status(const struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint16_t reg_val;\n@@ -195,7 +195,7 @@ intel_ntb_get_link_status(struct rte_rawdev *dev)\n }\n \n static int\n-intel_ntb_set_link(struct rte_rawdev *dev, bool up)\n+intel_ntb_set_link(const struct rte_rawdev *dev, bool up)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint32_t ntb_ctrl, reg_off;\n@@ -221,7 +221,7 @@ intel_ntb_set_link(struct rte_rawdev *dev, bool up)\n }\n \n static uint32_t\n-intel_ntb_spad_read(struct rte_rawdev *dev, int spad, bool peer)\n+intel_ntb_spad_read(const struct rte_rawdev *dev, int spad, bool peer)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint32_t spad_v, reg_off;\n@@ -241,7 +241,7 @@ intel_ntb_spad_read(struct rte_rawdev *dev, int spad, bool peer)\n }\n \n static int\n-intel_ntb_spad_write(struct rte_rawdev *dev, int spad,\n+intel_ntb_spad_write(const struct rte_rawdev *dev, int spad,\n \t\t bool peer, uint32_t spad_v)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n@@ -263,7 +263,7 @@ intel_ntb_spad_write(struct rte_rawdev *dev, int spad,\n }\n \n static uint64_t\n-intel_ntb_db_read(struct rte_rawdev *dev)\n+intel_ntb_db_read(const struct rte_rawdev *dev)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint64_t db_off, db_bits;\n@@ -278,7 +278,7 @@ intel_ntb_db_read(struct rte_rawdev *dev)\n }\n \n static int\n-intel_ntb_db_clear(struct rte_rawdev *dev, uint64_t db_bits)\n+intel_ntb_db_clear(const struct rte_rawdev *dev, uint64_t db_bits)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint64_t db_off;\n@@ -293,7 +293,7 @@ intel_ntb_db_clear(struct rte_rawdev *dev, uint64_t db_bits)\n }\n \n static int\n-intel_ntb_db_set_mask(struct rte_rawdev *dev, uint64_t db_mask)\n+intel_ntb_db_set_mask(const struct rte_rawdev *dev, uint64_t db_mask)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint64_t db_m_off;\n@@ -312,7 +312,7 @@ intel_ntb_db_set_mask(struct rte_rawdev *dev, uint64_t db_mask)\n }\n \n static int\n-intel_ntb_peer_db_set(struct rte_rawdev *dev, uint8_t db_idx)\n+intel_ntb_peer_db_set(const struct rte_rawdev *dev, uint8_t db_idx)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint32_t db_off;\n@@ -332,7 +332,7 @@ intel_ntb_peer_db_set(struct rte_rawdev *dev, uint8_t db_idx)\n }\n \n static int\n-intel_ntb_vector_bind(struct rte_rawdev *dev, uint8_t intr, uint8_t msix)\n+intel_ntb_vector_bind(const struct rte_rawdev *dev, uint8_t intr, uint8_t msix)\n {\n \tstruct ntb_hw *hw = dev->dev_private;\n \tuint8_t reg_off;\ndiff --git a/drivers/raw/ntb/rte_pmd_ntb.h b/drivers/raw/ntb/rte_pmd_ntb.h\nnew file mode 100644\nindex 000000000..6591ce793\n--- /dev/null\n+++ b/drivers/raw/ntb/rte_pmd_ntb.h\n@@ -0,0 +1,43 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation.\n+ */\n+\n+#ifndef _RTE_PMD_NTB_H_\n+#define _RTE_PMD_NTB_H_\n+\n+/* App needs to set/get these attrs */\n+#define NTB_QUEUE_SZ_NAME \"queue_size\"\n+#define NTB_QUEUE_NUM_NAME \"queue_num\"\n+#define NTB_TOPO_NAME \"topo\"\n+#define NTB_LINK_STATUS_NAME \"link_status\"\n+#define NTB_SPEED_NAME \"speed\"\n+#define NTB_WIDTH_NAME \"width\"\n+#define NTB_MW_CNT_NAME \"mw_count\"\n+#define NTB_DB_CNT_NAME \"db_count\"\n+#define NTB_SPAD_CNT_NAME \"spad_count\"\n+\n+#define NTB_MAX_DESC_SIZE 1024\n+#define NTB_MIN_DESC_SIZE 64\n+\n+struct ntb_dev_info {\n+\tuint32_t ntb_hdr_size;\n+\t/**< memzone needs to be mw size align or not. */\n+\tuint8_t mw_size_align;\n+\tuint8_t mw_cnt;\n+\tuint64_t *mw_size;\n+};\n+\n+struct ntb_dev_config {\n+\tuint16_t num_queues;\n+\tuint16_t queue_size;\n+\tuint8_t mz_num;\n+\tconst struct rte_memzone **mz_list;\n+};\n+\n+struct ntb_queue_conf {\n+\tuint16_t nb_desc;\n+\tuint16_t tx_free_thresh;\n+\tstruct rte_mempool *rx_mp;\n+};\n+\n+#endif /* _RTE_PMD_NTB_H_ */\n", "prefixes": [ "1/4" ] }