Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/58024/?format=api
{ "id": 58024, "url": "http://patches.dpdk.org/api/patches/58024/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190827070730.11206-30-sachin.saxena@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190827070730.11206-30-sachin.saxena@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190827070730.11206-30-sachin.saxena@nxp.com", "date": "2019-08-27T07:07:29", "name": "[v1,29/30] net/dpaa2: add support for soft parser in MC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "90b9f1f4c4671a452a8857db2627840d242ca1f3", "submitter": { "id": 1054, "url": "http://patches.dpdk.org/api/people/1054/?format=api", "name": "Sachin Saxena", "email": "sachin.saxena@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190827070730.11206-30-sachin.saxena@nxp.com/mbox/", "series": [ { "id": 6130, "url": "http://patches.dpdk.org/api/series/6130/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6130", "date": "2019-08-27T07:07:00", "name": "Enhancements and fixes in NXP dpaax drivers and fsl-mc bus", "version": 1, "mbox": "http://patches.dpdk.org/series/6130/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58024/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/58024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 34F971C1DA;\n\tTue, 27 Aug 2019 09:10:44 +0200 (CEST)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby dpdk.org (Postfix) with ESMTP id AB6181C034\n\tfor <dev@dpdk.org>; Tue, 27 Aug 2019 09:09:35 +0200 (CEST)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8B8FC1A001C;\n\tTue, 27 Aug 2019 09:09:35 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 521581A0207;\n\tTue, 27 Aug 2019 09:09:33 +0200 (CEST)", "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n\t[10.232.133.63])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 3EF3840324;\n\tTue, 27 Aug 2019 15:09:30 +0800 (SGT)" ], "From": "Sachin Saxena <sachin.saxena@nxp.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net,\n\tSunil Kumar Kori <sunil.kori@nxp.com>", "Date": "Tue, 27 Aug 2019 12:37:29 +0530", "Message-Id": "<20190827070730.11206-30-sachin.saxena@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190827070730.11206-1-sachin.saxena@nxp.com>", "References": "<20190827070730.11206-1-sachin.saxena@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[dpdk-dev] [PATCH v1 29/30] net/dpaa2: add support for soft parser\n\tin MC", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <sunil.kori@nxp.com>\n\nSigned-off-by: Sunil Kumar Kori <sunil.kori@nxp.com>\nReviewed-by: Sachin Saxena <sachin.saxena@nxp.com>\n---\n drivers/net/dpaa2/mc/dpni.c | 117 ++++++++++++++++++++++++\n drivers/net/dpaa2/mc/fsl_dpni.h | 133 ++++++++++++++++++++++++++++\n drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 43 ++++++++-\n 3 files changed, 292 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c\nindex 362cd476f..b37f9976f 100644\n--- a/drivers/net/dpaa2/mc/dpni.c\n+++ b/drivers/net/dpaa2/mc/dpni.c\n@@ -2484,3 +2484,120 @@ int dpni_get_custom_tpid(struct fsl_mc_io *mc_io, uint32_t cmd_flags,\n \n \treturn err;\n }\n+\n+int dpni_load_sw_sequence(struct fsl_mc_io *mc_io,\n+\t uint32_t cmd_flags,\n+\t uint16_t token,\n+\t\t struct dpni_load_ss_cfg *cfg)\n+{\n+\tstruct dpni_load_sw_sequence *cmd_params;\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_LOAD_SW_SEQUENCE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_load_sw_sequence *)cmd.params;\n+\tcmd_params->dest = cfg->dest;\n+\tcmd_params->ss_offset = cpu_to_le16(cfg->ss_offset);\n+\tcmd_params->ss_size = cpu_to_le16(cfg->ss_size);\n+\tcmd_params->ss_iova = cpu_to_le64(cfg->ss_iova);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+int dpni_enable_sw_sequence(struct fsl_mc_io *mc_io,\n+\t uint32_t cmd_flags,\n+\t uint16_t token,\n+\t\t struct dpni_enable_ss_cfg *cfg)\n+{\n+\tstruct dpni_enable_sw_sequence *cmd_params;\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE_SW_SEQUENCE,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\tcmd_params = (struct dpni_enable_sw_sequence *)cmd.params;\n+\tcmd_params->dest = cfg->dest;\n+\tcmd_params->set_start = cfg->set_start;\n+\tcmd_params->hxs = cpu_to_le16(cfg->hxs);\n+\tcmd_params->ss_offset = cpu_to_le16(cfg->ss_offset);\n+\tcmd_params->param_offset = cfg->param_offset;\n+\tcmd_params->param_size = cfg->param_size;\n+\tcmd_params->param_iova = cpu_to_le64(cfg->param_iova);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+/**\n+ * dpni_get_sw_sequence_layout() - Get the soft sequence layout\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @src:\tSource of the layout (WRIOP Rx or Tx)\n+ * @ss_layout_iova: I/O virtual address of 264 bytes DMA-able memory\n+ *\n+ * warning: After calling this function, call dpni_extract_sw_sequence_layout()\n+ *\t\tto get the layout.\n+ *\n+ * Return:\t'0' on Success; error code otherwise.\n+ */\n+int dpni_get_sw_sequence_layout(struct fsl_mc_io *mc_io,\n+\t uint32_t cmd_flags,\n+\t uint16_t token,\n+\t\t enum dpni_soft_sequence_dest src,\n+\t\t uint64_t ss_layout_iova)\n+{\n+\tstruct dpni_get_sw_sequence_layout *cmd_params;\n+\tstruct mc_command cmd = { 0 };\n+\n+\t/* prepare command */\n+\tcmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT,\n+\t\t\t\t\t cmd_flags,\n+\t\t\t\t\t token);\n+\n+\tcmd_params = (struct dpni_get_sw_sequence_layout *)cmd.params;\n+\tcmd_params->src = src;\n+\tcmd_params->layout_iova = cpu_to_le64(ss_layout_iova);\n+\n+\t/* send command to mc*/\n+\treturn mc_send_command(mc_io, &cmd);\n+}\n+\n+/**\n+ * dpni_extract_sw_sequence_layout() - extract the software sequence layout\n+ * @layout:\t\tsoftware sequence layout\n+ * @sw_sequence_layout_buf:\tZeroed 264 bytes of memory before mapping it\n+ *\t\t\t\tto DMA\n+ *\n+ * This function has to be called after dpni_get_sw_sequence_layout\n+ *\n+ */\n+void dpni_extract_sw_sequence_layout(struct dpni_sw_sequence_layout *layout,\n+\t\t\t const uint8_t *sw_sequence_layout_buf)\n+{\n+\tconst struct dpni_sw_sequence_layout_entry *ext_params;\n+\tint i;\n+\tuint16_t ss_size, ss_offset;\n+\n+\text_params = (const struct dpni_sw_sequence_layout_entry *)\n+\t\t\t\t\t\tsw_sequence_layout_buf;\n+\n+\tfor (i = 0; i < DPNI_SW_SEQUENCE_LAYOUT_SIZE; i++) {\n+\t\tss_offset = le16_to_cpu(ext_params[i].ss_offset);\n+\t\tss_size = le16_to_cpu(ext_params[i].ss_size);\n+\n+\t\tif (ss_offset == 0 && ss_size == 0) {\n+\t\t\tlayout->num_ss = i;\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tlayout->ss[i].ss_offset = ss_offset;\n+\t\tlayout->ss[i].ss_size = ss_size;\n+\t\tlayout->ss[i].param_offset = ext_params[i].param_offset;\n+\t\tlayout->ss[i].param_size = ext_params[i].param_size;\n+\t}\n+}\ndiff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h\nindex 8b1cfbac7..97fde316e 100644\n--- a/drivers/net/dpaa2/mc/fsl_dpni.h\n+++ b/drivers/net/dpaa2/mc/fsl_dpni.h\n@@ -96,6 +96,12 @@ struct fsl_mc_io;\n */\n #define DPNI_OPT_CUSTOM_CG\t\t\t\t0x000200\n \n+\n+/**\n+ * Software sequence maximum layout size\n+ */\n+#define DPNI_SW_SEQUENCE_LAYOUT_SIZE 33\n+\n int dpni_open(struct fsl_mc_io *mc_io,\n \t uint32_t cmd_flags,\n \t int dpni_id,\n@@ -1424,4 +1430,131 @@ struct dpni_custom_tpid_cfg {\n int dpni_get_custom_tpid(struct fsl_mc_io *mc_io, uint32_t cmd_flags,\n \t\tuint16_t token, struct dpni_custom_tpid_cfg *tpid);\n \n+/**\n+ * enum dpni_soft_sequence_dest - Enumeration of WRIOP software sequence\n+ *\t\t\t\tdestinations\n+ * @DPNI_SS_INGRESS: Ingress parser\n+ * @DPNI_SS_EGRESS: Egress parser\n+ */\n+enum dpni_soft_sequence_dest {\n+\tDPNI_SS_INGRESS = 0,\n+\tDPNI_SS_EGRESS = 1,\n+};\n+\n+/**\n+ * struct dpni_load_ss_cfg - Structure for Software Sequence load configuration\n+ * @dest:\tDestination of the Software Sequence: ingress or egress parser\n+ * @ss_size: Size of the Software Sequence\n+ * @ss_offset:\tThe offset where to load the Software Sequence (0x20-0x7FD)\n+ * @ss_iova: I/O virtual address of the Software Sequence\n+ */\n+struct dpni_load_ss_cfg {\n+\tenum dpni_soft_sequence_dest dest;\n+\tuint16_t ss_size;\n+\tuint16_t ss_offset;\n+\tuint64_t ss_iova;\n+};\n+\n+/**\n+ * struct dpni_enable_ss_cfg - Structure for software sequence enable\n+ *\t\t\t\tconfiguration\n+ * @dest:\tDestination of the Software Sequence: ingress or egress parser\n+ * @hxs: HXS to attach the software sequence to\n+ * @set_start: If the Software Sequence or HDR it is attached to is set as\n+ *\t\tparser start\n+ *\t\tIf hxs=DUMMY_LAST_HXS the ss_offset is set directly as parser\n+ *\t\t\tstart else the hdr index code is set as parser start\n+ * @ss_offset: The offset of the Software Sequence to enable or set as parse\n+ *\t\tstart\n+ * @param_size: Size of the software sequence parameters\n+ * @param_offset: Offset in the parameter zone for the software sequence\n+ *\t\t\tparameters\n+ * @param_iova: I/O virtual address of the parameters\n+ */\n+struct dpni_enable_ss_cfg {\n+\tenum dpni_soft_sequence_dest dest;\n+\tuint16_t hxs;\n+\tuint8_t set_start;\n+\tuint16_t ss_offset;\n+\tuint8_t param_size;\n+\tuint8_t param_offset;\n+\tuint64_t param_iova;\n+};\n+\n+/**\n+ * dpni_load_sw_sequence() - Loads a software sequence in parser memory.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @cfg:\tSoftware sequence load configuration\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_load_sw_sequence(struct fsl_mc_io *mc_io,\n+\t uint32_t cmd_flags,\n+\t uint16_t token,\n+\t\t struct dpni_load_ss_cfg *cfg);\n+\n+/**\n+ * dpni_eanble_sw_sequence() - Enables a software sequence in the parser\n+ *\t\t\t\tprofile\n+ * corresponding to the ingress or egress of the DPNI.\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @cfg:\tSoftware sequence enable configuration\n+ * Return:\t'0' on Success; Error code otherwise.\n+ */\n+int dpni_enable_sw_sequence(struct fsl_mc_io *mc_io,\n+\t\t\t uint32_t cmd_flags,\n+\t\t\t uint16_t token,\n+\t\t\t struct dpni_enable_ss_cfg *cfg);\n+\n+/**\n+ * struct dpni_sw_sequence_layout - Structure for software sequence enable\n+ *\t\t\t\tconfiguration\n+ * @num_ss:\tNumber of software sequences returned\n+ * @ss: Array of software sequence entries. The number of valid entries\n+ *\t\t\tmust match 'num_ss' value\n+ */\n+struct dpni_sw_sequence_layout {\n+\tuint8_t num_ss;\n+\tstruct {\n+\t\tuint16_t ss_offset;\n+\t\tuint16_t ss_size;\n+\t\tuint8_t param_offset;\n+\t\tuint8_t param_size;\n+\t} ss[DPNI_SW_SEQUENCE_LAYOUT_SIZE];\n+};\n+\n+/**\n+ * dpni_get_sw_sequence_layout() - Get the soft sequence layout\n+ * @mc_io:\tPointer to MC portal's I/O object\n+ * @cmd_flags:\tCommand flags; one or more of 'MC_CMD_FLAG_'\n+ * @token:\tToken of DPNI object\n+ * @src:\tSource of the layout (WRIOP Rx or Tx)\n+ * @ss_layout_iova: I/O virtual address of 264 bytes DMA-able memory\n+ *\n+ * warning: After calling this function, call dpni_extract_sw_sequence_layout()\n+ *\t\tto get the layout\n+ *\n+ * Return:\t'0' on Success; error code otherwise.\n+ */\n+int dpni_get_sw_sequence_layout(struct fsl_mc_io *mc_io,\n+\t\t\t\tuint32_t cmd_flags,\n+\t\t\t\tuint16_t token,\n+\t\t\t\tenum dpni_soft_sequence_dest src,\n+\t\t\t\tuint64_t ss_layout_iova);\n+\n+/**\n+ * dpni_extract_sw_sequence_layout() - extract the software sequence layout\n+ * @layout:\t\tsoftware sequence layout\n+ * @sw_sequence_layout_buf:\tZeroed 264 bytes of memory before mapping it\n+ *\t\t\t\tto DMA\n+ *\n+ * This function has to be called after dpni_get_sw_sequence_layout\n+ *\n+ */\n+void dpni_extract_sw_sequence_layout(struct dpni_sw_sequence_layout *layout,\n+\t\t\t\t const uint8_t *sw_sequence_layout_buf);\n+\n #endif /* __FSL_DPNI_H */\ndiff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\nindex 5effbb300..dfaccd91c 100644\n--- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\n+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n *\n * Copyright 2013-2016 Freescale Semiconductor Inc.\n- * Copyright 2016-2017 NXP\n+ * Copyright 2016-2019 NXP\n *\n */\n #ifndef _FSL_DPNI_CMD_H\n@@ -97,6 +97,9 @@\n #define DPNI_CMDID_SET_OFFLOAD\t\t\tDPNI_CMD(0x26C)\n #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE\tDPNI_CMD(0x266)\n #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE\tDPNI_CMD(0x26D)\n+#define DPNI_CMDID_LOAD_SW_SEQUENCE\t\tDPNI_CMD(0x270)\n+#define DPNI_CMDID_ENABLE_SW_SEQUENCE\t\tDPNI_CMD(0x271)\n+#define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT\tDPNI_CMD(0x272)\n #define DPNI_CMDID_SET_OPR\t\t\tDPNI_CMD(0x26e)\n #define DPNI_CMDID_GET_OPR\t\t\tDPNI_CMD(0x26f)\n #define DPNI_CMDID_SET_RX_FS_DIST\t\tDPNI_CMD(0x273)\n@@ -798,5 +801,43 @@ struct dpni_cmd_set_rx_hash_dist {\n \tuint64_t\tkey_cfg_iova;\n };\n \n+struct dpni_load_sw_sequence {\n+\tuint8_t dest;\n+\tuint8_t pad0[7];\n+\tuint16_t ss_offset;\n+\tuint16_t pad1;\n+\tuint16_t ss_size;\n+\tuint16_t pad2;\n+\tuint64_t ss_iova;\n+};\n+\n+struct dpni_enable_sw_sequence {\n+\tuint8_t dest;\n+\tuint8_t pad0[7];\n+\tuint16_t ss_offset;\n+\tuint16_t hxs;\n+\tuint8_t set_start;\n+\tuint8_t pad1[3];\n+\tuint8_t param_offset;\n+\tuint8_t pad2[3];\n+\tuint8_t param_size;\n+\tuint8_t pad3[3];\n+\tuint64_t param_iova;\n+};\n+\n+struct dpni_get_sw_sequence_layout {\n+\tuint8_t src;\n+\tuint8_t pad0[7];\n+\tuint64_t layout_iova;\n+};\n+\n+struct dpni_sw_sequence_layout_entry {\n+\tuint16_t ss_offset;\n+\tuint16_t ss_size;\n+\tuint8_t param_offset;\n+\tuint8_t param_size;\n+\tuint16_t pad;\n+};\n+\n #pragma pack(pop)\n #endif /* _FSL_DPNI_CMD_H */\n", "prefixes": [ "v1", "29/30" ] }