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GET /api/patches/57937/?format=api
{ "id": 57937, "url": "http://patches.dpdk.org/api/patches/57937/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-37-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-37-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-37-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:38", "name": "[36/63] net/ice/base: add support for not locking sideband queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f9e508a609ca5879a24846ffafae2efcbef5a91f", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-37-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57937/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57937/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 323101C1C6;\n\tMon, 26 Aug 2019 12:50:42 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 9593A1BFA2\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:31 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:31 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:29 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402334\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tBen Shelton <benjamin.h.shelton@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:38 +0800", "Message-Id": "<20190826105105.19121-37-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 36/63] net/ice/base: add support for not locking\n\tsideband queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "For certain PTP clock adjustments, there is a use case for locking the\nsideband queue at a higher level and performing an atomic series of\noperations while the sideband queue is locked. To accommodate this use\ncase, split ice_sw_send_cmd() into a version that takes the lock and a\nversion that does not.\n\nSigned-off-by: Ben Shelton <benjamin.h.shelton@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_controlq.c | 40 +++++++++++++++++++++++++++++++------\n 1 file changed, 34 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 8070bb9a7..70a50bff4 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -859,7 +859,7 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n }\n \n /**\n- * ice_sq_send_cmd - send command to Control Queue (ATQ)\n+ * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ)\n * @hw: pointer to the HW struct\n * @cq: pointer to the specific Control queue\n * @desc: prefilled descriptor describing the command (non DMA mem)\n@@ -870,10 +870,10 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n * This is the main send command routine for the ATQ. It runs the queue,\n * cleans the queue, etc.\n */\n-enum ice_status\n-ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n-\t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n-\t\tstruct ice_sq_cd *cd)\n+static enum ice_status\n+ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\t struct ice_aq_desc *desc, void *buf, u16 buf_size,\n+\t\t struct ice_sq_cd *cd)\n {\n \tstruct ice_dma_mem *dma_buf = NULL;\n \tstruct ice_aq_desc *desc_on_ring;\n@@ -887,7 +887,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t/* if reset is in progress return a soft error */\n \tif (hw->reset_ongoing)\n \t\treturn ICE_ERR_RESET_ONGOING;\n-\tice_acquire_lock(&cq->sq_lock);\n \n \tcq->sq_last_status = ICE_AQ_RC_OK;\n \n@@ -1040,7 +1039,36 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t}\n \n sq_send_command_error:\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sq_send_cmd - send command to Control Queue (ATQ)\n+ * @hw: pointer to the HW struct\n+ * @cq: pointer to the specific Control queue\n+ * @desc: prefilled descriptor describing the command (non DMA mem)\n+ * @buf: buffer to use for indirect commands (or NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (or 0 for direct commands)\n+ * @cd: pointer to command details structure\n+ *\n+ * This is the main send command routine for the ATQ. It runs the queue,\n+ * cleans the queue, etc.\n+ */\n+enum ice_status\n+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\t/* if reset is in progress return a soft error */\n+\tif (hw->reset_ongoing)\n+\t\treturn ICE_ERR_RESET_ONGOING;\n+\n+\tice_acquire_lock(&cq->sq_lock);\n+\tstatus = ice_sq_send_cmd_nolock(hw, cq, desc, buf, buf_size, cd);\n \tice_release_lock(&cq->sq_lock);\n+\n \treturn status;\n }\n \n", "prefixes": [ "36/63" ] }