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GET /api/patches/57926/?format=api
{ "id": 57926, "url": "http://patches.dpdk.org/api/patches/57926/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-52-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-52-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-52-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:53", "name": "[51/63] net/ice/base: update switch training packets with open ports", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a96ff5719403fc7f4b38da42eaefbffdfbdc1c80", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-52-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57926/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57926/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6A9331C20A;\n\tMon, 26 Aug 2019 12:51:29 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 5EC9F1C116\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:59 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:59 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:57 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402507\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tDan Nowlin <dan.nowlin@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:53 +0800", "Message-Id": "<20190826105105.19121-52-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 51/63] net/ice/base: update switch training\n\tpackets with open ports", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch updates UDP tunneled training packets with an appropriate\nUDP dest port. For the correct profile to be chosen, an open tunnel\nport must be included in the training packet.\n\nAdded GENEVE tunnel labels in the test package in order to test GENEVE\ntunnel rule creation.\n\nSigned-off-by: Dan Nowlin <dan.nowlin@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_switch.c | 57 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 57 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex ef12df5db..c39a77a0f 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -5826,6 +5826,55 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n }\n \n /**\n+ * ice_fill_adv_packet_tun - fill dummy packet with udp tunnel port\n+ * @hw: pointer to the hardware structure\n+ * @tun_type: tunnel type\n+ * @pkt: dummy packet to fill in\n+ * @offsets: offset info for the dummy packet\n+ */\n+static enum ice_status\n+ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,\n+\t\t\tu8 *pkt, const struct ice_dummy_pkt_offsets *offsets)\n+{\n+\tu16 open_port, i;\n+\n+\tswitch (tun_type) {\n+\tcase ICE_SW_TUN_AND_NON_TUN:\n+\tcase ICE_SW_TUN_VXLAN_GPE:\n+\tcase ICE_SW_TUN_VXLAN:\n+\tcase ICE_SW_TUN_UDP:\n+\t\tif (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port))\n+\t\t\treturn ICE_ERR_CFG;\n+\t\tbreak;\n+\n+\tcase ICE_SW_TUN_GENEVE:\n+\t\tif (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port))\n+\t\t\treturn ICE_ERR_CFG;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\t/* Nothing needs to be done for this tunnel type */\n+\t\treturn ICE_SUCCESS;\n+\t}\n+\n+\t/* Find the outer UDP protocol header and insert the port number */\n+\tfor (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {\n+\t\tif (offsets[i].type == ICE_UDP_OF) {\n+\t\t\tstruct ice_l4_hdr *hdr;\n+\t\t\tu16 offset;\n+\n+\t\t\toffset = offsets[i].offset;\n+\t\t\thdr = (struct ice_l4_hdr *)&pkt[offset];\n+\t\t\thdr->dst_port = open_port << 8 | open_port >> 8;\n+\n+\t\t\treturn ICE_SUCCESS;\n+\t\t}\n+\t}\n+\n+\treturn ICE_ERR_CFG;\n+}\n+\n+/**\n * ice_find_adv_rule_entry - Search a rule entry\n * @hw: pointer to the hardware structure\n * @lkups: lookup elements or match criteria for the advanced recipe, one\n@@ -6129,6 +6178,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \tice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len,\n \t\t\t\t pkt_offsets);\n \n+\tif (rinfo->tun_type != ICE_NON_TUN) {\n+\t\tstatus = ice_fill_adv_packet_tun(hw, rinfo->tun_type,\n+\t\t\t\t\t\t s_rule->pdata.lkup_tx_rx.hdr,\n+\t\t\t\t\t\t pkt_offsets);\n+\t\tif (status)\n+\t\t\tgoto err_ice_add_adv_rule;\n+\t}\n+\n \tstatus = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,\n \t\t\t\t rule_buf_sz, 1, ice_aqc_opc_add_sw_rules,\n \t\t\t\t NULL);\n", "prefixes": [ "51/63" ] }