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GET /api/patches/57907/?format=api
{ "id": 57907, "url": "http://patches.dpdk.org/api/patches/57907/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-12-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-12-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-12-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:13", "name": "[11/63] net/ice/base: add capabilities when in safe mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a5998d726b3b64917c57adf766a2085d8439483e", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-12-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57907/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57907/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 634081C033;\n\tMon, 26 Aug 2019 12:48:54 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id C97541BFFC\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:48:45 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:48:45 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:48:43 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402116\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:13 +0800", "Message-Id": "<20190826105105.19121-12-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 11/63] net/ice/base: add capabilities when in\n\tsafe mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The dynamic device personalization (DDP) file download onto the device\ncan fail, and when this happens the driver has to transition to \"safe\nmode\" where only basic functionality is possible.\n\nThe device though doesn't understand safe mode, and so the opcodes to\ndiscover device/function capabilities (0x000A and 0x000B) return all\nthe capabilities of the device, which includes capabilities that the\ndriver cannot support when in safe mode.\n\nThe initialization flows in the driver are based on the capabilities\ninformation (obtained by the driver with the above mentioned opcodes).\nTo reuse the same initialization flows in safe mode, it becomes\nnecessary for the driver to override the currently stored capabilities\ninformation with safe mode capabilities. This is done by a new function\nintroduced in this patch - ice_set_safe_mode_caps.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 64 +++++++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h | 2 ++\n 2 files changed, 66 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex ae7837149..9907d9dae 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2172,6 +2172,70 @@ ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)\n }\n \n /**\n+ * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode\n+ * @hw: pointer to the hardware structure\n+ */\n+void ice_set_safe_mode_caps(struct ice_hw *hw)\n+{\n+\tstruct ice_hw_func_caps *func_caps = &hw->func_caps;\n+\tstruct ice_hw_dev_caps *dev_caps = &hw->dev_caps;\n+\tu32 valid_func, rxq_first_id, txq_first_id;\n+\tu32 msix_vector_first_id, max_mtu;\n+\tu32 num_funcs;\n+\n+\t/* cache some func_caps values that should be restored after memset */\n+\tvalid_func = func_caps->common_cap.valid_functions;\n+\ttxq_first_id = func_caps->common_cap.txq_first_id;\n+\trxq_first_id = func_caps->common_cap.rxq_first_id;\n+\tmsix_vector_first_id = func_caps->common_cap.msix_vector_first_id;\n+\tmax_mtu = func_caps->common_cap.max_mtu;\n+\n+\t/* unset func capabilities */\n+\tmemset(func_caps, 0, sizeof(*func_caps));\n+\n+\t/* restore cached values */\n+\tfunc_caps->common_cap.valid_functions = valid_func;\n+\tfunc_caps->common_cap.txq_first_id = txq_first_id;\n+\tfunc_caps->common_cap.rxq_first_id = rxq_first_id;\n+\tfunc_caps->common_cap.msix_vector_first_id = msix_vector_first_id;\n+\tfunc_caps->common_cap.max_mtu = max_mtu;\n+\n+\t/* one Tx and one Rx queue in safe mode */\n+\tfunc_caps->common_cap.num_rxq = 1;\n+\tfunc_caps->common_cap.num_txq = 1;\n+\n+\t/* two MSIX vectors, one for traffic and one for misc causes */\n+\tfunc_caps->common_cap.num_msix_vectors = 2;\n+\tfunc_caps->guar_num_vsi = 1;\n+\n+\t/* cache some dev_caps values that should be restored after memset */\n+\tvalid_func = dev_caps->common_cap.valid_functions;\n+\ttxq_first_id = dev_caps->common_cap.txq_first_id;\n+\trxq_first_id = dev_caps->common_cap.rxq_first_id;\n+\tmsix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;\n+\tmax_mtu = dev_caps->common_cap.max_mtu;\n+\tnum_funcs = dev_caps->num_funcs;\n+\n+\t/* unset dev capabilities */\n+\tmemset(dev_caps, 0, sizeof(*dev_caps));\n+\n+\t/* restore cached values */\n+\tdev_caps->common_cap.valid_functions = valid_func;\n+\tdev_caps->common_cap.txq_first_id = txq_first_id;\n+\tdev_caps->common_cap.rxq_first_id = rxq_first_id;\n+\tdev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;\n+\tdev_caps->common_cap.max_mtu = max_mtu;\n+\tdev_caps->num_funcs = num_funcs;\n+\n+\t/* one Tx and one Rx queue per function in safe mode */\n+\tdev_caps->common_cap.num_rxq = num_funcs;\n+\tdev_caps->common_cap.num_txq = num_funcs;\n+\n+\t/* two MSIX vectors per function */\n+\tdev_caps->common_cap.num_msix_vectors = 2 * num_funcs;\n+}\n+\n+/**\n * ice_get_caps - get info about the HW\n * @hw: pointer to the hardware structure\n */\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex d865021bf..df1fecec5 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -61,6 +61,8 @@ void ice_clear_pxe_mode(struct ice_hw *hw);\n \n enum ice_status ice_get_caps(struct ice_hw *hw);\n \n+void ice_set_safe_mode_caps(struct ice_hw *hw);\n+\n /* Define a macro that will align a pointer to point to the next memory address\n * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For\n * example, given the variable pointer = 0x1006, then after the following call:\n", "prefixes": [ "11/63" ] }