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GET /api/patches/57858/?format=api
{ "id": 57858, "url": "http://patches.dpdk.org/api/patches/57858/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-19-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1566568031-45991-19-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-19-git-send-email-xavier.huwei@huawei.com", "date": "2019-08-23T13:47:07", "name": "[18/22] net/hns3: add abnormal interrupt process for hns3 PMD driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "4c738e5ccd5b872226f5ca3ad43699660a2ac6fd", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-19-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6114, "url": "http://patches.dpdk.org/api/series/6114/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6114", "date": "2019-08-23T13:46:49", "name": "add hns3 ethernet PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/6114/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57858/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/57858/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 076BF1C0B5;\n\tFri, 23 Aug 2019 15:50:15 +0200 (CEST)", "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 493BB1BFB4\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:40 +0200 (CEST)", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id EAD94D50A27413811F8B;\n\tFri, 23 Aug 2019 21:49:36 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:30 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Fri, 23 Aug 2019 21:47:07 +0800", "Message-ID": "<1566568031-45991-19-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 18/22] net/hns3: add abnormal interrupt process\n\tfor hns3 PMD driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds abnormal interrupt process for hns3 PMD driver,\nthe interrupt reported by NIC hardware.\n\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.c | 135 ++++++++\n drivers/net/hns3/hns3_ethdev.h | 1 +\n drivers/net/hns3/hns3_ethdev_vf.c | 10 +\n drivers/net/hns3/hns3_intr.c | 657 ++++++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_intr.h | 68 ++++\n drivers/net/hns3/hns3_mbx.c | 13 +-\n 6 files changed, 883 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/hns3/hns3_intr.c\n create mode 100644 drivers/net/hns3/hns3_intr.h", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 340f92f..17acfc5 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -36,6 +36,7 @@\n #include \"hns3_ethdev.h\"\n #include \"hns3_logs.h\"\n #include \"hns3_rxtx.h\"\n+#include \"hns3_intr.h\"\n #include \"hns3_regs.h\"\n #include \"hns3_dcb.h\"\n \n@@ -62,10 +63,134 @@\n int hns3_logtype_init;\n int hns3_logtype_driver;\n \n+enum hns3_evt_cause {\n+\tHNS3_VECTOR0_EVENT_RST,\n+\tHNS3_VECTOR0_EVENT_MBX,\n+\tHNS3_VECTOR0_EVENT_ERR,\n+\tHNS3_VECTOR0_EVENT_OTHER,\n+};\n+\n static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,\n \t\t\t\t int on);\n \n+static void\n+hns3_pf_disable_irq0(struct hns3_hw *hw)\n+{\n+\thns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);\n+}\n+\n+static void\n+hns3_pf_enable_irq0(struct hns3_hw *hw)\n+{\n+\thns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);\n+}\n+\n+static enum hns3_evt_cause\n+hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint32_t vector0_int_stats;\n+\tuint32_t cmdq_src_val;\n+\tuint32_t val;\n+\tenum hns3_evt_cause ret;\n+\n+\t/* fetch the events from their corresponding regs */\n+\tvector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n+\tcmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);\n+\n+\t/*\n+\t * Assumption: If by any chance reset and mailbox events are reported\n+\t * together then we will only process reset event and defer the\n+\t * processing of the mailbox events. Since, we would have not cleared\n+\t * RX CMDQ event this time we would receive again another interrupt\n+\t * from H/W just for the mailbox.\n+\t */\n+\tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */\n+\t\tret = HNS3_VECTOR0_EVENT_RST;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Global reset */\n+\tif (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {\n+\t\tret = HNS3_VECTOR0_EVENT_RST;\n+\t\tgoto out;\n+\t}\n+\n+\t/* check for vector0 msix event source */\n+\tif (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {\n+\t\tval = vector0_int_stats;\n+\t\tret = HNS3_VECTOR0_EVENT_ERR;\n+\t\tgoto out;\n+\t}\n+\n+\t/* check for vector0 mailbox(=CMDQ RX) event source */\n+\tif (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {\n+\t\tcmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);\n+\t\tval = cmdq_src_val;\n+\t\tret = HNS3_VECTOR0_EVENT_MBX;\n+\t\tgoto out;\n+\t}\n+\n+\tif (clearval && (vector0_int_stats || cmdq_src_val))\n+\t\thns3_warn(hw, \"surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x\",\n+\t\t\t vector0_int_stats, cmdq_src_val);\n+\tval = vector0_int_stats;\n+\tret = HNS3_VECTOR0_EVENT_OTHER;\n+out:\n+\n+\tif (clearval)\n+\t\t*clearval = val;\n+\treturn ret;\n+}\n+\n+static void\n+hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)\n+{\n+\tif (event_type == HNS3_VECTOR0_EVENT_RST)\n+\t\thns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);\n+\telse if (event_type == HNS3_VECTOR0_EVENT_MBX)\n+\t\thns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);\n+}\n+\n+static void\n+hns3_clear_all_event_cause(struct hns3_hw *hw)\n+{\n+\tuint32_t vector0_int_stats;\n+\tvector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);\n+\n+\tif (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)\n+\t\thns3_warn(hw, \"Probe during IMP reset interrupt\");\n+\n+\tif (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)\n+\t\thns3_warn(hw, \"Probe during Global reset interrupt\");\n+\n+\thns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,\n+\t\t\t BIT(HNS3_VECTOR0_IMPRESET_INT_B) |\n+\t\t\t BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |\n+\t\t\t BIT(HNS3_VECTOR0_CORERESET_INT_B));\n+\thns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);\n+}\n+\n+static void\n+hns3_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tenum hns3_evt_cause event_cause;\n+\tuint32_t clearval = 0;\n+\n+\t/* Disable interrupt */\n+\thns3_pf_disable_irq0(hw);\n+\n+\tevent_cause = hns3_check_event_cause(hns, &clearval);\n+\n+\thns3_clear_event_cause(hw, event_cause, clearval);\n+\t/* Enable interrupt if it is not cause by reset */\n+\thns3_pf_enable_irq0(hw);\n+}\n+\n static int\n hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)\n {\n@@ -3652,8 +3777,17 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)\n \n \thns3_set_default_rss_args(hw);\n \n+\tret = hns3_enable_hw_error_intr(hns, true);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"fail to enable hw error interrupts: %d\",\n+\t\t\t ret);\n+\t\tgoto err_fdir;\n+\t}\n+\n \treturn 0;\n \n+err_fdir:\n+\thns3_fdir_filter_uninit(hns);\n err_hw_init:\n \thns3_uninit_umv_space(hw);\n \n@@ -3685,6 +3819,7 @@ hns3_uninit_pf(struct rte_eth_dev *eth_dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\thns3_enable_hw_error_intr(hns, false);\n \thns3_rss_uninit(hns);\n \thns3_fdir_filter_uninit(hns);\n \thns3_uninit_umv_space(hw);\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex 413db04..83bcb34 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -329,6 +329,7 @@ struct hns3_hw {\n \tstruct hns3_cmq cmq;\n \tstruct hns3_mbx_resp_status mbx_resp; /* mailbox response */\n \tstruct hns3_mbx_arq_ring arq; /* mailbox async rx queue */\n+\tpthread_t irq_thread_id;\n \tstruct hns3_mac mac;\n \tunsigned int secondary_cnt; /* Number of secondary processes init'd. */\n \tuint32_t fw_version;\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 32ba26c..a473a35 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -37,6 +37,7 @@\n #include \"hns3_logs.h\"\n #include \"hns3_rxtx.h\"\n #include \"hns3_regs.h\"\n+#include \"hns3_intr.h\"\n #include \"hns3_dcb.h\"\n \n #define HNS3VF_KEEP_ALIVE_INTERVAL\t2000000 /* us */\n@@ -45,6 +46,12 @@\n #define HNS3VF_RESET_WAIT_MS\t20\n #define HNS3VF_RESET_WAIT_CNT\t2000\n \n+enum hns3vf_evt_cause {\n+\tHNS3VF_VECTOR0_EVENT_RST,\n+\tHNS3VF_VECTOR0_EVENT_MBX,\n+\tHNS3VF_VECTOR0_EVENT_OTHER,\n+};\n+\n static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);\n \n@@ -561,6 +568,9 @@ hns3vf_interrupt_handler(void *param)\n \tenum hns3vf_evt_cause event_cause;\n \tuint32_t clearval;\n \n+\tif (hw->irq_thread_id == 0)\n+\t\thw->irq_thread_id = pthread_self();\n+\n \t/* Disable interrupt */\n \thns3vf_disable_irq0(hw);\n \ndiff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c\nnew file mode 100644\nindex 0000000..b695914\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_intr.c\n@@ -0,0 +1,657 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#include <stdbool.h>\n+#include <sys/time.h>\n+#include <rte_atomic.h>\n+#include <rte_alarm.h>\n+#include <rte_cycles.h>\n+#include <rte_ethdev.h>\n+#include <rte_io.h>\n+#include <rte_malloc.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#include \"hns3_cmd.h\"\n+#include \"hns3_mbx.h\"\n+#include \"hns3_rss.h\"\n+#include \"hns3_fdir.h\"\n+#include \"hns3_ethdev.h\"\n+#include \"hns3_logs.h\"\n+#include \"hns3_intr.h\"\n+#include \"hns3_regs.h\"\n+#include \"hns3_rxtx.h\"\n+\n+/* offset in MSIX bd */\n+#define MAC_ERROR_OFFSET\t1\n+#define PPP_PF_ERROR_OFFSET\t2\n+#define PPU_PF_ERROR_OFFSET\t3\n+#define RCB_ERROR_OFFSET\t5\n+#define RCB_ERROR_STATUS_OFFSET\t2\n+\n+#define HNS3_CHECK_MERGE_CNT(val)\t\t\t\\\n+\tdo {\t\t\t\t\t\t\\\n+\t\tif (val)\t\t\t\t\\\n+\t\t\thw->reset.stats.merge_cnt++;\t\\\n+\t} while (0)\n+\n+const struct hns3_hw_error mac_afifo_tnl_int[] = {\n+\t{ .int_msk = BIT(0), .msg = \"egu_cge_afifo_ecc_1bit_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(1), .msg = \"egu_cge_afifo_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(2), .msg = \"egu_lge_afifo_ecc_1bit_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(3), .msg = \"egu_lge_afifo_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(4), .msg = \"cge_igu_afifo_ecc_1bit_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(5), .msg = \"cge_igu_afifo_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(6), .msg = \"lge_igu_afifo_ecc_1bit_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(7), .msg = \"lge_igu_afifo_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(8), .msg = \"cge_igu_afifo_overflow_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(9), .msg = \"lge_igu_afifo_overflow_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(10), .msg = \"egu_cge_afifo_underrun_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(11), .msg = \"egu_lge_afifo_underrun_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(12), .msg = \"egu_ge_afifo_underrun_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(13), .msg = \"ge_igu_afifo_overflow_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = 0, .msg = NULL,\n+\t .reset_level = HNS3_NONE_RESET}\n+};\n+\n+const struct hns3_hw_error ppu_mpf_abnormal_int_st2[] = {\n+\t{ .int_msk = BIT(13), .msg = \"rpu_rx_pkt_bit32_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(14), .msg = \"rpu_rx_pkt_bit33_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(15), .msg = \"rpu_rx_pkt_bit34_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(16), .msg = \"rpu_rx_pkt_bit35_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(17), .msg = \"rcb_tx_ring_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(18), .msg = \"rcb_rx_ring_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(19), .msg = \"rcb_tx_fbd_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(20), .msg = \"rcb_rx_ebd_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(21), .msg = \"rcb_tso_info_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(22), .msg = \"rcb_tx_int_info_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(23), .msg = \"rcb_rx_int_info_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(24), .msg = \"tpu_tx_pkt_0_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(25), .msg = \"tpu_tx_pkt_1_ecc_mbit_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(26), .msg = \"rd_bus_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(27), .msg = \"wr_bus_err\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(28), .msg = \"reg_search_miss\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(29), .msg = \"rx_q_search_miss\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(30), .msg = \"ooo_ecc_err_detect\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(31), .msg = \"ooo_ecc_err_multpl\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = 0, .msg = NULL,\n+\t .reset_level = HNS3_NONE_RESET}\n+};\n+\n+const struct hns3_hw_error ssu_port_based_pf_int[] = {\n+\t{ .int_msk = BIT(0), .msg = \"roc_pkt_without_key_port\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = BIT(9), .msg = \"low_water_line_err_port\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(10), .msg = \"hi_water_line_err_port\",\n+\t .reset_level = HNS3_GLOBAL_RESET },\n+\t{ .int_msk = 0, .msg = NULL,\n+\t .reset_level = HNS3_NONE_RESET}\n+};\n+\n+const struct hns3_hw_error ppp_pf_abnormal_int[] = {\n+\t{ .int_msk = BIT(0), .msg = \"tx_vlan_tag_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(1), .msg = \"rss_list_tc_unassigned_queue_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = 0, .msg = NULL,\n+\t .reset_level = HNS3_NONE_RESET}\n+};\n+\n+const struct hns3_hw_error ppu_pf_abnormal_int[] = {\n+\t{ .int_msk = BIT(0), .msg = \"over_8bd_no_fe\",\n+\t .reset_level = HNS3_FUNC_RESET },\n+\t{ .int_msk = BIT(1), .msg = \"tso_mss_cmp_min_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(2), .msg = \"tso_mss_cmp_max_err\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = BIT(3), .msg = \"tx_rd_fbd_poison\",\n+\t .reset_level = HNS3_FUNC_RESET },\n+\t{ .int_msk = BIT(4), .msg = \"rx_rd_ebd_poison\",\n+\t .reset_level = HNS3_FUNC_RESET },\n+\t{ .int_msk = BIT(5), .msg = \"buf_wait_timeout\",\n+\t .reset_level = HNS3_NONE_RESET },\n+\t{ .int_msk = 0, .msg = NULL,\n+\t .reset_level = HNS3_NONE_RESET}\n+};\n+\n+static int\n+config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_cmd_desc desc[2];\n+\tint ret;\n+\n+\t/* configure PPP error interrupts */\n+\thns3_cmd_setup_basic_desc(&desc[0], cmd, false);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\thns3_cmd_setup_basic_desc(&desc[1], cmd, false);\n+\n+\tif (cmd == HNS3_PPP_CMD0_INT_CMD) {\n+\t\tif (en) {\n+\t\t\tdesc[0].data[0] =\n+\t\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN);\n+\t\t\tdesc[0].data[1] =\n+\t\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN);\n+\t\t\tdesc[0].data[4] =\n+\t\t\t\trte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN);\n+\t\t}\n+\n+\t\tdesc[1].data[0] =\n+\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK);\n+\t\tdesc[1].data[1] =\n+\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK);\n+\t\tdesc[1].data[2] =\n+\t\t\trte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK);\n+\t} else if (cmd == HNS3_PPP_CMD1_INT_CMD) {\n+\t\tif (en) {\n+\t\t\tdesc[0].data[0] =\n+\t\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN);\n+\t\t\tdesc[0].data[1] =\n+\t\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN);\n+\t\t}\n+\n+\t\tdesc[1].data[0] =\n+\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK);\n+\t\tdesc[1].data[1] =\n+\t\t\trte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK);\n+\t}\n+\n+\tret = hns3_cmd_send(hw, &desc[0], 2);\n+\tif (ret)\n+\t\thns3_err(hw, \"fail to configure PPP error int: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+enable_ppp_err_intr(struct hns3_adapter *hns, bool en)\n+{\n+\tint ret;\n+\n+\tret = config_ppp_err_intr(hns, HNS3_PPP_CMD0_INT_CMD, en);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn config_ppp_err_intr(hns, HNS3_PPP_CMD1_INT_CMD, en);\n+}\n+\n+static int\n+enable_ssu_err_intr(struct hns3_adapter *hns, bool en)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_cmd_desc desc[2];\n+\tint ret;\n+\n+\t/* configure SSU ecc error interrupts */\n+\thns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_ECC_INT_CMD, false);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\thns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_ECC_INT_CMD, false);\n+\tif (en) {\n+\t\tdesc[0].data[0] =\n+\t\t\trte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN);\n+\t\tdesc[0].data[1] =\n+\t\t\trte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN);\n+\t\tdesc[0].data[4] =\n+\t\t\trte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN);\n+\t}\n+\n+\tdesc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK);\n+\tdesc[1].data[1] =\n+\t\trte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);\n+\tdesc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK);\n+\n+\tret = hns3_cmd_send(hw, &desc[0], 2);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to configure SSU ECC error interrupt: %d\",\n+\t\t\t ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* configure SSU common error interrupts */\n+\thns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_COMMON_INT_CMD, false);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\thns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_COMMON_INT_CMD, false);\n+\n+\tif (en) {\n+\t\tdesc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN);\n+\t\tdesc[0].data[1] =\n+\t\t\trte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN);\n+\t\tdesc[0].data[2] =\n+\t\t\trte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN);\n+\t}\n+\n+\tdesc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK |\n+\t\t\t\t\t HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK);\n+\tdesc[1].data[1] =\n+\t\trte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);\n+\n+\tret = hns3_cmd_send(hw, &desc[0], 2);\n+\tif (ret)\n+\t\thns3_err(hw, \"fail to configure SSU COMMON error intr: %d\",\n+\t\t\t ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_cmd_desc desc[2];\n+\tint num = 1;\n+\n+\t/* configure PPU error interrupts */\n+\tswitch (cmd) {\n+\tcase HNS3_PPU_MPF_ECC_INT_CMD:\n+\t\thns3_cmd_setup_basic_desc(&desc[0], cmd, false);\n+\t\tdesc[0].flag |= HNS3_CMD_FLAG_NEXT;\n+\t\thns3_cmd_setup_basic_desc(&desc[1], cmd, false);\n+\t\tif (en) {\n+\t\t\tdesc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN;\n+\t\t\tdesc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN;\n+\t\t\tdesc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN;\n+\t\t\tdesc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN;\n+\t\t}\n+\n+\t\tdesc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK;\n+\t\tdesc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK;\n+\t\tdesc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK;\n+\t\tdesc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK;\n+\t\tnum = 2;\n+\t\tbreak;\n+\tcase HNS3_PPU_MPF_OTHER_INT_CMD:\n+\t\thns3_cmd_setup_basic_desc(&desc[0], cmd, false);\n+\t\tif (en)\n+\t\t\tdesc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2;\n+\n+\t\tdesc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK;\n+\t\tbreak;\n+\tcase HNS3_PPU_PF_OTHER_INT_CMD:\n+\t\thns3_cmd_setup_basic_desc(&desc[0], cmd, false);\n+\t\tif (en)\n+\t\t\tdesc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN;\n+\n+\t\tdesc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK;\n+\t\tbreak;\n+\tdefault:\n+\t\thns3_err(hw,\n+\t\t\t \"Invalid cmd(%u) to configure PPU error interrupts.\",\n+\t\t\t cmd);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn hns3_cmd_send(hw, &desc[0], num);\n+}\n+\n+static int\n+enable_ppu_err_intr(struct hns3_adapter *hns, bool en)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_ECC_INT_CMD, en);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to configure PPU MPF ECC error intr: %d\",\n+\t\t\t ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_OTHER_INT_CMD, en);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to configure PPU MPF other intr: %d\",\n+\t\t\t ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = config_ppu_err_intrs(hns, HNS3_PPU_PF_OTHER_INT_CMD, en);\n+\tif (ret)\n+\t\thns3_err(hw, \"fail to configure PPU PF error interrupts: %d\",\n+\t\t\t ret);\n+\treturn ret;\n+}\n+\n+static int\n+enable_mac_err_intr(struct hns3_adapter *hns, bool en)\n+{\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\t/* configure MAC common error interrupts */\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_MAC_COMMON_INT_EN, false);\n+\tif (en)\n+\t\tdesc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN);\n+\n+\tdesc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK);\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"fail to configure MAC COMMON error intr: %d\",\n+\t\t\t ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct hns3_hw_blk hw_blk[] = {\n+\t{\n+\t\t.name = \"PPP\",\n+\t\t.enable_err_intr = enable_ppp_err_intr,\n+\t},\n+\t{\n+\t\t.name = \"SSU\",\n+\t\t.enable_err_intr = enable_ssu_err_intr,\n+\t},\n+\t{\n+\t\t.name = \"PPU\",\n+\t\t.enable_err_intr = enable_ppu_err_intr,\n+\t},\n+\t{\n+\t\t.name = \"MAC\",\n+\t\t.enable_err_intr = enable_mac_err_intr,\n+\t},\n+\t{\n+\t\t.name = NULL,\n+\t\t.enable_err_intr = NULL,\n+\t}\n+};\n+\n+int\n+hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en)\n+{\n+\tconst struct hns3_hw_blk *module = hw_blk;\n+\tint ret = 0;\n+\n+\twhile (module->enable_err_intr) {\n+\t\tret = module->enable_err_intr(hns, en);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tmodule++;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static enum hns3_reset_level\n+hns3_find_highest_level(struct hns3_adapter *hns, const char *reg,\n+\t\t\tconst struct hns3_hw_error *err, uint32_t err_sts)\n+{\n+\tenum hns3_reset_level reset_level = HNS3_FUNC_RESET;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tbool need_reset = false;\n+\n+\twhile (err->msg) {\n+\t\tif (err->int_msk & err_sts) {\n+\t\t\thns3_warn(hw, \"%s %s found [error status=0x%x]\",\n+\t\t\t\t reg, err->msg, err_sts);\n+\t\t\tif (err->reset_level != HNS3_NONE_RESET &&\n+\t\t\t err->reset_level >= reset_level) {\n+\t\t\t\treset_level = err->reset_level;\n+\t\t\t\tneed_reset = true;\n+\t\t\t}\n+\t\t}\n+\t\terr++;\n+\t}\n+\tif (need_reset)\n+\t\treturn reset_level;\n+\telse\n+\t\treturn HNS3_NONE_RESET;\n+}\n+\n+static int\n+query_num_bds_in_msix(struct hns3_hw *hw, struct hns3_cmd_desc *desc_bd)\n+{\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(desc_bd, HNS3_QUERY_MSIX_INT_STS_BD_NUM,\n+\t\t\t\t true);\n+\tret = hns3_cmd_send(hw, desc_bd, 1);\n+\tif (ret)\n+\t\thns3_err(hw, \"query num bds in msix failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+query_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,\n+\t\t uint32_t mpf_bd_num)\n+{\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT,\n+\t\t\t\t true);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\n+\tret = hns3_cmd_send(hw, &desc[0], mpf_bd_num);\n+\tif (ret)\n+\t\thns3_err(hw, \"query all mpf msix err failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+clear_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,\n+\t\t uint32_t mpf_bd_num)\n+{\n+\tint ret;\n+\n+\thns3_cmd_reuse_desc(desc, false);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\n+\tret = hns3_cmd_send(hw, desc, mpf_bd_num);\n+\tif (ret)\n+\t\thns3_err(hw, \"clear all mpf msix err failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+query_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,\n+\t\t uint32_t pf_bd_num)\n+{\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT, true);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\n+\tret = hns3_cmd_send(hw, desc, pf_bd_num);\n+\tif (ret)\n+\t\thns3_err(hw, \"query all pf msix int cmd failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int\n+clear_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc,\n+\t\t uint32_t pf_bd_num)\n+{\n+\tint ret;\n+\n+\thns3_cmd_reuse_desc(desc, false);\n+\tdesc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);\n+\n+\tret = hns3_cmd_send(hw, desc, pf_bd_num);\n+\tif (ret)\n+\t\thns3_err(hw, \"clear all pf msix err failed: %d\", ret);\n+\n+\treturn ret;\n+}\n+\n+void\n+hns3_intr_unregister(const struct rte_intr_handle *hdl,\n+\t\t rte_intr_callback_fn cb_fn, void *cb_arg)\n+{\n+\tint retry_cnt = 0;\n+\tint ret;\n+\n+\tdo {\n+\t\tret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg);\n+\t\tif (ret >= 0) {\n+\t\t\tbreak;\n+\t\t} else if (ret != -EAGAIN) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to unregister intr: %d\", ret);\n+\t\t\tbreak;\n+\t\t}\n+\t\trte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS);\n+\t} while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT);\n+}\n+\n+void\n+hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)\n+{\n+\tuint32_t mpf_bd_num, pf_bd_num, bd_num;\n+\tenum hns3_reset_level req_level;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tstruct hns3_cmd_desc desc_bd;\n+\tstruct hns3_cmd_desc *desc;\n+\tuint32_t *desc_data;\n+\tuint32_t status;\n+\tint ret;\n+\n+\t/* query the number of bds for the MSIx int status */\n+\tret = query_num_bds_in_msix(hw, &desc_bd);\n+\tif (ret) {\n+\t\thns3_err(hw, \"fail to query msix int status bd num: %d\", ret);\n+\t\treturn;\n+\t}\n+\n+\tmpf_bd_num = rte_le_to_cpu_32(desc_bd.data[0]);\n+\tpf_bd_num = rte_le_to_cpu_32(desc_bd.data[1]);\n+\tbd_num = max_t(uint32_t, mpf_bd_num, pf_bd_num);\n+\tif (bd_num < RCB_ERROR_OFFSET) {\n+\t\thns3_err(hw, \"bd_num is less than RCB_ERROR_OFFSET: %u\",\n+\t\t\t bd_num);\n+\t\treturn;\n+\t}\n+\n+\tdesc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0);\n+\tif (desc == NULL) {\n+\t\thns3_err(hw, \"fail to zmalloc desc\");\n+\t\treturn;\n+\t}\n+\n+\t/* query all main PF MSIx errors */\n+\tret = query_all_mpf_msix_err(hw, &desc[0], mpf_bd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"query all mpf msix int cmd failed: %d\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\t/* log MAC errors */\n+\tdesc_data = (uint32_t *)&desc[MAC_ERROR_OFFSET];\n+\tstatus = rte_le_to_cpu_32(*desc_data);\n+\tif (status) {\n+\t\treq_level = hns3_find_highest_level(hns, \"MAC_AFIFO_TNL_INT_R\",\n+\t\t\t\t\t\t mac_afifo_tnl_int,\n+\t\t\t\t\t\t status);\n+\t\thns3_atomic_set_bit(req_level, levels);\n+\t\tpf->abn_int_stats.mac_afifo_tnl_intr_cnt++;\n+\t}\n+\n+\t/* log PPU(RCB) errors */\n+\tdesc_data = (uint32_t *)&desc[RCB_ERROR_OFFSET];\n+\tstatus = rte_le_to_cpu_32(*(desc_data + RCB_ERROR_STATUS_OFFSET)) &\n+\t\t\tHNS3_PPU_MPF_INT_ST2_MSIX_MASK;\n+\tif (status) {\n+\t\treq_level = hns3_find_highest_level(hns,\n+\t\t\t\t\t\t \"PPU_MPF_ABNORMAL_INT_ST2\",\n+\t\t\t\t\t\t ppu_mpf_abnormal_int_st2,\n+\t\t\t\t\t\t status);\n+\t\thns3_atomic_set_bit(req_level, levels);\n+\t\tpf->abn_int_stats.ppu_mpf_abnormal_intr_st2_cnt++;\n+\t}\n+\n+\t/* clear all main PF MSIx errors */\n+\tret = clear_all_mpf_msix_err(hw, desc, mpf_bd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"clear all mpf msix int cmd failed: %d\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\t/* query all PF MSIx errors */\n+\tmemset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc));\n+\tret = query_all_pf_msix_err(hw, &desc[0], pf_bd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"query all pf msix int cmd failed (%d)\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\t/* log SSU PF errors */\n+\tstatus = rte_le_to_cpu_32(desc[0].data[0]) &\n+\t\t HNS3_SSU_PORT_INT_MSIX_MASK;\n+\tif (status) {\n+\t\treq_level = hns3_find_highest_level(hns,\n+\t\t\t\t\t\t \"SSU_PORT_BASED_ERR_INT\",\n+\t\t\t\t\t\t ssu_port_based_pf_int,\n+\t\t\t\t\t\t status);\n+\t\thns3_atomic_set_bit(req_level, levels);\n+\t\tpf->abn_int_stats.ssu_port_based_pf_intr_cnt++;\n+\t}\n+\n+\t/* log PPP PF errors */\n+\tdesc_data = (uint32_t *)&desc[PPP_PF_ERROR_OFFSET];\n+\tstatus = rte_le_to_cpu_32(*desc_data);\n+\tif (status) {\n+\t\treq_level = hns3_find_highest_level(hns,\n+\t\t\t\t\t\t \"PPP_PF_ABNORMAL_INT_ST0\",\n+\t\t\t\t\t\t ppp_pf_abnormal_int,\n+\t\t\t\t\t\t status);\n+\t\thns3_atomic_set_bit(req_level, levels);\n+\t\tpf->abn_int_stats.ppp_pf_abnormal_intr_cnt++;\n+\t}\n+\n+\t/* log PPU(RCB) PF errors */\n+\tdesc_data = (uint32_t *)&desc[PPU_PF_ERROR_OFFSET];\n+\tstatus = rte_le_to_cpu_32(*desc_data) & HNS3_PPU_PF_INT_MSIX_MASK;\n+\tif (status) {\n+\t\treq_level = hns3_find_highest_level(hns,\n+\t\t\t\t\t\t \"PPU_PF_ABNORMAL_INT_ST\",\n+\t\t\t\t\t\t ppu_pf_abnormal_int,\n+\t\t\t\t\t\t status);\n+\t\thns3_atomic_set_bit(req_level, levels);\n+\t\tpf->abn_int_stats.ppu_pf_abnormal_intr_cnt++;\n+\t}\n+\n+\t/* clear all PF MSIx errors */\n+\tret = clear_all_pf_msix_err(hw, desc, pf_bd_num);\n+\tif (ret)\n+\t\thns3_err(hw, \"clear all pf msix int cmd failed: %d\", ret);\n+out:\n+\trte_free(desc);\n+}\ndiff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h\nnew file mode 100644\nindex 0000000..b57b4ac\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_intr.h\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#ifndef _HNS3_INTR_H_\n+#define _HNS3_INTR_H_\n+\n+#define HNS3_PPP_MPF_ECC_ERR_INT0_EN\t\t0xFFFFFFFF\n+#define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK\t0xFFFFFFFF\n+#define HNS3_PPP_MPF_ECC_ERR_INT1_EN\t\t0xFFFFFFFF\n+#define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK\t0xFFFFFFFF\n+#define HNS3_PPP_PF_ERR_INT_EN\t\t\t0x0003\n+#define HNS3_PPP_PF_ERR_INT_EN_MASK\t\t0x0003\n+#define HNS3_PPP_MPF_ECC_ERR_INT2_EN\t\t0x003F\n+#define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK\t0x003F\n+#define HNS3_PPP_MPF_ECC_ERR_INT3_EN\t\t0x003F\n+#define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK\t0x003F\n+\n+#define HNS3_MAC_COMMON_ERR_INT_EN\t\t0x107FF\n+#define HNS3_MAC_COMMON_ERR_INT_EN_MASK\t\t0x107FF\n+\n+#define HNS3_PPU_MPF_ABNORMAL_INT0_EN\t\tGENMASK(31, 0)\n+#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK\tGENMASK(31, 0)\n+#define HNS3_PPU_MPF_ABNORMAL_INT1_EN\t\tGENMASK(31, 0)\n+#define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK\tGENMASK(31, 0)\n+#define HNS3_PPU_MPF_ABNORMAL_INT2_EN\t\t0x3FFF3FFF\n+#define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK\t0x3FFF3FFF\n+#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2\t\t0xB\n+#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK\t0xB\n+#define HNS3_PPU_MPF_ABNORMAL_INT3_EN\t\tGENMASK(7, 0)\n+#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK\tGENMASK(23, 16)\n+#define HNS3_PPU_PF_ABNORMAL_INT_EN\t\tGENMASK(5, 0)\n+#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK\tGENMASK(5, 0)\n+#define HNS3_PPU_PF_INT_MSIX_MASK\t\t0x27\n+#define HNS3_PPU_MPF_INT_ST2_MSIX_MASK\t\tGENMASK(29, 28)\n+\n+#define HNS3_SSU_1BIT_ECC_ERR_INT_EN\t\tGENMASK(31, 0)\n+#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK\tGENMASK(31, 0)\n+#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN\tGENMASK(31, 0)\n+#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK\tGENMASK(31, 0)\n+#define HNS3_SSU_BIT32_ECC_ERR_INT_EN\t\t0x0101\n+#define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK\t0x0101\n+#define HNS3_SSU_COMMON_INT_EN\t\t\tGENMASK(9, 0)\n+#define HNS3_SSU_COMMON_INT_EN_MASK\t\tGENMASK(9, 0)\n+#define HNS3_SSU_PORT_BASED_ERR_INT_EN\t\t0x0BFF\n+#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK\t0x0BFF0000\n+#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN\tGENMASK(23, 0)\n+#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK\tGENMASK(23, 0)\n+#define HNS3_SSU_COMMON_ERR_INT_MASK\t\tGENMASK(9, 0)\n+#define HNS3_SSU_PORT_INT_MSIX_MASK\t\t0x7BFF\n+\n+struct hns3_hw_blk {\n+\tconst char *name;\n+\tint (*enable_err_intr)(struct hns3_adapter *hns, bool en);\n+};\n+\n+struct hns3_hw_error {\n+\tuint32_t int_msk;\n+\tconst char *msg;\n+\tenum hns3_reset_level reset_level;\n+};\n+\n+int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state);\n+void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);\n+void hns3_intr_unregister(const struct rte_intr_handle *hdl,\n+\t\t\t rte_intr_callback_fn cb_fn, void *cb_arg);\n+\n+#endif /* _HNS3_INTR_H_ */\ndiff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c\nindex 485d810..de16cbe 100644\n--- a/drivers/net/hns3/hns3_mbx.c\n+++ b/drivers/net/hns3/hns3_mbx.c\n@@ -31,6 +31,7 @@\n #include \"hns3_ethdev.h\"\n #include \"hns3_regs.h\"\n #include \"hns3_logs.h\"\n+#include \"hns3_intr.h\"\n \n #define HNS3_REG_MSG_DATA_OFFSET\t4\n #define HNS3_CMD_CODE_OFFSET\t\t2\n@@ -105,7 +106,17 @@ hns3_get_mbx_resp(struct hns3_hw *hw, uint16_t code0, uint16_t code1,\n \tend = now + HNS3_MAX_RETRY_MS;\n \twhile ((hw->mbx_resp.head != hw->mbx_resp.tail + hw->mbx_resp.lost) &&\n \t (now < end)) {\n-\t\trte_delay_ms(HNS3_POLL_RESPONE_MS);\n+\t\t/*\n+\t\t * The mbox response is running on the interrupt thread.\n+\t\t * Sending mbox in the interrupt thread cannot wait for the\n+\t\t * response, so polling the mbox response on the irq thread.\n+\t\t */\n+\t\tif (pthread_equal(hw->irq_thread_id, pthread_self())) {\n+\t\t\tin_irq = true;\n+\t\t\thns3_poll_all_sync_msg();\n+\t\t} else {\n+\t\t\trte_delay_ms(HNS3_POLL_RESPONE_MS);\n+\t\t}\n \t\tnow = get_timeofday_ms();\n \t}\n \thw->mbx_resp.req_msg_data = 0;\n", "prefixes": [ "18/22" ] }