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GET /api/patches/57852/?format=api
{ "id": 57852, "url": "http://patches.dpdk.org/api/patches/57852/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-18-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1566568031-45991-18-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-18-git-send-email-xavier.huwei@huawei.com", "date": "2019-08-23T13:47:06", "name": "[17/22] net/hns3: add dump register ops for hns3 PMD driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c57faad16f83397cee14a5e22c66eefe8cf5ce32", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-18-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6114, "url": "http://patches.dpdk.org/api/series/6114/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6114", "date": "2019-08-23T13:46:49", "name": "add hns3 ethernet PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/6114/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57852/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/57852/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AA2B21C013;\n\tFri, 23 Aug 2019 15:50:01 +0200 (CEST)", "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id E7DD41BFC8\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:38 +0200 (CEST)", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id CB99DC816157EA3D6A99;\n\tFri, 23 Aug 2019 21:49:36 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:30 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Fri, 23 Aug 2019 21:47:06 +0800", "Message-ID": "<1566568031-45991-18-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 17/22] net/hns3: add dump register ops for hns3\n\tPMD driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds get_reg related function codes for hns3 PMD driver.\n\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.c | 1 +\n drivers/net/hns3/hns3_ethdev_vf.c | 1 +\n drivers/net/hns3/hns3_regs.c | 377 ++++++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_regs.h | 1 +\n 4 files changed, 380 insertions(+)\n create mode 100644 drivers/net/hns3/hns3_regs.c", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 4a57474..340f92f 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -4030,6 +4030,7 @@ static const struct eth_dev_ops hns3_eth_dev_ops = {\n \t.vlan_tpid_set = hns3_vlan_tpid_set,\n \t.vlan_offload_set = hns3_vlan_offload_set,\n \t.vlan_pvid_set = hns3_vlan_pvid_set,\n+\t.get_reg = hns3_get_regs,\n \t.get_dcb_info = hns3_get_dcb_info,\n \t.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,\n };\ndiff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 7e73845..32ba26c 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -1161,6 +1161,7 @@ static const struct eth_dev_ops hns3vf_eth_dev_ops = {\n \t.filter_ctrl = hns3_dev_filter_ctrl,\n \t.vlan_filter_set = hns3vf_vlan_filter_set,\n \t.vlan_offload_set = hns3vf_vlan_offload_set,\n+\t.get_reg = hns3_get_regs,\n \t.dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,\n };\n \ndiff --git a/drivers/net/hns3/hns3_regs.c b/drivers/net/hns3/hns3_regs.c\nnew file mode 100644\nindex 0000000..91cd7c1\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_regs.c\n@@ -0,0 +1,377 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#include <errno.h>\n+#include <stdarg.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <sys/queue.h>\n+#include <inttypes.h>\n+#include <unistd.h>\n+#include <rte_alarm.h>\n+#include <rte_atomic.h>\n+#include <rte_bus_pci.h>\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_debug.h>\n+#include <rte_dev.h>\n+#include <rte_eal.h>\n+#include <rte_ether.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_ethdev_pci.h>\n+#include <rte_io.h>\n+#include <rte_log.h>\n+#include <rte_pci.h>\n+\n+#include \"hns3_cmd.h\"\n+#include \"hns3_mbx.h\"\n+#include \"hns3_rss.h\"\n+#include \"hns3_fdir.h\"\n+#include \"hns3_ethdev.h\"\n+#include \"hns3_logs.h\"\n+#include \"hns3_rxtx.h\"\n+#include \"hns3_regs.h\"\n+\n+#define MAX_SEPARATE_NUM\t4\n+#define SEPARATOR_VALUE\t\t0xFFFFFFFF\n+#define REG_NUM_PER_LINE\t4\n+#define REG_LEN_PER_LINE\t(REG_NUM_PER_LINE * sizeof(uint32_t))\n+\n+static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,\n+\t\t\t\t\t HNS3_CMDQ_TX_ADDR_H_REG,\n+\t\t\t\t\t HNS3_CMDQ_TX_DEPTH_REG,\n+\t\t\t\t\t HNS3_CMDQ_TX_TAIL_REG,\n+\t\t\t\t\t HNS3_CMDQ_TX_HEAD_REG,\n+\t\t\t\t\t HNS3_CMDQ_RX_ADDR_L_REG,\n+\t\t\t\t\t HNS3_CMDQ_RX_ADDR_H_REG,\n+\t\t\t\t\t HNS3_CMDQ_RX_DEPTH_REG,\n+\t\t\t\t\t HNS3_CMDQ_RX_TAIL_REG,\n+\t\t\t\t\t HNS3_CMDQ_RX_HEAD_REG,\n+\t\t\t\t\t HNS3_VECTOR0_CMDQ_SRC_REG,\n+\t\t\t\t\t HNS3_CMDQ_INTR_STS_REG,\n+\t\t\t\t\t HNS3_CMDQ_INTR_EN_REG,\n+\t\t\t\t\t HNS3_CMDQ_INTR_GEN_REG};\n+\n+static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,\n+\t\t\t\t\t HNS3_VECTOR0_OTER_EN_REG,\n+\t\t\t\t\t HNS3_MISC_RESET_STS_REG,\n+\t\t\t\t\t HNS3_VECTOR0_OTHER_INT_STS_REG,\n+\t\t\t\t\t HNS3_GLOBAL_RESET_REG,\n+\t\t\t\t\t HNS3_FUN_RST_ING,\n+\t\t\t\t\t HNS3_GRO_EN_REG};\n+\n+static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,\n+\t\t\t\t\t HNS3_FUN_RST_ING,\n+\t\t\t\t\t HNS3_GRO_EN_REG};\n+\n+static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,\n+\t\t\t\t\t HNS3_RING_RX_BASEADDR_H_REG,\n+\t\t\t\t\t HNS3_RING_RX_BD_NUM_REG,\n+\t\t\t\t\t HNS3_RING_RX_BD_LEN_REG,\n+\t\t\t\t\t HNS3_RING_RX_MERGE_EN_REG,\n+\t\t\t\t\t HNS3_RING_RX_TAIL_REG,\n+\t\t\t\t\t HNS3_RING_RX_HEAD_REG,\n+\t\t\t\t\t HNS3_RING_RX_FBDNUM_REG,\n+\t\t\t\t\t HNS3_RING_RX_OFFSET_REG,\n+\t\t\t\t\t HNS3_RING_RX_FBD_OFFSET_REG,\n+\t\t\t\t\t HNS3_RING_RX_STASH_REG,\n+\t\t\t\t\t HNS3_RING_RX_BD_ERR_REG,\n+\t\t\t\t\t HNS3_RING_TX_BASEADDR_L_REG,\n+\t\t\t\t\t HNS3_RING_TX_BASEADDR_H_REG,\n+\t\t\t\t\t HNS3_RING_TX_BD_NUM_REG,\n+\t\t\t\t\t HNS3_RING_TX_PRIORITY_REG,\n+\t\t\t\t\t HNS3_RING_TX_TC_REG,\n+\t\t\t\t\t HNS3_RING_TX_MERGE_EN_REG,\n+\t\t\t\t\t HNS3_RING_TX_TAIL_REG,\n+\t\t\t\t\t HNS3_RING_TX_HEAD_REG,\n+\t\t\t\t\t HNS3_RING_TX_FBDNUM_REG,\n+\t\t\t\t\t HNS3_RING_TX_OFFSET_REG,\n+\t\t\t\t\t HNS3_RING_TX_EBD_NUM_REG,\n+\t\t\t\t\t HNS3_RING_TX_EBD_OFFSET_REG,\n+\t\t\t\t\t HNS3_RING_TX_BD_ERR_REG,\n+\t\t\t\t\t HNS3_RING_EN_REG};\n+\n+static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,\n+\t\t\t\t\t HNS3_TQP_INTR_GL0_REG,\n+\t\t\t\t\t HNS3_TQP_INTR_GL1_REG,\n+\t\t\t\t\t HNS3_TQP_INTR_GL2_REG,\n+\t\t\t\t\t HNS3_TQP_INTR_RL_REG};\n+\n+static int\n+hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,\n+\t\t uint32_t *regs_num_64_bit)\n+{\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Query register number cmd failed, ret = %d\",\n+\t\t\t ret);\n+\t\treturn ret;\n+\t}\n+\n+\t*regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);\n+\t*regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\tint cmdq_lines, common_lines, ring_lines, tqp_intr_lines;\n+\tuint32_t regs_num_32_bit, regs_num_64_bit;\n+\tint ret;\n+\n+\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Get register number failed, ret = %d.\",\n+\t\t\t ret);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tcmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;\n+\tif (hns->is_vf)\n+\t\tcommon_lines =\n+\t\t\tsizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;\n+\telse\n+\t\tcommon_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;\n+\tring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;\n+\ttqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;\n+\n+\t*length = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +\n+\t\t tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE +\n+\t\t regs_num_32_bit * sizeof(uint32_t) +\n+\t\t regs_num_64_bit * sizeof(uint64_t);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n+{\n+#define HNS3_32_BIT_REG_RTN_DATANUM 8\n+#define HNS3_32_BIT_DESC_NODATA_LEN 2\n+\tstruct hns3_cmd_desc *desc;\n+\tuint32_t *reg_val = data;\n+\tuint32_t *desc_data;\n+\tint cmd_num;\n+\tint i, k, n;\n+\tint ret;\n+\n+\tif (regs_num == 0)\n+\t\treturn 0;\n+\n+\tcmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,\n+\t\t\t HNS3_32_BIT_REG_RTN_DATANUM);\n+\tdesc = rte_zmalloc(\"hns3-32bit-regs\",\n+\t\t\t sizeof(struct hns3_cmd_desc) * cmd_num, 0);\n+\tif (desc == NULL) {\n+\t\thns3_err(hw, \"Failed to allocate %ld bytes needed to \"\n+\t\t\t \"store 32bit regs\",\n+\t\t\t sizeof(struct hns3_cmd_desc) * cmd_num);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\thns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);\n+\tret = hns3_cmd_send(hw, desc, cmd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Query 32 bit register cmd failed, ret = %d\",\n+\t\t\t ret);\n+\t\trte_free(desc);\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < cmd_num; i++) {\n+\t\tif (i == 0) {\n+\t\t\tdesc_data = &desc[i].data[0];\n+\t\t\tn = HNS3_32_BIT_REG_RTN_DATANUM -\n+\t\t\t HNS3_32_BIT_DESC_NODATA_LEN;\n+\t\t} else {\n+\t\t\tdesc_data = (uint32_t *)(&desc[i]);\n+\t\t\tn = HNS3_32_BIT_REG_RTN_DATANUM;\n+\t\t}\n+\t\tfor (k = 0; k < n; k++) {\n+\t\t\t*reg_val++ = rte_le_to_cpu_32(*desc_data++);\n+\n+\t\t\tregs_num--;\n+\t\t\tif (regs_num == 0)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\trte_free(desc);\n+\treturn 0;\n+}\n+\n+static int\n+hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)\n+{\n+#define HNS3_64_BIT_REG_RTN_DATANUM 4\n+#define HNS3_64_BIT_DESC_NODATA_LEN 1\n+\tstruct hns3_cmd_desc *desc;\n+\tuint64_t *reg_val = data;\n+\tuint64_t *desc_data;\n+\tint cmd_num;\n+\tint i, k, n;\n+\tint ret;\n+\n+\tif (regs_num == 0)\n+\t\treturn 0;\n+\n+\tcmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,\n+\t\t\t HNS3_64_BIT_REG_RTN_DATANUM);\n+\tdesc = rte_zmalloc(\"hns3-64bit-regs\",\n+\t\t\t sizeof(struct hns3_cmd_desc) * cmd_num, 0);\n+\tif (desc == NULL) {\n+\t\thns3_err(hw, \"Failed to allocate %ld bytes needed to \"\n+\t\t\t \"store 64bit regs\",\n+\t\t\t sizeof(struct hns3_cmd_desc) * cmd_num);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\thns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);\n+\tret = hns3_cmd_send(hw, desc, cmd_num);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Query 64 bit register cmd failed, ret = %d\",\n+\t\t\t ret);\n+\t\trte_free(desc);\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < cmd_num; i++) {\n+\t\tif (i == 0) {\n+\t\t\tdesc_data = (uint64_t *)(&desc[i].data[0]);\n+\t\t\tn = HNS3_64_BIT_REG_RTN_DATANUM -\n+\t\t\t HNS3_64_BIT_DESC_NODATA_LEN;\n+\t\t} else {\n+\t\t\tdesc_data = (uint64_t *)(&desc[i]);\n+\t\t\tn = HNS3_64_BIT_REG_RTN_DATANUM;\n+\t\t}\n+\t\tfor (k = 0; k < n; k++) {\n+\t\t\t*reg_val++ = rte_le_to_cpu_64(*desc_data++);\n+\n+\t\t\tregs_num--;\n+\t\t\tif (!regs_num)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\trte_free(desc);\n+\treturn 0;\n+}\n+\n+static void\n+hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\tuint32_t reg_offset;\n+\tint separator_num;\n+\tint reg_um;\n+\tint i, j;\n+\n+\t/* fetching per-PF registers values from PF PCIe register space */\n+\treg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);\n+\tseparator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;\n+\tfor (i = 0; i < reg_um; i++)\n+\t\t*data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);\n+\tfor (i = 0; i < separator_num; i++)\n+\t\t*data++ = SEPARATOR_VALUE;\n+\n+\tif (hns->is_vf)\n+\t\treg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);\n+\telse\n+\t\treg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);\n+\tseparator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;\n+\tfor (i = 0; i < reg_um; i++)\n+\t\tif (hns->is_vf)\n+\t\t\t*data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);\n+\t\telse\n+\t\t\t*data++ = hns3_read_dev(hw, common_reg_addrs[i]);\n+\tfor (i = 0; i < separator_num; i++)\n+\t\t*data++ = SEPARATOR_VALUE;\n+\n+\treg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);\n+\tseparator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;\n+\tfor (j = 0; j < hw->tqps_num; j++) {\n+\t\treg_offset = HNS3_TQP_REG_OFFSET + HNS3_TQP_REG_SIZE * j;\n+\t\tfor (i = 0; i < reg_um; i++)\n+\t\t\t*data++ = hns3_read_dev(hw,\n+\t\t\t\t\t\tring_reg_addrs[i] + reg_offset);\n+\t\tfor (i = 0; i < separator_num; i++)\n+\t\t\t*data++ = SEPARATOR_VALUE;\n+\t}\n+\n+\treg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);\n+\tseparator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;\n+\tfor (j = 0; j < hw->num_msi; j++) {\n+\t\treg_offset = HNS3_TQP_INTR_REG_SIZE * j;\n+\t\tfor (i = 0; i < reg_um; i++)\n+\t\t\t*data++ = hns3_read_dev(hw,\n+\t\t\t\t\t\ttqp_intr_reg_addrs[i] +\n+\t\t\t\t\t\treg_offset);\n+\t\tfor (i = 0; i < separator_num; i++)\n+\t\t\t*data++ = SEPARATOR_VALUE;\n+\t}\n+}\n+\n+int\n+hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint32_t regs_num_32_bit;\n+\tuint32_t regs_num_64_bit;\n+\tuint32_t length;\n+\tuint32_t *data;\n+\tint ret;\n+\n+\tif (regs == NULL) {\n+\t\thns3_err(hw, \"the input parameter regs is NULL!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = hns3_get_regs_length(hw, &length);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdata = regs->data;\n+\tif (data == NULL) {\n+\t\tregs->length = length;\n+\t\tregs->width = sizeof(uint32_t);\n+\t\treturn 0;\n+\t}\n+\n+\t/* Only full register dump is supported */\n+\tif (regs->length && regs->length != length)\n+\t\treturn -ENOTSUP;\n+\n+\t/* fetching per-PF registers values from PF PCIe register space */\n+\thns3_direct_access_regs(hw, data);\n+\n+\tret = hns3_get_regs_num(hw, ®s_num_32_bit, ®s_num_64_bit);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Get register number failed, ret = %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* fetching PF common registers values from firmware */\n+\tret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);\n+\tif (ret) {\n+\t\thns3_err(hw, \"Get 32 bit register failed, ret = %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tdata += regs_num_32_bit;\n+\tret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);\n+\tif (ret)\n+\t\thns3_err(hw, \"Get 64 bit register failed, ret = %d\", ret);\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h\nindex 5a4f315..2f5faaf 100644\n--- a/drivers/net/hns3/hns3_regs.h\n+++ b/drivers/net/hns3/hns3_regs.h\n@@ -95,4 +95,5 @@\n \n #define HNS3_TQP_INTR_REG_SIZE\t\t\t4\n \n+int hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs);\n #endif /* _HNS3_REGS_H_ */\n", "prefixes": [ "17/22" ] }