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GET /api/patches/57846/?format=api
{ "id": 57846, "url": "http://patches.dpdk.org/api/patches/57846/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-5-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1566568031-45991-5-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-5-git-send-email-xavier.huwei@huawei.com", "date": "2019-08-23T13:46:53", "name": "[04/22] net/hns3: add support for cmd of hns3 PMD driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "de7d83f57a7836eebb0303b12f1e4d49462b7b8b", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-5-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6114, "url": "http://patches.dpdk.org/api/series/6114/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6114", "date": "2019-08-23T13:46:49", "name": "add hns3 ethernet PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/6114/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57846/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/57846/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 111B31BFD7;\n\tFri, 23 Aug 2019 15:49:46 +0200 (CEST)", "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 3709E1BFBF\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:33 +0200 (CEST)", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id 9FD3EEBCE1DE81B20004;\n\tFri, 23 Aug 2019 21:49:31 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:25 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Fri, 23 Aug 2019 21:46:53 +0800", "Message-ID": "<1566568031-45991-5-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 04/22] net/hns3: add support for cmd of hns3 PMD\n\tdriver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds support for cmd of hns3 PMD driver, driver can interact\nwith firmware through command to complete hardware configuration.\n\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_cmd.c | 524 ++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_cmd.h | 752 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_ethdev.c | 70 ++++\n drivers/net/hns3/hns3_ethdev.h | 2 +-\n 4 files changed, 1347 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/hns3/hns3_cmd.c\n create mode 100644 drivers/net/hns3/hns3_cmd.h", "diff": "diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c\nnew file mode 100644\nindex 0000000..f272374\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_cmd.c\n@@ -0,0 +1,524 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#include <errno.h>\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <sys/queue.h>\n+#include <inttypes.h>\n+#include <unistd.h>\n+#include <rte_alarm.h>\n+#include <rte_bus_pci.h>\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_dev.h>\n+#include <rte_eal.h>\n+#include <rte_ether.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_ethdev_pci.h>\n+#include <rte_flow.h>\n+#include <rte_flow_driver.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_io.h>\n+\n+#include \"hns3_cmd.h\"\n+#include \"hns3_ethdev.h\"\n+#include \"hns3_regs.h\"\n+#include \"hns3_logs.h\"\n+\n+#define hns3_is_csq(ring) ((ring)->flag & HNS3_TYPE_CSQ)\n+\n+#define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)\n+\n+static int\n+hns3_ring_space(struct hns3_cmq_ring *ring)\n+{\n+\tint ntu = ring->next_to_use;\n+\tint ntc = ring->next_to_clean;\n+\tint used = (ntu - ntc + ring->desc_num) % ring->desc_num;\n+\n+\treturn ring->desc_num - used - 1;\n+}\n+\n+static bool\n+is_valid_csq_clean_head(struct hns3_cmq_ring *ring, int head)\n+{\n+\tint ntu = ring->next_to_use;\n+\tint ntc = ring->next_to_clean;\n+\n+\tif (ntu > ntc)\n+\t\treturn head >= ntc && head <= ntu;\n+\n+\treturn head >= ntc || head <= ntu;\n+}\n+\n+/*\n+ * hns3_allocate_dma_mem - Specific memory alloc for command function.\n+ * Malloc a memzone, which is a contiguous portion of physical memory identified\n+ * by a name.\n+ * @ring: pointer to the ring structure\n+ * @size: size of memory requested\n+ * @alignment: what to align the allocation to\n+ */\n+static int\n+hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring,\n+\t\t uint64_t size, uint32_t alignment)\n+{\n+\tconst struct rte_memzone *mz = NULL;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tsnprintf(z_name, sizeof(z_name), \"hns3_dma_%\" PRIu64, rte_rand());\n+\tmz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,\n+\t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG, alignment,\n+\t\t\t\t\t RTE_PGSIZE_2M);\n+\tif (mz == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tring->buf_size = size;\n+\tring->desc = mz->addr;\n+\tring->desc_dma_addr = mz->iova;\n+\tring->zone = (const void *)mz;\n+\thns3_dbg(hw, \"memzone %s allocated with physical address: %\" PRIu64,\n+\t\t mz->name, ring->desc_dma_addr);\n+\n+\treturn 0;\n+}\n+\n+static void\n+hns3_free_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring)\n+{\n+\thns3_dbg(hw, \"memzone %s to be freed with physical address: %\" PRIu64,\n+\t\t ((const struct rte_memzone *)ring->zone)->name,\n+\t\t ring->desc_dma_addr);\n+\trte_memzone_free((const struct rte_memzone *)ring->zone);\n+\tring->buf_size = 0;\n+\tring->desc = NULL;\n+\tring->desc_dma_addr = 0;\n+\tring->zone = NULL;\n+}\n+\n+static int\n+hns3_alloc_cmd_desc(struct hns3_hw *hw, struct hns3_cmq_ring *ring)\n+{\n+\tint size = ring->desc_num * sizeof(struct hns3_cmd_desc);\n+\n+\tif (hns3_allocate_dma_mem(hw, ring, size, HNS3_CMD_DESC_ALIGNMENT)) {\n+\t\thns3_err(hw, \"allocate dma mem failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+hns3_free_cmd_desc(struct hns3_hw *hw, struct hns3_cmq_ring *ring)\n+{\n+\tif (ring->desc)\n+\t\thns3_free_dma_mem(hw, ring);\n+}\n+\n+static int\n+hns3_alloc_cmd_queue(struct hns3_hw *hw, int ring_type)\n+{\n+\tstruct hns3_cmq_ring *ring =\n+\t\t(ring_type == HNS3_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;\n+\tint ret;\n+\n+\tring->ring_type = ring_type;\n+\tring->hw = hw;\n+\n+\tret = hns3_alloc_cmd_desc(hw, ring);\n+\tif (ret)\n+\t\thns3_err(hw, \"descriptor %s alloc error %d\",\n+\t\t\t (ring_type == HNS3_TYPE_CSQ) ? \"CSQ\" : \"CRQ\", ret);\n+\n+\treturn ret;\n+}\n+\n+void\n+hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read)\n+{\n+\tdesc->flag = rte_cpu_to_le_16(HNS3_CMD_FLAG_NO_INTR | HNS3_CMD_FLAG_IN);\n+\tif (is_read)\n+\t\tdesc->flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_WR);\n+\telse\n+\t\tdesc->flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_WR);\n+}\n+\n+void\n+hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,\n+\t\t\t enum hns3_opcode_type opcode, bool is_read)\n+{\n+\tmemset((void *)desc, 0, sizeof(struct hns3_cmd_desc));\n+\tdesc->opcode = rte_cpu_to_le_16(opcode);\n+\tdesc->flag = rte_cpu_to_le_16(HNS3_CMD_FLAG_NO_INTR | HNS3_CMD_FLAG_IN);\n+\n+\tif (is_read)\n+\t\tdesc->flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_WR);\n+}\n+\n+static void\n+hns3_cmd_clear_regs(struct hns3_hw *hw)\n+{\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_ADDR_L_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_ADDR_H_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_HEAD_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_TAIL_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_RX_ADDR_L_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_RX_ADDR_H_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_RX_DEPTH_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_RX_HEAD_REG, 0);\n+\thns3_write_dev(hw, HNS3_CMDQ_RX_TAIL_REG, 0);\n+}\n+\n+static void\n+hns3_cmd_config_regs(struct hns3_cmq_ring *ring)\n+{\n+\tuint64_t dma = ring->desc_dma_addr;\n+\n+\tif (ring->ring_type == HNS3_TYPE_CSQ) {\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_TX_ADDR_L_REG,\n+\t\t\t lower_32_bits(dma));\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_TX_ADDR_H_REG,\n+\t\t\t upper_32_bits(dma));\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_TX_DEPTH_REG,\n+\t\t\t ring->desc_num >> HNS3_NIC_CMQ_DESC_NUM_S |\n+\t\t\t HNS3_NIC_SW_RST_RDY);\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_TX_HEAD_REG, 0);\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_TX_TAIL_REG, 0);\n+\t} else {\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_RX_ADDR_L_REG,\n+\t\t\t lower_32_bits(dma));\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_RX_ADDR_H_REG,\n+\t\t\t upper_32_bits(dma));\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_RX_DEPTH_REG,\n+\t\t\t ring->desc_num >> HNS3_NIC_CMQ_DESC_NUM_S);\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_RX_HEAD_REG, 0);\n+\t\thns3_write_dev(ring->hw, HNS3_CMDQ_RX_TAIL_REG, 0);\n+\t}\n+}\n+\n+static void\n+hns3_cmd_init_regs(struct hns3_hw *hw)\n+{\n+\thns3_cmd_config_regs(&hw->cmq.csq);\n+\thns3_cmd_config_regs(&hw->cmq.crq);\n+}\n+\n+static int\n+hns3_cmd_csq_clean(struct hns3_hw *hw)\n+{\n+\tstruct hns3_cmq_ring *csq = &hw->cmq.csq;\n+\tuint32_t head;\n+\tint clean;\n+\n+\thead = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG);\n+\n+\tif (!is_valid_csq_clean_head(csq, head)) {\n+\t\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\t\tuint32_t global;\n+\t\tuint32_t fun_rst;\n+\t\thns3_err(hw, \"wrong cmd head (%d, %d-%d)\", head,\n+\t\t\t csq->next_to_use, csq->next_to_clean);\n+\t\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\t\treturn -EIO;\n+\t}\n+\n+\tclean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;\n+\tcsq->next_to_clean = head;\n+\treturn clean;\n+}\n+\n+static int\n+hns3_cmd_csq_done(struct hns3_hw *hw)\n+{\n+\tuint32_t head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG);\n+\n+\treturn head == hw->cmq.csq.next_to_use;\n+}\n+\n+static bool\n+hns3_is_special_opcode(uint16_t opcode)\n+{\n+\t/*\n+\t * These commands have several descriptors,\n+\t * and use the first one to save opcode and return value.\n+\t */\n+\tuint16_t spec_opcode[] = {HNS3_OPC_STATS_64_BIT,\n+\t\t\t HNS3_OPC_STATS_32_BIT,\n+\t\t\t HNS3_OPC_STATS_MAC,\n+\t\t\t HNS3_OPC_STATS_MAC_ALL,\n+\t\t\t HNS3_OPC_QUERY_32_BIT_REG,\n+\t\t\t HNS3_OPC_QUERY_64_BIT_REG};\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(spec_opcode); i++)\n+\t\tif (spec_opcode[i] == opcode)\n+\t\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static int\n+hns3_cmd_get_hardware_reply(struct hns3_hw *hw,\n+\t\t\t struct hns3_cmd_desc *desc, int num, int ntc)\n+{\n+\tuint16_t opcode, desc_ret;\n+\tint current_ntc = ntc;\n+\tint retval = 0;\n+\tint handle;\n+\n+\topcode = rte_le_to_cpu_16(desc[0].opcode);\n+\thandle = 0;\n+\twhile (handle < num) {\n+\t\t/* Get the result of hardware write back */\n+\t\tdesc[handle] = hw->cmq.csq.desc[current_ntc];\n+\n+\t\tif (likely(!hns3_is_special_opcode(opcode)))\n+\t\t\tdesc_ret = rte_le_to_cpu_16(desc[handle].retval);\n+\t\telse\n+\t\t\tdesc_ret = rte_le_to_cpu_16(desc[0].retval);\n+\n+\t\tswitch (desc_ret) {\n+\t\tcase HNS3_CMD_EXEC_SUCCESS:\n+\t\t\tretval = 0;\n+\t\t\tbreak;\n+\t\tcase HNS3_CMD_NO_AUTH:\n+\t\t\tretval = -EPERM;\n+\t\t\tbreak;\n+\t\tcase HNS3_CMD_NOT_SUPPORTED:\n+\t\t\tretval = -EOPNOTSUPP;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tretval = -EIO;\n+\t\t}\n+\t\thw->cmq.last_status = desc_ret;\n+\t\tcurrent_ntc++;\n+\t\thandle++;\n+\t\tif (current_ntc == hw->cmq.csq.desc_num)\n+\t\t\tcurrent_ntc = 0;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+static int hns3_cmd_poll_reply(struct hns3_hw *hw)\n+{\n+\tstruct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);\n+\tuint32_t timeout = 0;\n+\n+\tdo {\n+\t\tif (hns3_cmd_csq_done(hw))\n+\t\t\treturn 0;\n+\n+\t\tif (rte_atomic16_read(&hw->reset.disable_cmd)) {\n+\t\t\thns3_err(hw,\n+\t\t\t\t \"Don't wait for reply because of disable_cmd\");\n+\t\t\treturn -EBUSY;\n+\t\t}\n+\n+\t\trte_delay_us(1);\n+\t\ttimeout++;\n+\t} while (timeout < hw->cmq.tx_timeout);\n+\thns3_err(hw, \"Wait for reply timeout\");\n+\treturn -ETIME;\n+}\n+\n+/*\n+ * hns3_cmd_send - send command to command queue\n+ * @hw: pointer to the hw struct\n+ * @desc: prefilled descriptor for describing the command\n+ * @num : the number of descriptors to be sent\n+ *\n+ * This is the main send command for command queue, it\n+ * sends the queue, cleans the queue, etc\n+ */\n+int\n+hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)\n+{\n+\tstruct hns3_cmd_desc *desc_to_use;\n+\tint handle = 0;\n+\tint retval;\n+\tuint32_t ntc;\n+\n+\tif (rte_atomic16_read(&hw->reset.disable_cmd))\n+\t\treturn -EBUSY;\n+\n+\trte_spinlock_lock(&hw->cmq.csq.lock);\n+\n+\t/* Clean the command send queue */\n+\tretval = hns3_cmd_csq_clean(hw);\n+\tif (retval < 0) {\n+\t\trte_spinlock_unlock(&hw->cmq.csq.lock);\n+\t\treturn retval;\n+\t}\n+\n+\tif (num > hns3_ring_space(&hw->cmq.csq)) {\n+\t\trte_spinlock_unlock(&hw->cmq.csq.lock);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/*\n+\t * Record the location of desc in the ring for this time\n+\t * which will be use for hardware to write back\n+\t */\n+\tntc = hw->cmq.csq.next_to_use;\n+\n+\twhile (handle < num) {\n+\t\tdesc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];\n+\t\t*desc_to_use = desc[handle];\n+\t\t(hw->cmq.csq.next_to_use)++;\n+\t\tif (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)\n+\t\t\thw->cmq.csq.next_to_use = 0;\n+\t\thandle++;\n+\t}\n+\n+\t/* Write to hardware */\n+\thns3_write_dev(hw, HNS3_CMDQ_TX_TAIL_REG, hw->cmq.csq.next_to_use);\n+\n+\t/*\n+\t * If the command is sync, wait for the firmware to write back,\n+\t * if multi descriptors to be sent, use the first one to check.\n+\t */\n+\tif (HNS3_CMD_SEND_SYNC(rte_le_to_cpu_16(desc->flag))) {\n+\t\tretval = hns3_cmd_poll_reply(hw);\n+\t\tif (!retval)\n+\t\t\tretval = hns3_cmd_get_hardware_reply(hw, desc, num,\n+\t\t\t\t\t\t\t ntc);\n+\t}\n+\n+\trte_spinlock_unlock(&hw->cmq.csq.lock);\n+\treturn retval;\n+}\n+\n+static enum hns3_cmd_status\n+hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)\n+{\n+\tstruct hns3_query_version_cmd *resp;\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FW_VER, 1);\n+\tresp = (struct hns3_query_version_cmd *)desc.data;\n+\n+\t/* Initialize the cmd function */\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret == 0)\n+\t\t*version = rte_le_to_cpu_32(resp->firmware);\n+\n+\treturn ret;\n+}\n+\n+int\n+hns3_cmd_init_queue(struct hns3_hw *hw)\n+{\n+\tint ret;\n+\n+\t/* Setup the lock for command queue */\n+\trte_spinlock_init(&hw->cmq.csq.lock);\n+\trte_spinlock_init(&hw->cmq.crq.lock);\n+\n+\t/*\n+\t * Clear up all command register,\n+\t * in case there are some residual values\n+\t */\n+\thns3_cmd_clear_regs(hw);\n+\n+\t/* Setup the queue entries for use cmd queue */\n+\thw->cmq.csq.desc_num = HNS3_NIC_CMQ_DESC_NUM;\n+\thw->cmq.crq.desc_num = HNS3_NIC_CMQ_DESC_NUM;\n+\n+\t/* Setup Tx write back timeout */\n+\thw->cmq.tx_timeout = HNS3_CMDQ_TX_TIMEOUT;\n+\n+\t/* Setup queue rings */\n+\tret = hns3_alloc_cmd_queue(hw, HNS3_TYPE_CSQ);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"CSQ ring setup error %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hns3_alloc_cmd_queue(hw, HNS3_TYPE_CRQ);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"CRQ ring setup error %d\", ret);\n+\t\tgoto err_crq;\n+\t}\n+\n+\treturn 0;\n+\n+err_crq:\n+\thns3_free_cmd_desc(hw, &hw->cmq.csq);\n+\n+\treturn ret;\n+}\n+\n+int\n+hns3_cmd_init(struct hns3_hw *hw)\n+{\n+\tint ret;\n+\n+\trte_spinlock_lock(&hw->cmq.csq.lock);\n+\trte_spinlock_lock(&hw->cmq.crq.lock);\n+\n+\thw->cmq.csq.next_to_clean = 0;\n+\thw->cmq.csq.next_to_use = 0;\n+\thw->cmq.crq.next_to_clean = 0;\n+\thw->cmq.crq.next_to_use = 0;\n+\thw->mbx_resp.head = 0;\n+\thw->mbx_resp.tail = 0;\n+\thw->mbx_resp.lost = 0;\n+\thns3_cmd_init_regs(hw);\n+\n+\trte_spinlock_unlock(&hw->cmq.crq.lock);\n+\trte_spinlock_unlock(&hw->cmq.csq.lock);\n+\n+\trte_atomic16_clear(&hw->reset.disable_cmd);\n+\n+\tret = hns3_cmd_query_firmware_version(hw, &hw->fw_version);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"firmware version query failed %d\", ret);\n+\t\tgoto err_cmd_init;\n+\t}\n+\n+\tPMD_INIT_LOG(INFO, \"The firmware version is %08x\", hw->fw_version);\n+\n+\treturn 0;\n+\n+err_cmd_init:\n+\thns3_cmd_uninit(hw);\n+\treturn ret;\n+}\n+\n+static void\n+hns3_destroy_queue(struct hns3_hw *hw, struct hns3_cmq_ring *ring)\n+{\n+\trte_spinlock_lock(&ring->lock);\n+\n+\thns3_free_cmd_desc(hw, ring);\n+\n+\trte_spinlock_unlock(&ring->lock);\n+}\n+\n+void\n+hns3_cmd_destroy_queue(struct hns3_hw *hw)\n+{\n+\thns3_destroy_queue(hw, &hw->cmq.csq);\n+\thns3_destroy_queue(hw, &hw->cmq.crq);\n+}\n+\n+void\n+hns3_cmd_uninit(struct hns3_hw *hw)\n+{\n+\trte_spinlock_lock(&hw->cmq.csq.lock);\n+\trte_spinlock_lock(&hw->cmq.crq.lock);\n+\trte_atomic16_set(&hw->reset.disable_cmd, 1);\n+\thns3_cmd_clear_regs(hw);\n+\trte_spinlock_unlock(&hw->cmq.crq.lock);\n+\trte_spinlock_unlock(&hw->cmq.csq.lock);\n+}\ndiff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nnew file mode 100644\nindex 0000000..b72d5cb\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -0,0 +1,752 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#ifndef _HNS3_CMD_H_\n+#define _HNS3_CMD_H_\n+\n+#define HNS3_CMDQ_TX_TIMEOUT\t\t30000\n+#define HNS3_CMDQ_RX_INVLD_B\t\t0\n+#define HNS3_CMDQ_RX_OUTVLD_B\t\t1\n+#define HNS3_CMD_DESC_ALIGNMENT\t\t4096\n+#define HNS3_QUEUE_ID_MASK\t\t0x1ff\n+#define HNS3_CMD_FLAG_NEXT\t\tBIT(2)\n+\n+struct hns3_hw;\n+\n+#define HNS3_CMD_DESC_DATA_NUM\t6\n+struct hns3_cmd_desc {\n+\tuint16_t opcode;\n+\tuint16_t flag;\n+\tuint16_t retval;\n+\tuint16_t rsv;\n+\tuint32_t data[HNS3_CMD_DESC_DATA_NUM];\n+};\n+\n+struct hns3_cmq_ring {\n+\tuint64_t desc_dma_addr;\n+\tstruct hns3_cmd_desc *desc;\n+\tstruct hns3_hw *hw;\n+\n+\tuint16_t buf_size;\n+\tuint16_t desc_num; /* max number of cmq descriptor */\n+\tuint32_t next_to_use;\n+\tuint32_t next_to_clean;\n+\tuint8_t ring_type; /* cmq ring type */\n+\trte_spinlock_t lock; /* Command queue lock */\n+\n+\tconst void *zone; /* memory zone */\n+};\n+\n+enum hns3_cmd_return_status {\n+\tHNS3_CMD_EXEC_SUCCESS\t= 0,\n+\tHNS3_CMD_NO_AUTH\t= 1,\n+\tHNS3_CMD_NOT_SUPPORTED\t= 2,\n+\tHNS3_CMD_QUEUE_FULL\t= 3,\n+};\n+\n+enum hns3_cmd_status {\n+\tHNS3_STATUS_SUCCESS\t= 0,\n+\tHNS3_ERR_CSQ_FULL\t= -1,\n+\tHNS3_ERR_CSQ_TIMEOUT\t= -2,\n+\tHNS3_ERR_CSQ_ERROR\t= -3,\n+};\n+\n+struct hns3_misc_vector {\n+\tuint8_t *addr;\n+\tint vector_irq;\n+};\n+\n+struct hns3_cmq {\n+\tstruct hns3_cmq_ring csq;\n+\tstruct hns3_cmq_ring crq;\n+\tuint16_t tx_timeout;\n+\tenum hns3_cmd_status last_status;\n+};\n+\n+enum hns3_opcode_type {\n+\t/* Generic commands */\n+\tHNS3_OPC_QUERY_FW_VER = 0x0001,\n+\tHNS3_OPC_CFG_RST_TRIGGER = 0x0020,\n+\tHNS3_OPC_GBL_RST_STATUS = 0x0021,\n+\tHNS3_OPC_QUERY_FUNC_STATUS = 0x0022,\n+\tHNS3_OPC_QUERY_PF_RSRC = 0x0023,\n+\tHNS3_OPC_GET_CFG_PARAM = 0x0025,\n+\tHNS3_OPC_PF_RST_DONE = 0x0026,\n+\n+\tHNS3_OPC_STATS_64_BIT = 0x0030,\n+\tHNS3_OPC_STATS_32_BIT = 0x0031,\n+\tHNS3_OPC_STATS_MAC = 0x0032,\n+\tHNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,\n+\tHNS3_OPC_STATS_MAC_ALL = 0x0034,\n+\n+\tHNS3_OPC_QUERY_REG_NUM = 0x0040,\n+\tHNS3_OPC_QUERY_32_BIT_REG = 0x0041,\n+\tHNS3_OPC_QUERY_64_BIT_REG = 0x0042,\n+\n+\t/* MAC command */\n+\tHNS3_OPC_CONFIG_MAC_MODE = 0x0301,\n+\tHNS3_OPC_QUERY_LINK_STATUS = 0x0307,\n+\tHNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,\n+\tHNS3_OPC_CONFIG_SPEED_DUP = 0x0309,\n+\tHNS3_MAC_COMMON_INT_EN = 0x030E,\n+\n+\t/* PFC/Pause commands */\n+\tHNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,\n+\tHNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,\n+\tHNS3_OPC_CFG_MAC_PARA = 0x0703,\n+\tHNS3_OPC_CFG_PFC_PARA = 0x0704,\n+\tHNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,\n+\tHNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,\n+\tHNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,\n+\tHNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,\n+\tHNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,\n+\tHNS3_OPC_QOS_MAP = 0x070A,\n+\n+\t/* ETS/scheduler commands */\n+\tHNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,\n+\tHNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,\n+\tHNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,\n+\tHNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,\n+\tHNS3_OPC_TM_PORT_WEIGHT = 0x0808,\n+\tHNS3_OPC_TM_PG_WEIGHT = 0x0809,\n+\tHNS3_OPC_TM_QS_WEIGHT = 0x080A,\n+\tHNS3_OPC_TM_PRI_WEIGHT = 0x080B,\n+\tHNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,\n+\tHNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,\n+\tHNS3_OPC_TM_PG_C_SHAPPING = 0x080E,\n+\tHNS3_OPC_TM_PG_P_SHAPPING = 0x080F,\n+\tHNS3_OPC_TM_PORT_SHAPPING = 0x0810,\n+\tHNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,\n+\tHNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,\n+\tHNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,\n+\tHNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,\n+\tHNS3_OPC_ETS_TC_WEIGHT = 0x0843,\n+\tHNS3_OPC_QSET_DFX_STS = 0x0844,\n+\tHNS3_OPC_PRI_DFX_STS = 0x0845,\n+\tHNS3_OPC_PG_DFX_STS = 0x0846,\n+\tHNS3_OPC_PORT_DFX_STS = 0x0847,\n+\tHNS3_OPC_SCH_NQ_CNT = 0x0848,\n+\tHNS3_OPC_SCH_RQ_CNT = 0x0849,\n+\tHNS3_OPC_TM_INTERNAL_STS = 0x0850,\n+\tHNS3_OPC_TM_INTERNAL_CNT = 0x0851,\n+\tHNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,\n+\n+\t/* Mailbox cmd */\n+\tHNS3_OPC_MBX_VF_TO_PF = 0x2001,\n+\n+\t/* Packet buffer allocate commands */\n+\tHNS3_OPC_TX_BUFF_ALLOC = 0x0901,\n+\tHNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,\n+\tHNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,\n+\tHNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,\n+\tHNS3_OPC_RX_COM_WL_ALLOC = 0x0905,\n+\n+\t/* SSU module INT commands */\n+\tHNS3_SSU_ECC_INT_CMD = 0x0989,\n+\tHNS3_SSU_COMMON_INT_CMD = 0x098C,\n+\n+\t/* TQP management command */\n+\tHNS3_OPC_SET_TQP_MAP = 0x0A01,\n+\n+\t/* TQP commands */\n+\tHNS3_OPC_QUERY_TX_STATUS = 0x0B03,\n+\tHNS3_OPC_QUERY_RX_STATUS = 0x0B13,\n+\tHNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,\n+\tHNS3_OPC_RESET_TQP_QUEUE = 0x0B22,\n+\n+\t/* PPU module intr commands */\n+\tHNS3_PPU_MPF_ECC_INT_CMD = 0x0B40,\n+\tHNS3_PPU_MPF_OTHER_INT_CMD = 0x0B41,\n+\tHNS3_PPU_PF_OTHER_INT_CMD = 0x0B42,\n+\n+\t/* TSO command */\n+\tHNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,\n+\tHNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,\n+\n+\t/* RSS commands */\n+\tHNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,\n+\tHNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,\n+\tHNS3_OPC_RSS_INDIR_TABLE = 0x0D07,\n+\tHNS3_OPC_RSS_TC_MODE = 0x0D08,\n+\n+\t/* Promisuous mode command */\n+\tHNS3_OPC_CFG_PROMISC_MODE = 0x0E01,\n+\n+\t/* Vlan offload commands */\n+\tHNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,\n+\tHNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,\n+\n+\t/* MAC commands */\n+\tHNS3_OPC_MAC_VLAN_ADD = 0x1000,\n+\tHNS3_OPC_MAC_VLAN_REMOVE = 0x1001,\n+\tHNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,\n+\tHNS3_OPC_MAC_VLAN_INSERT = 0x1003,\n+\tHNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,\n+\tHNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,\n+\n+\t/* VLAN commands */\n+\tHNS3_OPC_VLAN_FILTER_CTRL = 0x1100,\n+\tHNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,\n+\tHNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,\n+\n+\t/* Flow Director command */\n+\tHNS3_OPC_FD_MODE_CTRL = 0x1200,\n+\tHNS3_OPC_FD_GET_ALLOCATION = 0x1201,\n+\tHNS3_OPC_FD_KEY_CONFIG = 0x1202,\n+\tHNS3_OPC_FD_TCAM_OP = 0x1203,\n+\tHNS3_OPC_FD_AD_OP = 0x1204,\n+\tHNS3_OPC_FD_COUNTER_OP = 0x1205,\n+\n+\t/* SFP command */\n+\tHNS3_OPC_SFP_GET_SPEED = 0x7104,\n+\n+\t/* Error INT commands */\n+\tHNS3_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,\n+\tHNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,\n+\tHNS3_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,\n+\n+\t/* PPP module intr commands */\n+\tHNS3_PPP_CMD0_INT_CMD = 0x2100,\n+\tHNS3_PPP_CMD1_INT_CMD = 0x2101,\n+};\n+\n+#define HNS3_CMD_FLAG_IN\tBIT(0)\n+#define HNS3_CMD_FLAG_OUT\tBIT(1)\n+#define HNS3_CMD_FLAG_NEXT\tBIT(2)\n+#define HNS3_CMD_FLAG_WR\tBIT(3)\n+#define HNS3_CMD_FLAG_NO_INTR\tBIT(4)\n+#define HNS3_CMD_FLAG_ERR_INTR\tBIT(5)\n+\n+#define HNS3_BUF_SIZE_UNIT\t256\n+#define HNS3_BUF_MUL_BY\t\t2\n+#define HNS3_BUF_DIV_BY\t\t2\n+#define NEED_RESERVE_TC_NUM\t2\n+#define BUF_MAX_PERCENT\t\t100\n+#define BUF_RESERVE_PERCENT\t90\n+\n+#define HNS3_MAX_TC_NUM\t\t8\n+#define HNS3_TC0_PRI_BUF_EN_B\t15 /* Bit 15 indicate enable or not */\n+#define HNS3_BUF_UNIT_S\t\t7 /* Buf size is united by 128 bytes */\n+#define HNS3_TX_BUFF_RSV_NUM\t8\n+struct hns3_tx_buff_alloc_cmd {\n+\tuint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];\n+\tuint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];\n+};\n+\n+struct hns3_rx_priv_buff_cmd {\n+\tuint16_t buf_num[HNS3_MAX_TC_NUM];\n+\tuint16_t shared_buf;\n+\tuint8_t rsv[6];\n+};\n+\n+struct hns3_query_version_cmd {\n+\tuint32_t firmware;\n+\tuint32_t firmware_rsv[5];\n+};\n+\n+#define HNS3_RX_PRIV_EN_B\t15\n+#define HNS3_TC_NUM_ONE_DESC\t4\n+struct hns3_priv_wl {\n+\tuint16_t high;\n+\tuint16_t low;\n+};\n+\n+struct hns3_rx_priv_wl_buf {\n+\tstruct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];\n+};\n+\n+struct hns3_rx_com_thrd {\n+\tstruct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];\n+};\n+\n+struct hns3_rx_com_wl {\n+\tstruct hns3_priv_wl com_wl;\n+};\n+\n+struct hns3_waterline {\n+\tuint32_t low;\n+\tuint32_t high;\n+};\n+\n+struct hns3_tc_thrd {\n+\tuint32_t low;\n+\tuint32_t high;\n+};\n+\n+struct hns3_priv_buf {\n+\tstruct hns3_waterline wl; /* Waterline for low and high */\n+\tuint32_t buf_size; /* TC private buffer size */\n+\tuint32_t tx_buf_size;\n+\tuint32_t enable; /* Enable TC private buffer or not */\n+};\n+\n+struct hns3_shared_buf {\n+\tstruct hns3_waterline self;\n+\tstruct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];\n+\tuint32_t buf_size;\n+};\n+\n+struct hns3_pkt_buf_alloc {\n+\tstruct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];\n+\tstruct hns3_shared_buf s_buf;\n+};\n+\n+#define HNS3_RX_COM_WL_EN_B\t15\n+struct hns3_rx_com_wl_buf_cmd {\n+\tuint16_t high_wl;\n+\tuint16_t low_wl;\n+\tuint8_t rsv[20];\n+};\n+\n+#define HNS3_RX_PKT_EN_B\t15\n+struct hns3_rx_pkt_buf_cmd {\n+\tuint16_t high_pkt;\n+\tuint16_t low_pkt;\n+\tuint8_t rsv[20];\n+};\n+\n+#define HNS3_PF_STATE_DONE_B\t0\n+#define HNS3_PF_STATE_MAIN_B\t1\n+#define HNS3_PF_STATE_BOND_B\t2\n+#define HNS3_PF_STATE_MAC_N_B\t6\n+#define HNS3_PF_MAC_NUM_MASK\t0x3\n+#define HNS3_PF_STATE_MAIN\tBIT(HNS3_PF_STATE_MAIN_B)\n+#define HNS3_PF_STATE_DONE\tBIT(HNS3_PF_STATE_DONE_B)\n+#define HNS3_VF_RST_STATE_NUM\t4\n+struct hns3_func_status_cmd {\n+\tuint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];\n+\tuint8_t pf_state;\n+\tuint8_t mac_id;\n+\tuint8_t rsv1;\n+\tuint8_t pf_cnt_in_mac;\n+\tuint8_t pf_num;\n+\tuint8_t vf_num;\n+\tuint8_t rsv[2];\n+};\n+\n+#define HNS3_PF_VEC_NUM_S\t\t0\n+#define HNS3_PF_VEC_NUM_M\t\tGENMASK(7, 0)\n+struct hns3_pf_res_cmd {\n+\tuint16_t tqp_num;\n+\tuint16_t buf_size;\n+\tuint16_t msixcap_localid_ba_nic;\n+\tuint16_t msixcap_localid_ba_rocee;\n+\tuint16_t pf_intr_vector_number;\n+\tuint16_t pf_own_fun_number;\n+\tuint16_t tx_buf_size;\n+\tuint16_t dv_buf_size;\n+\tuint32_t rsv[2];\n+};\n+\n+#define HNS3_UMV_SPC_ALC_B\t0\n+struct hns3_umv_spc_alc_cmd {\n+\tuint8_t allocate;\n+\tuint8_t rsv1[3];\n+\tuint32_t space_size;\n+\tuint8_t rsv2[16];\n+};\n+\n+#define HNS3_CFG_OFFSET_S\t\t0\n+#define HNS3_CFG_OFFSET_M\t\tGENMASK(19, 0)\n+#define HNS3_CFG_RD_LEN_S\t\t24\n+#define HNS3_CFG_RD_LEN_M\t\tGENMASK(27, 24)\n+#define HNS3_CFG_RD_LEN_BYTES\t\t16\n+#define HNS3_CFG_RD_LEN_UNIT\t\t4\n+\n+#define HNS3_CFG_VMDQ_S\t\t\t0\n+#define HNS3_CFG_VMDQ_M\t\t\tGENMASK(7, 0)\n+#define HNS3_CFG_TC_NUM_S\t\t8\n+#define HNS3_CFG_TC_NUM_M\t\tGENMASK(15, 8)\n+#define HNS3_CFG_TQP_DESC_N_S\t\t16\n+#define HNS3_CFG_TQP_DESC_N_M\t\tGENMASK(31, 16)\n+#define HNS3_CFG_PHY_ADDR_S\t\t0\n+#define HNS3_CFG_PHY_ADDR_M\t\tGENMASK(7, 0)\n+#define HNS3_CFG_MEDIA_TP_S\t\t8\n+#define HNS3_CFG_MEDIA_TP_M\t\tGENMASK(15, 8)\n+#define HNS3_CFG_RX_BUF_LEN_S\t\t16\n+#define HNS3_CFG_RX_BUF_LEN_M\t\tGENMASK(31, 16)\n+#define HNS3_CFG_MAC_ADDR_H_S\t\t0\n+#define HNS3_CFG_MAC_ADDR_H_M\t\tGENMASK(15, 0)\n+#define HNS3_CFG_DEFAULT_SPEED_S\t16\n+#define HNS3_CFG_DEFAULT_SPEED_M\tGENMASK(23, 16)\n+#define HNS3_CFG_RSS_SIZE_S\t\t24\n+#define HNS3_CFG_RSS_SIZE_M\t\tGENMASK(31, 24)\n+#define HNS3_CFG_SPEED_ABILITY_S\t0\n+#define HNS3_CFG_SPEED_ABILITY_M\tGENMASK(7, 0)\n+#define HNS3_CFG_UMV_TBL_SPACE_S\t16\n+#define HNS3_CFG_UMV_TBL_SPACE_M\tGENMASK(31, 16)\n+\n+#define HNS3_ACCEPT_TAG1_B\t\t0\n+#define HNS3_ACCEPT_UNTAG1_B\t\t1\n+#define HNS3_PORT_INS_TAG1_EN_B\t\t2\n+#define HNS3_PORT_INS_TAG2_EN_B\t\t3\n+#define HNS3_CFG_NIC_ROCE_SEL_B\t\t4\n+#define HNS3_ACCEPT_TAG2_B\t\t5\n+#define HNS3_ACCEPT_UNTAG2_B\t\t6\n+\n+#define HNS3_REM_TAG1_EN_B\t\t0\n+#define HNS3_REM_TAG2_EN_B\t\t1\n+#define HNS3_SHOW_TAG1_EN_B\t\t2\n+#define HNS3_SHOW_TAG2_EN_B\t\t3\n+\n+/* Factor used to calculate offset and bitmap of VF num */\n+#define HNS3_VF_NUM_PER_CMD 64\n+#define HNS3_VF_NUM_PER_BYTE 8\n+\n+struct hns3_cfg_param_cmd {\n+\tuint32_t offset;\n+\tuint32_t rsv;\n+\tuint32_t param[4];\n+};\n+\n+#define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM\t8\n+struct hns3_vport_vtag_rx_cfg_cmd {\n+\tuint8_t vport_vlan_cfg;\n+\tuint8_t vf_offset;\n+\tuint8_t rsv1[6];\n+\tuint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];\n+\tuint8_t rsv2[8];\n+};\n+\n+struct hns3_vport_vtag_tx_cfg_cmd {\n+\tuint8_t vport_vlan_cfg;\n+\tuint8_t vf_offset;\n+\tuint8_t rsv1[2];\n+\tuint16_t def_vlan_tag1;\n+\tuint16_t def_vlan_tag2;\n+\tuint8_t vf_bitmap[8];\n+\tuint8_t rsv2[8];\n+};\n+\n+\n+struct hns3_vlan_filter_ctrl_cmd {\n+\tuint8_t vlan_type;\n+\tuint8_t vlan_fe;\n+\tuint8_t rsv1[2];\n+\tuint8_t vf_id;\n+\tuint8_t rsv2[19];\n+};\n+\n+#define HNS3_VLAN_OFFSET_BITMAP_NUM\t20\n+struct hns3_vlan_filter_pf_cfg_cmd {\n+\tuint8_t vlan_offset;\n+\tuint8_t vlan_cfg;\n+\tuint8_t rsv[2];\n+\tuint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];\n+};\n+\n+#define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM\t16\n+struct hns3_vlan_filter_vf_cfg_cmd {\n+\tuint16_t vlan_id;\n+\tuint8_t resp_code;\n+\tuint8_t rsv;\n+\tuint8_t vlan_cfg;\n+\tuint8_t rsv1[3];\n+\tuint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];\n+};\n+\n+struct hns3_tx_vlan_type_cfg_cmd {\n+\tuint16_t ot_vlan_type;\n+\tuint16_t in_vlan_type;\n+\tuint8_t rsv[20];\n+};\n+\n+struct hns3_rx_vlan_type_cfg_cmd {\n+\tuint16_t ot_fst_vlan_type;\n+\tuint16_t ot_sec_vlan_type;\n+\tuint16_t in_fst_vlan_type;\n+\tuint16_t in_sec_vlan_type;\n+\tuint8_t rsv[16];\n+};\n+\n+#define HNS3_TSO_MSS_MIN_S\t0\n+#define HNS3_TSO_MSS_MIN_M\tGENMASK(13, 0)\n+\n+#define HNS3_TSO_MSS_MAX_S\t16\n+#define HNS3_TSO_MSS_MAX_M\tGENMASK(29, 16)\n+\n+struct hns3_cfg_tso_status_cmd {\n+\trte_le16_t tso_mss_min;\n+\trte_le16_t tso_mss_max;\n+\tuint8_t rsv[20];\n+};\n+\n+#define HNS3_GRO_EN_B\t\t0\n+struct hns3_cfg_gro_status_cmd {\n+\trte_le16_t gro_en;\n+\tuint8_t rsv[22];\n+};\n+\n+#define HNS3_TSO_MSS_MIN\t256\n+#define HNS3_TSO_MSS_MAX\t9668\n+\n+#define HNS3_RSS_HASH_KEY_OFFSET_B\t4\n+\n+#define HNS3_RSS_CFG_TBL_SIZE\t16\n+#define HNS3_RSS_HASH_KEY_NUM\t16\n+/* Configure the algorithm mode and Hash Key, opcode:0x0D01 */\n+struct hns3_rss_generic_config_cmd {\n+\t/* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */\n+\tuint8_t hash_config;\n+\tuint8_t rsv[7];\n+\tuint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];\n+};\n+\n+/* Configure the tuple selection for RSS hash input, opcode:0x0D02 */\n+struct hns3_rss_input_tuple_cmd {\n+\tuint8_t ipv4_tcp_en;\n+\tuint8_t ipv4_udp_en;\n+\tuint8_t ipv4_sctp_en;\n+\tuint8_t ipv4_fragment_en;\n+\tuint8_t ipv6_tcp_en;\n+\tuint8_t ipv6_udp_en;\n+\tuint8_t ipv6_sctp_en;\n+\tuint8_t ipv6_fragment_en;\n+\tuint8_t rsv[16];\n+};\n+\n+#define HNS3_RSS_CFG_TBL_SIZE\t16\n+\n+/* Configure the indirection table, opcode:0x0D07 */\n+struct hns3_rss_indirection_table_cmd {\n+\tuint16_t start_table_index; /* Bit3~0 must be 0x0. */\n+\tuint16_t rss_set_bitmap;\n+\tuint8_t rsv[4];\n+\tuint8_t rss_result[HNS3_RSS_CFG_TBL_SIZE];\n+};\n+\n+#define HNS3_RSS_TC_OFFSET_S\t\t0\n+#define HNS3_RSS_TC_OFFSET_M\t\t(0x3ff << HNS3_RSS_TC_OFFSET_S)\n+#define HNS3_RSS_TC_SIZE_S\t\t12\n+#define HNS3_RSS_TC_SIZE_M\t\t(0x7 << HNS3_RSS_TC_SIZE_S)\n+#define HNS3_RSS_TC_VALID_B\t\t15\n+\n+/* Configure the tc_size and tc_offset, opcode:0x0D08 */\n+struct hns3_rss_tc_mode_cmd {\n+\tuint16_t rss_tc_mode[HNS3_MAX_TC_NUM];\n+\tuint8_t rsv[8];\n+};\n+\n+#define HNS3_LINK_STATUS_UP_B\t0\n+#define HNS3_LINK_STATUS_UP_M\tBIT(HNS3_LINK_STATUS_UP_B)\n+struct hns3_link_status_cmd {\n+\tuint8_t status;\n+\tuint8_t rsv[23];\n+};\n+\n+struct hns3_promisc_param {\n+\tuint8_t vf_id;\n+\tuint8_t enable;\n+};\n+\n+#define HNS3_PROMISC_TX_EN_B\tBIT(4)\n+#define HNS3_PROMISC_RX_EN_B\tBIT(5)\n+#define HNS3_PROMISC_EN_B\t1\n+#define HNS3_PROMISC_EN_ALL\t0x7\n+#define HNS3_PROMISC_EN_UC\t0x1\n+#define HNS3_PROMISC_EN_MC\t0x2\n+#define HNS3_PROMISC_EN_BC\t0x4\n+struct hns3_promisc_cfg_cmd {\n+\tuint8_t flag;\n+\tuint8_t vf_id;\n+\tuint16_t rsv0;\n+\tuint8_t rsv1[20];\n+};\n+\n+enum hns3_promisc_type {\n+\tHNS3_UNICAST\t= 1,\n+\tHNS3_MULTICAST\t= 2,\n+\tHNS3_BROADCAST\t= 3,\n+};\n+\n+#define HNS3_MAC_TX_EN_B\t\t6\n+#define HNS3_MAC_RX_EN_B\t\t7\n+#define HNS3_MAC_PAD_TX_B\t\t11\n+#define HNS3_MAC_PAD_RX_B\t\t12\n+#define HNS3_MAC_1588_TX_B\t\t13\n+#define HNS3_MAC_1588_RX_B\t\t14\n+#define HNS3_MAC_APP_LP_B\t\t15\n+#define HNS3_MAC_LINE_LP_B\t\t16\n+#define HNS3_MAC_FCS_TX_B\t\t17\n+#define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B\t18\n+#define HNS3_MAC_RX_FCS_STRIP_B\t\t19\n+#define HNS3_MAC_RX_FCS_B\t\t20\n+#define HNS3_MAC_TX_UNDER_MIN_ERR_B\t21\n+#define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B\t22\n+\n+struct hns3_config_mac_mode_cmd {\n+\tuint32_t txrx_pad_fcs_loop_en;\n+\tuint8_t rsv[20];\n+};\n+\n+#define HNS3_CFG_SPEED_10M\t\t6\n+#define HNS3_CFG_SPEED_100M\t\t7\n+#define HNS3_CFG_SPEED_1G\t\t0\n+#define HNS3_CFG_SPEED_10G\t\t1\n+#define HNS3_CFG_SPEED_25G\t\t2\n+#define HNS3_CFG_SPEED_40G\t\t3\n+#define HNS3_CFG_SPEED_50G\t\t4\n+#define HNS3_CFG_SPEED_100G\t\t5\n+\n+#define HNS3_CFG_SPEED_S\t\t0\n+#define HNS3_CFG_SPEED_M\t\tGENMASK(5, 0)\n+#define HNS3_CFG_DUPLEX_B\t\t7\n+#define HNS3_CFG_DUPLEX_M\t\tBIT(HNS3_CFG_DUPLEX_B)\n+\n+#define HNS3_CFG_MAC_SPEED_CHANGE_EN_B\t0\n+\n+struct hns3_config_mac_speed_dup_cmd {\n+\tuint8_t speed_dup;\n+\tuint8_t mac_change_fec_en;\n+\tuint8_t rsv[22];\n+};\n+\n+#define HNS3_RING_ID_MASK\t\tGENMASK(9, 0)\n+#define HNS3_TQP_ENABLE_B\t\t0\n+\n+#define HNS3_MAC_CFG_AN_EN_B\t\t0\n+#define HNS3_MAC_CFG_AN_INT_EN_B\t1\n+#define HNS3_MAC_CFG_AN_INT_MSK_B\t2\n+#define HNS3_MAC_CFG_AN_INT_CLR_B\t3\n+#define HNS3_MAC_CFG_AN_RST_B\t\t4\n+\n+#define HNS3_MAC_CFG_AN_EN\tBIT(HNS3_MAC_CFG_AN_EN_B)\n+\n+struct hns3_config_auto_neg_cmd {\n+\tuint32_t cfg_an_cmd_flag;\n+\tuint8_t rsv[20];\n+};\n+\n+struct hns3_sfp_speed_cmd {\n+\tuint32_t sfp_speed;\n+\tuint32_t rsv[5];\n+};\n+\n+#define HNS3_MAC_MGR_MASK_VLAN_B\t\tBIT(0)\n+#define HNS3_MAC_MGR_MASK_MAC_B\t\t\tBIT(1)\n+#define HNS3_MAC_MGR_MASK_ETHERTYPE_B\t\tBIT(2)\n+#define HNS3_MAC_ETHERTYPE_LLDP\t\t\t0x88cc\n+\n+struct hns3_mac_mgr_tbl_entry_cmd {\n+\tuint8_t flags;\n+\tuint8_t resp_code;\n+\tuint16_t vlan_tag;\n+\tuint32_t mac_addr_hi32;\n+\tuint16_t mac_addr_lo16;\n+\tuint16_t rsv1;\n+\tuint16_t ethter_type;\n+\tuint16_t egress_port;\n+\tuint16_t egress_queue;\n+\tuint8_t sw_port_id_aware;\n+\tuint8_t rsv2;\n+\tuint8_t i_port_bitmap;\n+\tuint8_t i_port_direction;\n+\tuint8_t rsv3[2];\n+};\n+\n+struct hns3_cfg_com_tqp_queue_cmd {\n+\tuint16_t tqp_id;\n+\tuint16_t stream_id;\n+\tuint8_t enable;\n+\tuint8_t rsv[19];\n+};\n+\n+#define HNS3_TQP_MAP_TYPE_PF\t\t0\n+#define HNS3_TQP_MAP_TYPE_VF\t\t1\n+#define HNS3_TQP_MAP_TYPE_B\t\t0\n+#define HNS3_TQP_MAP_EN_B\t\t1\n+\n+struct hns3_tqp_map_cmd {\n+\tuint16_t tqp_id; /* Absolute tqp id for in this pf */\n+\tuint8_t tqp_vf; /* VF id */\n+\tuint8_t tqp_flag; /* Indicate it's pf or vf tqp */\n+\tuint16_t tqp_vid; /* Virtual id in this pf/vf */\n+\tuint8_t rsv[18];\n+};\n+\n+struct hns3_config_max_frm_size_cmd {\n+\tuint16_t max_frm_size;\n+\tuint8_t min_frm_size;\n+\tuint8_t rsv[21];\n+};\n+\n+enum hns3_mac_vlan_tbl_opcode {\n+\tHNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */\n+\tHNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */\n+\tHNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */\n+\tHNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */\n+};\n+\n+enum hns3_mac_vlan_add_resp_code {\n+\tHNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */\n+\tHNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */\n+};\n+\n+#define HNS3_MC_MAC_VLAN_ADD_DESC_NUM\t3\n+\n+#define HNS3_MAC_VLAN_BIT0_EN_B\t\t0\n+#define HNS3_MAC_VLAN_BIT1_EN_B\t\t1\n+#define HNS3_MAC_EPORT_SW_EN_B\t\t12\n+#define HNS3_MAC_EPORT_TYPE_B\t\t11\n+#define HNS3_MAC_EPORT_VFID_S\t\t3\n+#define HNS3_MAC_EPORT_VFID_M\t\tGENMASK(10, 3)\n+#define HNS3_MAC_EPORT_PFID_S\t\t0\n+#define HNS3_MAC_EPORT_PFID_M\t\tGENMASK(2, 0)\n+struct hns3_mac_vlan_tbl_entry_cmd {\n+\tuint8_t\t flags;\n+\tuint8_t resp_code;\n+\tuint16_t vlan_tag;\n+\tuint32_t mac_addr_hi32;\n+\tuint16_t mac_addr_lo16;\n+\tuint16_t rsv1;\n+\tuint8_t entry_type;\n+\tuint8_t mc_mac_en;\n+\tuint16_t egress_port;\n+\tuint16_t egress_queue;\n+\tuint8_t rsv2[6];\n+};\n+\n+#define HNS3_TQP_RESET_B\t0\n+struct hns3_reset_tqp_queue_cmd {\n+\tuint16_t tqp_id;\n+\tuint8_t reset_req;\n+\tuint8_t ready_to_reset;\n+\tuint8_t rsv[20];\n+};\n+\n+#define HNS3_CFG_RESET_MAC_B\t\t3\n+#define HNS3_CFG_RESET_FUNC_B\t\t7\n+struct hns3_reset_cmd {\n+\tuint8_t mac_func_reset;\n+\tuint8_t fun_reset_vfid;\n+\tuint8_t rsv[22];\n+};\n+\n+#define HNS3_DEFAULT_TX_BUF\t\t0x4000 /* 16k bytes */\n+#define HNS3_TOTAL_PKT_BUF\t\t0x108000 /* 1.03125M bytes */\n+#define HNS3_DEFAULT_DV\t\t\t0xA000 /* 40k byte */\n+#define HNS3_DEFAULT_NON_DCB_DV\t\t0x7800 /* 30K byte */\n+#define HNS3_NON_DCB_ADDITIONAL_BUF\t0x1400 /* 5120 byte */\n+\n+#define HNS3_TYPE_CRQ\t\t\t0\n+#define HNS3_TYPE_CSQ\t\t\t1\n+\n+#define HNS3_NIC_SW_RST_RDY_B\t\t16\n+#define HNS3_NIC_SW_RST_RDY\t\t\tBIT(HNS3_NIC_SW_RST_RDY_B)\n+#define HNS3_NIC_CMQ_DESC_NUM\t\t1024\n+#define HNS3_NIC_CMQ_DESC_NUM_S\t\t3\n+\n+#define HNS3_CMD_SEND_SYNC(flag) \\\n+\t((flag) & HNS3_CMD_FLAG_NO_INTR)\n+\n+void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);\n+void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,\n+\t\t\t\tenum hns3_opcode_type opcode, bool is_read);\n+int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);\n+int hns3_cmd_init_queue(struct hns3_hw *hw);\n+int hns3_cmd_init(struct hns3_hw *hw);\n+void hns3_cmd_destroy_queue(struct hns3_hw *hw);\n+void hns3_cmd_uninit(struct hns3_hw *hw);\n+\n+#endif /* _HNS3_CMD_H_ */\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex 0587a9c..4f4de6d 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -29,6 +29,7 @@\n #include <rte_log.h>\n #include <rte_pci.h>\n \n+#include \"hns3_cmd.h\"\n #include \"hns3_ethdev.h\"\n #include \"hns3_logs.h\"\n #include \"hns3_regs.h\"\n@@ -36,12 +37,70 @@\n int hns3_logtype_init;\n int hns3_logtype_driver;\n \n+static int\n+hns3_init_pf(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_device *dev = eth_dev->device;\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Get hardware io base address from pcie BAR2 IO space */\n+\thw->io_base = pci_dev->mem_resource[2].addr;\n+\n+\t/* Firmware command queue initialize */\n+\tret = hns3_cmd_init_queue(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init cmd queue: %d\", ret);\n+\t\tgoto err_cmd_init_queue;\n+\t}\n+\n+\thns3_clear_all_event_cause(hw);\n+\n+\t/* Firmware command initialize */\n+\tret = hns3_cmd_init(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init cmd: %d\", ret);\n+\t\tgoto err_cmd_init;\n+\t}\n+\n+\treturn 0;\n+\n+err_cmd_init:\n+\thns3_cmd_destroy_queue(hw);\n+\n+err_cmd_init_queue:\n+\thw->io_base = NULL;\n+\n+\treturn ret;\n+}\n+\n+static void\n+hns3_uninit_pf(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n+\tstruct rte_device *dev = eth_dev->device;\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);\n+\tstruct hns3_hw *hw = &hns->hw;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\thns3_cmd_uninit(hw);\n+\thns3_cmd_destroy_queue(hw);\n+\thw->io_base = NULL;\n+}\n+\n static void\n hns3_dev_close(struct rte_eth_dev *eth_dev)\n {\n \tstruct hns3_adapter *hns = eth_dev->data->dev_private;\n \tstruct hns3_hw *hw = &hns->hw;\n \n+\thw->adapter_state = HNS3_NIC_CLOSING;\n+\thns3_uninit_pf(eth_dev);\n \thw->adapter_state = HNS3_NIC_CLOSED;\n }\n \n@@ -69,9 +128,20 @@ hns3_dev_init(struct rte_eth_dev *eth_dev)\n \n \thns->is_vf = false;\n \thw->data = eth_dev->data;\n+\n+\tret = hns3_init_pf(eth_dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init pf: %d\", ret);\n+\t\tgoto err_init_pf;\n+\t}\n+\n \thw->adapter_state = HNS3_NIC_INITIALIZED;\n \n \treturn 0;\n+\n+err_init_pf:\n+\teth_dev->dev_ops = NULL;\n+\treturn ret;\n }\n \n static int\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex bfb54f2..84fcf34 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -39,7 +39,6 @@\n \n #define HNS3_4_TCS\t\t\t4\n #define HNS3_8_TCS\t\t\t8\n-#define HNS3_MAX_TC_NUM\t\t\t8\n \n #define HNS3_MAX_PF_NUM\t\t\t8\n #define HNS3_UMV_TBL_SIZE\t\t3072\n@@ -327,6 +326,7 @@ struct hns3_reset_data {\n struct hns3_hw {\n \tstruct rte_eth_dev_data *data;\n \tvoid *io_base;\n+\tstruct hns3_cmq cmq;\n \tstruct hns3_mac mac;\n \tunsigned int secondary_cnt; /* Number of secondary processes init'd. */\n \tuint32_t fw_version;\n", "prefixes": [ "04/22" ] }